SU1167692A2 - Frequency multiplier - Google Patents

Abstract

MUNOZHITELB FREQUENCIES1 on author. St. No. 1061236, characterized in that, in order to increase the frequency multiplication accuracy when frequency-modulated pulses arrive at the frequency multiplier input, one comparator output is connected to the first input of the third match element via the fifth matching element introduced in series and the first trigger of the comparator connected to the first input of the fourth match element through the sixth matching element entered in series and the second trigger, and also connected in series The combined element, the third trigger and the seventh match element, the output of which is connected to the second inputs of the first, second and third flip-flops, while the second output of the third trigger is connected to the additional third inputs of the third and fourth match elements, the outputs of which are connected respectively to the first and second inputs the combining element, and the second inputs of the fifth and sixth elements of the match are connected to the input of the second frequency divider, the output of which is also connected to the second input of the seventh element Denis. (/}

Description

The invention relates to a pulse technique, namely to devices for multiplying the frequency and tracking the change in the input frequency, and can be used in various radio devices.

According to the main author. St. No. 1061236 is known a frequency multiplier comprising a series-connected delay line, a first standby multivibrator, a first frequency divider, a second standby multivibrator, a first inverter and a phase meter, a series-connected reversing counter, a code-voltage converter and a controlled oscillator, and a second frequency divider, the second inverter, the first and second coincidence elements, the first inputs of which are connected to the outputs of the phase meter, and the outputs are connected respectively to the summing and subtracting inputs of the reversing c The second input of the second matching element is connected to the output of the second inverter, and the third input to the output of the second standby multivibrator, while the inputs of the delay line, the second frequency divider, the second inverter and the second inputs of the phase meter and the first match element are combined and are the input of the frequency multiplier , the comparator, the source of reference voltages, the third and fourth elements of the match and the series-connected reverse shift register and frequency divider with a variable division factor, the first the comparator input is connected to the code-voltage converter output, the second and third inputs are connected to the source outputs of the reference voltages, and the outputs are connected to the first inputs of the third and fourth match elements, the second inputs of which are connected to the output of the second frequency divider, and the outputs respectively to summing and subtracting inputs of the reverse shift register, with the output of the controlled generator connected to the signal input of a frequency divider with a variable division factor, the output of which is connected to the signal input the first frequency divider and is the output of frequency multiplier 1.

However, in the known frequency multiplier, when frequency-modulated pulses arrive at its input, the error in the frequency multiplication is increased due to the low reliability of the selection of the required division factor of the frequency divider with a variable division factor.

The purpose of the invention is to increase the frequency multiplication accuracy when frequency-modulated pulses arrive at the frequency multiplier input.

The goal is achieved by the fact that in a known frequency multiplier, which contains a serially connected delay line, the first multivibrator is waiting, the first frequency divider, the second is waiting multivibrator, the first inverter and phase meter, a series-connected reversible counter, a code-voltage converter and a controlled oscillator, as well as the second frequency divider, the second inverter, the first and second elements of the match, the first inputs of which are connected to the outputs of the phase meter, and the outputs are connected respectively to the summing and subtracting inputs of down counter, a second input of the second coincidence element connected to the output of the second inverter, the third input - to the output of the second monostable multivibrator, the input of the delay line, a second frequency divider, the second inverter and a second input

The 2 phase meters and the first match element are combined and are the input of the frequency multiplier, the comparator, the source of the reference voltages, the third and fourth match elements, and the reversing shift register and the divider connected in series

0 frequencies with a variable division factor, with the first input of the comparator connected to the output of the code converter, the second and third inputs to the outputs of the source of the reference voltages, and the outputs to the first inputs of the third and fourth elements of the match, the second inputs of which are connected to the output of the second frequency divider, and outputs - respectively to the summing and subtracting inputs of the reverse shift register, with

Q this output of the controlled oscillator is connected to the signal input of a frequency divider with a variable division factor, the output of which is connected to the signal input of the first frequency divider and is the output of a frequency multiplier, one output

5, the comparator is connected to the first input of the third match element through the fifth match element entered in series and the first trigger, the other output of the comparator is connected to the first input of the fourth match element via

0 entered in series the sixth match element and the second trigger, as well as the successively connected combination element, the third trigger and the seventh match element, the output of which is connected to the second inputs of the first, second and third triggers, and the second output of the third trigger the third and fourth elements of the match, the outputs of which are connected respectively to the first and second inputs of the combination element, and the second inputs of the fifth and sixth elements Adenomas are connected to the input of the second frequency divider, whose output is also connected to the second input of the seventh member matcher.

5 In FIG. Figure 1 shows a structural electrical frequency multiplier circuit; in fig. 2 - timing diagrams for the operation of the frequency multiplier.

The frequency multiplier contains delay line 1, the first and second standby multivibrators 2 and 3, the first and second frequency dividers 4 and 5, the first and second inverters 6 and 7, the first and second elements of coincidence 8 and 9, the phase meter 10, the reversing counter 11 / converter code-voltage 12, controlled oscillator 13, source of reference voltages 14, comparator 15, third and fourth elements of coincidence 16 and 17, reversing shift register 18 and variable frequency division divider (DFD) 19, fifth, scattering and the seventh match elements 20, 21 and 22, the first, in Ora and third flip-flops 23, 24 and 25, the combining member 26, inlet 27 and outlet 28 frequency multiplier.

The frequency multiplier works as follows.

Triggers 23, 24, and 25 are enabled by the BK scheme.

The second frequency divider 5 must have a division factor not less than the conversion factor of the reversible counter 11.

The reverse shift register 18 has n bits, one of which is set to "one state, and the rest is set to" zero, the size is determined by the ratio

Hmm

P .

where KBX is the overlap factor

input frequency; Kge is the overlap ratio of the modulated part of the controlled generator 13.

The division ratio of DPKD 19 can be Kd1i d Kg € nIli Kdp1dg Kge "(p-1),

where is the orderly connection of the PDCD control input to the "one bit of the reverse shift register 18. The proposed frequency multiplier operates on the principle of phase comparison with the subsequent frequency balancing of the pulses generated by the multiplier circuit to the input ones. A phase comparison is made by a phase meter 10, made on the basis of a 1-K trigger, at the first input of which pulses are fed to exit 28 through the first frequency divider 4, having a division factor N equal to the multiplication factor, the second waiting multivibrator 3 and the first inverter 6, and The second input receives pulses from input 27. In this case, depending on the phase position of the input and output pulses, the phase meter 10 passes pulses to the summing or subtracting inputs through the first 8 or 9 second matching elements Field counter 11, thereby changing the code value at the input of the code-voltage converter 12, which sets the operating point of frequency shaping to the controlled oscillator 13.

From the output of the converter, the code-voltage 12, a voltage proportional to the output frequency of the controlled oscillator 13, is supplied to the comparator 15, where it is compared with the reference values Vwm and VHOKC. (Fig. 2L) corresponding to the boundary values of freuMi and the gene.nvs of the linear portion of the characteristic of the controlled oscillator 13. If the voltage value at the output of the code-voltage converter 12 does not go beyond the linear portion of the modulation characteristic of the controlled oscillator 13, then at the outputs of the comparator 15 there will be a constant potential that prohibits the passage through the fifth and sixth elements of the coincidence of 20 and 21 pulses from the input 27 to the first inputs 0 of the first and second triggers 23 and 24, and hence at the first inputs of the third and the fourth coincidence elements 16 and 17 will be supported by the inhibitory potential for the passage of pulses from the output of the second frequency divider 5 to the summing or

5 subtracting input of the reverse shift register 18 controlling the division ratio of the CCD 19.

In this case (if the voltage value at the output of the converter code-voltage 12 does not exceed the limits of the linear section

0 the modulation characteristic of the controlled oscillator, 13) the division ratio of the CCD 19 will maintain its constant value.

If the voltage value at the output of the converter code-voltage 12 at least in the interval of one period of the following impulses goes beyond the limits VMKH-V aKc, then the corresponding division factor of the PDKD 19 is automatically adjusted, thus switching the operating point of the controlled generator to linear plot characteristics.

FIG. Figure 2 shows the process of tuning the frequency multiplier when the input signal is frequency modulated and only the lower frequency band does not correspond to the linear portion of the modulation characteristic of the controlled oscillator 13 (Fig. 2, interval ti-12), and the switching pulses at the output of the second frequency divider 5 are generated at the moments corresponding to the linear section of the modulation characteristic (Fig. 2, points ts and 1b).

In the initial state (Fig. 2d, e, g, in the to-ti interval), the triggers 23, 24, and 25 are set so that the first inputs 5 of the third, fourth, and seventh elements of the matches 16, 17, and 22 have forbidding potentials for passing through them switching pulses, and at the third inputs of the third and fourth elements of the coincidence 16 and 17 there are resolving potentials. At time ti, when the voltage at the output of the converter code-voltage 12 crosses the boundary (Fig. 2L), the first potential of the comparator 15 is formed (see Fig. 2c) for passing the input pulses (Fig. 2a) through the fifth coincidence element 20 to the first input of the first trigger 23 (Fig. 2d). On the first pulse, the trigger 23 is energized and at its output a resolving potential (Fig. 2e) is formed to pass the switching pulses (Fig. 26) generated by the second frequency divider 5 through the third coincidence element 16 (Fig. 2z) to the summing input of the reverse shift register 18 and to the first input of the combining element 26. In the reverse shift register 18, the leading edge of the input pulse shifts a unit to the next bit, which increases the division ratio of the DCPD with a corresponding jump. The DPKD 19 program reduces the pulse frequency at output 28 (Fig. 2n, point ts) and at the first input of the phase meter 10. To provide frequency balancing between the input pulses and the pulses arriving at the first input of the phase meter 10, it gives the command to work the reverse account Punch 11 in addition mode, which causes a rise in voltage at the output of the code-voltage converter 12 (Fig. 2L, ta-is interval), ensuring that the operating point of the controlled generator 13 is transferred to the linear portion of the modulation characteristic (Fig. 2m). After the frequency multiplier circuit enters the dynamic equilibrium mode at the output 28 (fig.2n from the moment to), a significant decrease in the frequency multiplication error is observed. At the same time, a switching pulse transmitted through combining element 26, with a falling edge (Fig. 2i, point t4), triggers the third trigger 25, which closes the third and fourth coincidence circuits 16 and 17 (Fig. 2e) and opens the seventh coincidence element 22 ( Fig. 2g). In this case, the next switching pulse (Fig. 26, point te) does not pass through the third match element 16, which eliminates an additional "one" shift in the reverse shift register 18, but passes through the seventh match element 22 to the second inputs of the first, second and third triggers 23 , 24 and 25 (Fig. 2k, point te), set them to their original state. After that, the device is ready for the next analysis of the voltage value at the output of the converter, voltage 12, and subsequent correction of the division ratio of the DPD 19. The process of operation of the frequency multiplier is similar, when the voltage at the output of the code-voltage converter 12 crosses Umax. Only in this case, the input pulses, the passage through the sixth match element 21, cocks the second trigger 24, which opens the fourth match element 17, which transmits the switching pulses to the subtracting input of the reverse shift register 18, which gives the command to reduce the division ratio of the CWD 19. Thus, the proposed frequency multiplier provides for the rearrangement of the PDCD division factor when multiplying the pulse sequence unmodulated and modulated in frequency, which allows tnym frequency multiplier, the received for the base object to produce multiplication input pulse sequence with a frequency deviation y ,, L Dgen.naksu hgen.mii prototype tests showed that the multiplication of the input signal to the next deviation f 2 gene. NIN is produced only in the linear region of the modulation characteristic of the controlled signal. At the same time, compared with the base object in this frequency multiplier, the multiplication accuracy increased more than 3 times. Practical use of this frequency multiplier is most advisable in multichannel magnetic recording systems operated in adverse conditions on autonomous systems without the presence of an operator, when exposed to destabilizing factors, in particular in conditions where the input frequencies can take arbitrary values with a frequency deviation to { Gen. Aax 100%. Cost-effective is the refinement in accordance with the proposed solution of previously released and commercially available frequency multipliers. The revision is associated with insignificant material costs. When operating the proposed frequency multiplier, there is no need for the presence of an operator, accuracy and speed are increased.

but

P I 1 I I I II I I I and they I I I I I I I I I I I I 111

I I I I I

l

m

n

.-Nffx

/ X

.

 5 (iz, 2

Claims (1)

FREQUENCY FREQUENCY by ed. St. No. 1061236, characterized in that, in order to increase the accuracy of the frequency multiplication when the frequency modulated pulses arrive at the input of the frequency multiplier, one comparator output is connected to the first input of the third coincidence element through the fifth coincidence element and the first trigger connected in series, the other comparator output is connected to the first input of the fourth coincidence element through the sixth coincidence element and the second trigger entered in series and connected in series combining moment, the third trigger and the seventh coincidence element, the output of which is connected to the second inputs of the first, second and third triggers, while the second output of the third trigger is connected to the additional third inputs of the third and fourth coincidence elements, the outputs of which are connected respectively to the first and second inputs of the element combining, and the second inputs of the fifth and sixth coincidence elements are connected to the input of the second frequency divider, the output of which is also connected to the second input of the seventh coincidence element. 05 M 05 SO Figure 1