CA1086866A - Self protection against breakover turn-on failure in thyristors - Google Patents
Self protection against breakover turn-on failure in thyristorsInfo
- Publication number
- CA1086866A CA1086866A CA280,370A CA280370A CA1086866A CA 1086866 A CA1086866 A CA 1086866A CA 280370 A CA280370 A CA 280370A CA 1086866 A CA1086866 A CA 1086866A
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- thyristor
- subtransistor
- carrier lifetime
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- 239000002800 charge carrier Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001965 increasing effect Effects 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 239000007787 solid Substances 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 150000001768 cations Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
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- 229910052697 platinum Inorganic materials 0.000 description 2
- 241000478345 Afer Species 0.000 description 1
- 244000187656 Eucalyptus cornuta Species 0.000 description 1
- 241000283986 Lepus Species 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A semiconductor device protected against breakover turn-on failure and operative in connection with applying voltage and generating electrical currents. The device has a silicon base substrate. The substrate has a main thyris-tor region with at least a main emitter area. A gate region is associated with the main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in the gate region. The gate region includes a localized subtransistor. The subtransistor has a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of the main thyristor region. This, the location of the initial current conduction under the conditions of excessive forward voltage is limited to the gate region. The device permits control of the location of the turn-on point.
A semiconductor device protected against breakover turn-on failure and operative in connection with applying voltage and generating electrical currents. The device has a silicon base substrate. The substrate has a main thyris-tor region with at least a main emitter area. A gate region is associated with the main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in the gate region. The gate region includes a localized subtransistor. The subtransistor has a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of the main thyristor region. This, the location of the initial current conduction under the conditions of excessive forward voltage is limited to the gate region. The device permits control of the location of the turn-on point.
Description
2 ¦ 10~86F
3~ This inYention relates to the fabrication of solid state 41 devices and relates particularly to self-protection of thyristor devices an~ the li~e.
6 A thyristor is a solid state device havlng alternate 7 layers of ~ type and N type semiconductor materials. A thyristor 8 is typically a disc of four alternating layers of ~l and P type 9 silicon, the layers and junctions between them being formed by precision gaseous diffusion, substrate fusion and/or alloying 11 techni~ues. A thyristor has generally three electrodes, referred 12 to as the cathode, the anode, and the gate, the gate being the 13 control electrode for the device. During normal operation, the 14 thyristor is turned on by at least momentary application of a forward bias gate-to-cathode voltage. The device remains on 16 until the anode-to-cathode voltage is reduced to a value below l? that required to sustain regeneration, or forward current.
18 The thyristor may also be turned on without a voltage 19 applied to the gate if the anode-to-cathode voltage exceeds a value inherent in the device design. This phenomenon is known 21 as voltage breakover turn-on. The main emitter area in the 22 cathode of a thyristor is prone to failure during breakover 23 turn-on initiated by such excess device voltage. The location 24 of the turn-on point within the device is not usually subject to control. As a result, the turn-on point may often occur 26 within the cathode emitter in a manner causing permanent device 27 failure. .
28 The device turn-on criterion, which is based on the 29 current gain of the transistor formed by the anode layer, the anode base layer and the cathode base layer of the thyristor 31 device, is approximated to the first order as the product of 32 `'~
1 2.' iO81~8~
the anode base transport factor aT and the avalanche multi-plication factor M. (~trictly speaking, the turn-on criterion is the product of the current gain factor, ~0, and the multi-plication factor, M. However, because current gain, ~0, is the product of the anode base transport factor,~ T~ and the emitter efficiency, ~E~ of the anode emitter, which is close to unity and does not vary strongly with voltage, to the first order ~o~r~ Therefore, the subscript may be ignored and the terms current gain and base transport factor may be used interchange-ably.) Both the base transport factor and the avalanche multi-plication factor are voltage sensitive parameters. An excess forward voltage will cause the product~.~q to prematurely exceed unity within selected regions of the thyristor, resulting in a local current gain approaching infinity. Device turn-on in this lS manner often causes device failure.
In the past, there have been two basic methods for protecting against voltage breakover turn-on failure. In the first method, external circuitry is connected between the anode and the gate which has a breakover voltage below that of the internal emitter to be protected. As voltage between the anode and cathode approaches the breakover level, the resulting avalanche current in the external circuitry becomes the gate current of the thyristor, thereby firing the thyristor normally. One of the major shortcomings of this type of breakover protection is the need for additional external circuit components, with the result-ant increased expense and system size.
A second method involves the use of internal auxiliary fabrication techniques, wherein the silicon wafer from which the N type base region is fabricated is prepared so that the highest donor concentration is located precisely below the area for the gate contact. This method is described in an article by Peter 1b 3 , - ' . ' ' ' ~0868~;6 Voss, Solid State Electronics, ~olume 2~, page 265 (1974).
In the Voss method, the dependence of the avalanche break-down characteristic on donor concentration assures that the doped region is the first region in which breakdown can occur, there~y protecting against voltage breakover turn-on fail~re in any other-region of the thyristor.
Thyristors and many other semiconductor devices are fabricated from a wafer of silicon, initially of high purity, which is characterized by a long charge carrier lifetime. In the course of fabrication it is common prac-tice to uniformly irradiate-the wafer or to introduce a lifetime reducing impurity uniformly into the water surface to modify the characteristic of the silicon ~afer. This technique can be adapted to ad~antage as hereinafter des-cribed.
Accordingly, the invention is a semiconductordevice protected against breakover turn-on failure and operative in connection~with means for applying voltage and for generating electrical curr~nts comprising a sil-icon base substrate having: a main thyristor region with at least a main emitter area; a gate region-operatively associated with said main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in said gate region, said gate region including a localized subtransistor, said subtransistor being charac-terized by a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of said main thyristor region such that the location of initial current conduction under conditions of excessive forward 3~ voltage is limited.
.
68~6 In a further aspect the invention is a thyristor semiconductor device protected against voltage breakover failure, said device being for use in connection with means for applying voltage and for generating electrical currents and comprising a silicon substrate having on an obverse face an anode contact and on a reverse face a cathode contact and a gate contact, said gate contact being spaced laterally from said cathode contact, said substrate including a main thyristor region between the anode contact and the cathode contact, a gate subtransistor region between the anode contact and the gate contact and a gate emitter region substrate between the gate contact and the cathode contact establishing a pilot thyristor region, said pilot thyristor region being operatively coupled to said main thyristor region to turn on said main thyristor region when said pilot thyristor region is turned on, said gate subtransistor region being characterized by a locally longer minority carrier lifetime than the minority carrier lifetime in any area of the main thyristor region, such that excessive forward voltage causes currents initially to flow only in the gate subtransistor region and act to turn on said pilot thyristor region.
The invention will be best understood by reference to the following detailed description of preferred embodi-ments, taken in conjunction with the following drawings, inwhich:
Figure 1 is a schematic cross-section illustrating a section of an amplifying gate type thyristor device constructed according to the present invention;
10868~;6 Figure 2 shows cross-sections of silicon wafers illustrating the steps of fabrication of a device according to the invention by a first preferred method;
Figure 3 illustrates a second preferred method for fabrication of a device according to the invention;
Figure 4 illustrates a third preferred ~ethod for fabrication of a device according to the invention; and Fig~re 5 illustrates a fourth preferred ~ethod of fabrication of a device according to the invention.
A semiconductor thyristor 10 according to the invention is shown in Figure 1. The thyristor 10 co~prises an anode contact 12, a cathode contact 14, and a gate contact 16 in ohmic contact with first and second sides of a generally disc shaped silicon wafer substrate 18. The gate contact 16 is typically located near the center of the substrate 18, and in some designs it may be surrounded by an annular cathode contact 14.
The thyristor 10 comprises distinct joined semi-conductor -5a-10~16866 ll layers. The semiconductor layera are designated the anode base 2 or wide base or simply the NbaSe layer 22, the anode P or Panode 3 layor 24, the ca~hode base or P~ase layer 26 and d~scontinuou~
6 A thyristor is a solid state device havlng alternate 7 layers of ~ type and N type semiconductor materials. A thyristor 8 is typically a disc of four alternating layers of ~l and P type 9 silicon, the layers and junctions between them being formed by precision gaseous diffusion, substrate fusion and/or alloying 11 techni~ues. A thyristor has generally three electrodes, referred 12 to as the cathode, the anode, and the gate, the gate being the 13 control electrode for the device. During normal operation, the 14 thyristor is turned on by at least momentary application of a forward bias gate-to-cathode voltage. The device remains on 16 until the anode-to-cathode voltage is reduced to a value below l? that required to sustain regeneration, or forward current.
18 The thyristor may also be turned on without a voltage 19 applied to the gate if the anode-to-cathode voltage exceeds a value inherent in the device design. This phenomenon is known 21 as voltage breakover turn-on. The main emitter area in the 22 cathode of a thyristor is prone to failure during breakover 23 turn-on initiated by such excess device voltage. The location 24 of the turn-on point within the device is not usually subject to control. As a result, the turn-on point may often occur 26 within the cathode emitter in a manner causing permanent device 27 failure. .
28 The device turn-on criterion, which is based on the 29 current gain of the transistor formed by the anode layer, the anode base layer and the cathode base layer of the thyristor 31 device, is approximated to the first order as the product of 32 `'~
1 2.' iO81~8~
the anode base transport factor aT and the avalanche multi-plication factor M. (~trictly speaking, the turn-on criterion is the product of the current gain factor, ~0, and the multi-plication factor, M. However, because current gain, ~0, is the product of the anode base transport factor,~ T~ and the emitter efficiency, ~E~ of the anode emitter, which is close to unity and does not vary strongly with voltage, to the first order ~o~r~ Therefore, the subscript may be ignored and the terms current gain and base transport factor may be used interchange-ably.) Both the base transport factor and the avalanche multi-plication factor are voltage sensitive parameters. An excess forward voltage will cause the product~.~q to prematurely exceed unity within selected regions of the thyristor, resulting in a local current gain approaching infinity. Device turn-on in this lS manner often causes device failure.
In the past, there have been two basic methods for protecting against voltage breakover turn-on failure. In the first method, external circuitry is connected between the anode and the gate which has a breakover voltage below that of the internal emitter to be protected. As voltage between the anode and cathode approaches the breakover level, the resulting avalanche current in the external circuitry becomes the gate current of the thyristor, thereby firing the thyristor normally. One of the major shortcomings of this type of breakover protection is the need for additional external circuit components, with the result-ant increased expense and system size.
A second method involves the use of internal auxiliary fabrication techniques, wherein the silicon wafer from which the N type base region is fabricated is prepared so that the highest donor concentration is located precisely below the area for the gate contact. This method is described in an article by Peter 1b 3 , - ' . ' ' ' ~0868~;6 Voss, Solid State Electronics, ~olume 2~, page 265 (1974).
In the Voss method, the dependence of the avalanche break-down characteristic on donor concentration assures that the doped region is the first region in which breakdown can occur, there~y protecting against voltage breakover turn-on fail~re in any other-region of the thyristor.
Thyristors and many other semiconductor devices are fabricated from a wafer of silicon, initially of high purity, which is characterized by a long charge carrier lifetime. In the course of fabrication it is common prac-tice to uniformly irradiate-the wafer or to introduce a lifetime reducing impurity uniformly into the water surface to modify the characteristic of the silicon ~afer. This technique can be adapted to ad~antage as hereinafter des-cribed.
Accordingly, the invention is a semiconductordevice protected against breakover turn-on failure and operative in connection~with means for applying voltage and for generating electrical curr~nts comprising a sil-icon base substrate having: a main thyristor region with at least a main emitter area; a gate region-operatively associated with said main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in said gate region, said gate region including a localized subtransistor, said subtransistor being charac-terized by a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of said main thyristor region such that the location of initial current conduction under conditions of excessive forward 3~ voltage is limited.
.
68~6 In a further aspect the invention is a thyristor semiconductor device protected against voltage breakover failure, said device being for use in connection with means for applying voltage and for generating electrical currents and comprising a silicon substrate having on an obverse face an anode contact and on a reverse face a cathode contact and a gate contact, said gate contact being spaced laterally from said cathode contact, said substrate including a main thyristor region between the anode contact and the cathode contact, a gate subtransistor region between the anode contact and the gate contact and a gate emitter region substrate between the gate contact and the cathode contact establishing a pilot thyristor region, said pilot thyristor region being operatively coupled to said main thyristor region to turn on said main thyristor region when said pilot thyristor region is turned on, said gate subtransistor region being characterized by a locally longer minority carrier lifetime than the minority carrier lifetime in any area of the main thyristor region, such that excessive forward voltage causes currents initially to flow only in the gate subtransistor region and act to turn on said pilot thyristor region.
The invention will be best understood by reference to the following detailed description of preferred embodi-ments, taken in conjunction with the following drawings, inwhich:
Figure 1 is a schematic cross-section illustrating a section of an amplifying gate type thyristor device constructed according to the present invention;
10868~;6 Figure 2 shows cross-sections of silicon wafers illustrating the steps of fabrication of a device according to the invention by a first preferred method;
Figure 3 illustrates a second preferred method for fabrication of a device according to the invention;
Figure 4 illustrates a third preferred ~ethod for fabrication of a device according to the invention; and Fig~re 5 illustrates a fourth preferred ~ethod of fabrication of a device according to the invention.
A semiconductor thyristor 10 according to the invention is shown in Figure 1. The thyristor 10 co~prises an anode contact 12, a cathode contact 14, and a gate contact 16 in ohmic contact with first and second sides of a generally disc shaped silicon wafer substrate 18. The gate contact 16 is typically located near the center of the substrate 18, and in some designs it may be surrounded by an annular cathode contact 14.
The thyristor 10 comprises distinct joined semi-conductor -5a-10~16866 ll layers. The semiconductor layera are designated the anode base 2 or wide base or simply the NbaSe layer 22, the anode P or Panode 3 layor 24, the ca~hode base or P~ase layer 26 and d~scontinuou~
4 layers 28 and 30. The layer 28 is known as the main emitter g layer 28 and the layer 30 which is between the cathode contact 6 14 and the gate contact 16 is known as the gate emitter or pilot 7 thyristor emitter layer 30.
8 The anode base layer 22 is sandwiched between the anode 9 layer 24 and the cathode base layer 26. The anode layer 24 is in I0 ohmic contact through metallization of the anode contact 12. The II emitter layers 28 and 30 may be a high dopant concentration N-type 12 semiconductor fused or diffused over portions of the cathode base 13 layer 26. The cathode base layer 26 is in ohmic contact with 14 metallization of the cathode 14 through shorts in the main emitter -:~
I5 layer 28 and with metallization of the gate contact 16. The ~:
I6 anode base layer ~hares a relatively large semiconductor junction I~ 32 with the cathode base layer 26 and a further relati~ely large I8 semiconductor junction 34 with the anode layer 24. The cathode :
I9 base layer shares semiconductor junctions 36 and.38 with emitter layers 28 and 30.
21 Thyristor 10 is further characterized by a number of 22 operating regions. The region between the area of the gate 23 contact 16 and the anode contact 12 which roughly corresponds to 24 the area under the gate contact 16 is designated the gate region .
2~ 40. The region roughly corresponding to the area under the gate 26 emitter layer 30 is designated the gate or pilot thyristor region 27 42. The relatively broad area between the cathode contact 14 and 28 the anode contact 12 is generally known as the main thyristor 29 region 43. .
Thyristor 10 shown in FIG. 1 is known as an amplifying 3I gate thyristor because of the presence of the pilot thyristor 32 region 41. A sub~ransistor iQ defined by gate region 40 as 6``' . ", .
iO~8~;6 11 indicated by the phantom line through layers 26, 22 and 24. In 2 ! proper operation, the gate or pilot thyristor 41 is initially 31 turned on by the lateral flow of current betwee~ the yate contact 41 16 and the cathode contact 14. Once the pilot th~ristor 41 is 51 on,the main thyristor 43 is turned on by ga~e-to-cathode current 6, plus current flowing between the anode contact 12 belo-~ the gat 71 emitter region 30 and the cathode contact 14. According to the 8¦ method of thP present invention, control of the local gain 9 ¦characteristics interior to the gate emitter region 30, i.e. in 10¦ the gate region 40, inhibits device failure due to voltage brea~-11 ¦over caused by excessive forward voltage between the anode 12 and 12 the cathode 14. Regional gain control resu~s in an operational 13 geometry which causes the current through the subtransistor in 14l gate region 40 first to turn on the pilot thyristor region41 and 15¦ thereafter the main thyristor region 43 if excessive forward 161 voltage occurs. In structures omitting the pilot thyristor region ~71 the geometry is such that the main thyristor region 43 is turned i8¦ on by the current resulting from the excessive forward current.
19 The operation of the thyristor 10 is defined by well-known localized semiconductor characteristics. For example, the 21 turn-on point along the N-P junction 32 is determined by the pro-22 duct of the localized base transport factor , which approximates -23l the current gain characteristic~ and of the avalanche multipli-24 cation factor M. At the point ~.M first equals or exceeds uni~
along the N-P junction 32, avalanche current beings to flow.
26 The multiplication factor M and the transport factor are 27 both voltage dependent. The transport factor is approximated by 28 the equation:
30 ~ (V) = 2 tl) -31 exp (W(V) ) + exp ~ ) .
_ 10~6866 1 ¦ where:
2 WtV) is the undepleted base width at applied voltage;
3 and Lp is the base minority carrier diffusion length 4 in ~he NbaSe layer 22- .
6 Lp is defined by the expression:
7 Lp = ~D ~ )l/2 ~2 8 where: .
9 Dp is the characteristic minority charge-carrier difusio :-coefficient in the NbaSe material; and :
Tp iS the lifetime of excess minority charge carriers 12 in the NbaSe layer 22- . -~
13 The abrupt junction approximation for the multipli-14 cation factor M is given by the expression:
. .::
M~V) = l (3) -. :
16~
19 where:
V s the applied voltage; and 21 VBR is the characteristic breakdown voltage. :~
22 The abrupt junction approximation is insufficiently 23 accurate in the case of most diffusion formed junctions. More 24 exact expressions are found in the literature and may, for example 25 be found in S.M. Sze, Phvsics of Semiconductor Devices, Wiley .
26 Interscience Press, 1969.
27 The avalanche multiplication factor M and the transport 28 factor ~ may vary locally along the N-P junction 32. For the 29 purposes of explanation, the multiplication factor along the N-P junction 32 external to region 40 is designated MM, the 31 transport factor in the N base layer 22 external to region 40 is 32 designated aM, the ~ultiplication factor in the gate region 40 is 8. .
.
.
~ 10~866 1 ¦ designated MG, and the transport factor in the gate region 40 2 ¦ is designated G~
3 ¦ Since the turn-on criterion is a-M=l, the location of 4 the turn-on point can be controlled by relative modification of ¦ the transport factors aG and aM. Specifically, aG is established 6 according to the invention to be greater than aM, so t~at initial 7 device turn-on is constrained to occ~r in the gate region 40 and 8 along the inner portion of P-N junction 38.
9 An examination of equation (1) above indicates that aG
is physically dependent upon the charge-carrier diffusion length 11 Lp in the regions of interest. Equation (2) indicates that the 12 charge-carrier diffusion length ~p is directly dependent on ~3 charge-carrier lifetime ~p. Therefore, localized modification o 14 the charge-carrler li~etime ~p governs the location of device 15 turn-on. ' 16 FIGS. 2 and 3 illustraté possible methods for achieving 17 the desired control of localized carrier lifetime ~, and there-18 fore of the transport factor a, during fabrication of the '' lg thyristor device 10 illustrated in FIG. 1.
According to the inventive method of FIG. 2, a high 21 purity silicon wafer substrate 42 is first irradiated, for 22 example, with uniform electron irradiation 44 according to well-23 known methods in the art, as shown in (A) of FIG. 2. (See, for 24 example, Tarneia & Johnson, "Tailoring the recovered charge in power diodes using 2MeV electron irradiation," Electrochem.
26 Society Mtg., Paper 261 RNP 1975). This introduces lifetime 27 killing defect centers permeating the wafer 42. Thereafter, 28 the wafer 42 is subjected to localized heat annealling 46 in 2 the gate region 40, as shown in (B) of FIG. 2. The heat anneal-3 ling step 46 anneals out the lifetime killing defect centers in 3i the crystal structure of the wafer 18, thereby increasing 'the 32 lifetime T hence the transport factor a in the gate region 40.
. 9.
1 i ~he temperatures at which heat anneals out defects induced by 2 required irradiation levels for silicon are well known i~ the 3 art and in the literature. The results of the above-described 4 processing steps are localized variations in the charge-carrier lifetime of the silicon substr~te 42, a~ depicted in ~C) of 6 FIG. 2, which results in the relatively higher transport factor, 7 ~G' in the gate region 40.
8 FIG. 3 illl1strates an even simpler and somewhat more 9 versatile method for creating localized variation in the charge carrier lifetime in the silicon substrate 42. As depicted in (A) 11 of FIG. 3, a shield 48 is placed over the gate region 40, ~ ~ -12 whereupon the substrate is irradiated with electrcns or other ~3 defect inducing radiation. As a consequence, the gate region 40 14 under the shield 48 is protected against the creation of lifetime killing defects. The result is a silicon substrate 42 having 16 locally varying charge carrier lifetimes, as depicted in (~) of 17- FIG. 3. , 18 The shield 48 is preferably a removable mask such as 19 lead foil. The shield 48 may be mechanically held in place, a~
necessary.Should modification of the gate region lifetime be 21 desired, the shield 48 may be removed from the gate region 40 22 during a portion of the irradiation process. The method 23 illustrated in FIG. 3 is particularly versatile since the shield 24 48 can be provided for any length of time at any stage in the device fabrication process, but the method is performed most 26 conveniently after junction formation and metallization.
27 FIG. 4 illustrates a further method for creating a 28 desired localized variation in the charge carrier lifetime in 29 the silicon substrate 42. As depicted in (A), a patterned source of lifetime reducing impurities 51 is first deposited on the 31 surfacè of the substrate 42 except in the area of the gate region 32 40. The impurity material may comprise, for example, gold or ' 10, ~ .
;
108fà8~
platinum, and the layer may be emplaced by metal evaporiza-tion or by deposit of a CVD (chemical vapor deposition) glass or spun-on glass containing the impurity. General procedures for gold doping to control lifetime characteris-tics have been discussed in reference to particular applica-tions in the literature. See, for example, Fairfield &
Gokhale, "Control of diffused diode recovery time through ~old doping," Solid State Electronics, Vol. 9, pp. 905-907, 1~66. Such techniques may be adapted to the present method.
After deposition of the impurity layer, diffusion 50 is induced to urge the impurities to migrate into the substrate A2, which creates the desired lifetime-killing defects, as depicted in (B). The result is a substrate 42, depicted in (C), having a gate region of selective high lifetime.
Figure 5 illustrates a still further method for achieving the desired profile of charge carrier lifetime.
As depicted in (A) a layer of lifetime reducing impurity 52, such as gold or platinum, is deposited by ion implantation 53 on the surface of substrate 42 in the regions other than the gate regions 40. Thereafter, the impurity is diffused into the substrate 42, as depicted in (B). Consequently, a locally higher lifetime and hence a higher gate region transport factor is created, as depicted in (C).
Gold doping is a relatively straightforward means for controlling the lifetime. For example, in the fabrica-tion of a gold doped inverter type thyristor, control of the lifetime and thereby the base transport factor ~ may be achieved by merely assuring that the gate region 40 is not doped with gold.
Examples are hereafter presented to illustrate the :
;6 selection of appropriate gate region transport factor values for particular substrate doping profiles. Consider first a device substrate such as illustrated in Figure 1 having a constant carrier density of electron N = 3 x 10 3 electrons/cm3, a thickness of about 20 mils, a largeT pO (e.g., in excess of 30 usec), and P regions 24 and 26 formed by a 7 mil diffusion depth with a surface density Ns = 3 x 1016 carriers/ -~
cm3. Table I gives values for the multiplication factor of suitable accuracy for a substrate having this doping profile.
TABLE I
V M
3970 1.5 3870 1.25 3725 1.125 The lifetime~ M of layer 22 external of region 40 is reduced by the method of the invention to 15 ~sec., which is approximately one-half the lifetime in the gate region 40. This yields a minority carrier diffusion length of L =
approximately 5.3. mils. Where the imposed voltage across the thyristor 10 is V = 4050 volts, then the voltage across the main portion of N-P junction 32, VnbaSe~ is observed to be about 3350 volts. This corresponds to an undepleted base width of W(V)=5.3 mils. From equation (1), therefore,~ M
(4050) ~ 0.65 across the main portion of junction 32. The avalanche multiplication factor at the main portion of junc-tion 32, from Table I, is .~ (4050)~ 1.75. Therefore, the ~ ~ -12-..
8~i6 turn-on criterion ~M r~ = 1.13, indicating that the break-over voltage in the main portion of the thyristor 10 would be approximately 4000 volts.
After treatment according to the inventive m~thods, the minority carrier~ pO in the gate regions is adjusted to about 30 ~sec., or about twice as long as the time constant in the main portion of nbase layer 22. This yields a characteristic minority carrier length, L Yapproximately 7.5 mils. At 3900 volts, the junction voltage in gate region 40 of Figure 1 is about -12a-1~86866 ll ', 1 3200 volts. Therefore, by well-knswn relationships, W~V) - 5.6 2 mils. From equation (1), it follows that ~G (3900) ~ 1.37, from 3 Table I. It follows that the turn-on criterion is ~-M = 1.06,-4 indicating a breakover voltage in the gate emitter region 40 to be about 3850 volts, i.e., about 150 volts below the breakover 6 voltage in any other portion of the thyristor 10. Thus, device 7 breakover turn-on and current conduction ~hould occur in the gate 8 region 40 rather than in some other undesirable location.
9 It should, of course, be noted that these calculations .
assume that the edge region of the thyristor has a characteristic 11 breakdown voltage which is larger than 3850 volts. Relatively ~2 good edge passivation is maintained to this end, as is routinely 13¦ done in the industry.
14¦ ^ The concern about the breaXdown voltage at the edge of 15¦ the substrate 18 places an effective lower bound on the emitter 16¦ gate transport factor aG. For the breakover voltage to be higher --17-¦ in the main portion of the junction 32, a basic criterion is that 18¦ ~M be less than aG, which requires that the localized minority 19¦ diffusion length L in this region be reduced. Should ~M and L~l 201 be too low, however, a large increase in the forward voltage drop 21 may result.
22 On the other extreme, if ~G is increased substantially, 23 there is a resultant substantial increase in sensitivity to 24 leakage current and to the so-called dV/dt current in the gate region 40 which is increased by an amount proportional to the 26 gate region subtransistor gain and the area of gate region 40.
27 In order to minimize the change in the dV/dt rating of the 28 thyristor 10, gate region 40 may be reduced in area. .
29 The previous calculation was valid for a substrate characterized by an electron density constant of 3 x 1ol3~cm3.
31 For a device fabricated from a substrate 18 characterized by an 32 electron density of 5 x 1ol3 electron/cm , and 2 layer thickness 1l of 15 mils, utilizing equation (1) above and Table II below, 2 the breakover voltage on the junction 32 of the thyristor 10 3 external to region 4~ i9 calculated to ~e approximately 2800 4 volts with a charge-carrier lifetime T O - 5 ~sec- The break-over voltage in the gate region 40 is computed to be about 2500 6 volts with a carrier lifetime T Z 20 ~sec., or about four times 7 the lifetime in the main emitter region 28. Thus, the difference 8 ¦ in breakover voltage between the gate region 40 and the main 9 ¦ portion of the junction region 32 is approximately 300 volts.
T-AaLE II
11 V _ M
15 1 2880 1.5 16 I ~ 2775 1.25 171 2680 1.125 18¦ These calculations merely illustrate the magnitude of 19 ¦ difference in breakover voltage which may be obtained by local-20 ¦ ized control of the minority carrier lifetime T, upon which the 21 ¦ base transport factor , and thereby the turn-on criterion 22¦ a~M, is regulated.
23 ¦ Other specific embodiments of the inventive method will 24 ¦ be apparent in light of this disclosure. It is therefore not 25 ¦ intended that this invention be limited, except as indicated ~y za the ap ended clalms.
ll 14.
8 The anode base layer 22 is sandwiched between the anode 9 layer 24 and the cathode base layer 26. The anode layer 24 is in I0 ohmic contact through metallization of the anode contact 12. The II emitter layers 28 and 30 may be a high dopant concentration N-type 12 semiconductor fused or diffused over portions of the cathode base 13 layer 26. The cathode base layer 26 is in ohmic contact with 14 metallization of the cathode 14 through shorts in the main emitter -:~
I5 layer 28 and with metallization of the gate contact 16. The ~:
I6 anode base layer ~hares a relatively large semiconductor junction I~ 32 with the cathode base layer 26 and a further relati~ely large I8 semiconductor junction 34 with the anode layer 24. The cathode :
I9 base layer shares semiconductor junctions 36 and.38 with emitter layers 28 and 30.
21 Thyristor 10 is further characterized by a number of 22 operating regions. The region between the area of the gate 23 contact 16 and the anode contact 12 which roughly corresponds to 24 the area under the gate contact 16 is designated the gate region .
2~ 40. The region roughly corresponding to the area under the gate 26 emitter layer 30 is designated the gate or pilot thyristor region 27 42. The relatively broad area between the cathode contact 14 and 28 the anode contact 12 is generally known as the main thyristor 29 region 43. .
Thyristor 10 shown in FIG. 1 is known as an amplifying 3I gate thyristor because of the presence of the pilot thyristor 32 region 41. A sub~ransistor iQ defined by gate region 40 as 6``' . ", .
iO~8~;6 11 indicated by the phantom line through layers 26, 22 and 24. In 2 ! proper operation, the gate or pilot thyristor 41 is initially 31 turned on by the lateral flow of current betwee~ the yate contact 41 16 and the cathode contact 14. Once the pilot th~ristor 41 is 51 on,the main thyristor 43 is turned on by ga~e-to-cathode current 6, plus current flowing between the anode contact 12 belo-~ the gat 71 emitter region 30 and the cathode contact 14. According to the 8¦ method of thP present invention, control of the local gain 9 ¦characteristics interior to the gate emitter region 30, i.e. in 10¦ the gate region 40, inhibits device failure due to voltage brea~-11 ¦over caused by excessive forward voltage between the anode 12 and 12 the cathode 14. Regional gain control resu~s in an operational 13 geometry which causes the current through the subtransistor in 14l gate region 40 first to turn on the pilot thyristor region41 and 15¦ thereafter the main thyristor region 43 if excessive forward 161 voltage occurs. In structures omitting the pilot thyristor region ~71 the geometry is such that the main thyristor region 43 is turned i8¦ on by the current resulting from the excessive forward current.
19 The operation of the thyristor 10 is defined by well-known localized semiconductor characteristics. For example, the 21 turn-on point along the N-P junction 32 is determined by the pro-22 duct of the localized base transport factor , which approximates -23l the current gain characteristic~ and of the avalanche multipli-24 cation factor M. At the point ~.M first equals or exceeds uni~
along the N-P junction 32, avalanche current beings to flow.
26 The multiplication factor M and the transport factor are 27 both voltage dependent. The transport factor is approximated by 28 the equation:
30 ~ (V) = 2 tl) -31 exp (W(V) ) + exp ~ ) .
_ 10~6866 1 ¦ where:
2 WtV) is the undepleted base width at applied voltage;
3 and Lp is the base minority carrier diffusion length 4 in ~he NbaSe layer 22- .
6 Lp is defined by the expression:
7 Lp = ~D ~ )l/2 ~2 8 where: .
9 Dp is the characteristic minority charge-carrier difusio :-coefficient in the NbaSe material; and :
Tp iS the lifetime of excess minority charge carriers 12 in the NbaSe layer 22- . -~
13 The abrupt junction approximation for the multipli-14 cation factor M is given by the expression:
. .::
M~V) = l (3) -. :
16~
19 where:
V s the applied voltage; and 21 VBR is the characteristic breakdown voltage. :~
22 The abrupt junction approximation is insufficiently 23 accurate in the case of most diffusion formed junctions. More 24 exact expressions are found in the literature and may, for example 25 be found in S.M. Sze, Phvsics of Semiconductor Devices, Wiley .
26 Interscience Press, 1969.
27 The avalanche multiplication factor M and the transport 28 factor ~ may vary locally along the N-P junction 32. For the 29 purposes of explanation, the multiplication factor along the N-P junction 32 external to region 40 is designated MM, the 31 transport factor in the N base layer 22 external to region 40 is 32 designated aM, the ~ultiplication factor in the gate region 40 is 8. .
.
.
~ 10~866 1 ¦ designated MG, and the transport factor in the gate region 40 2 ¦ is designated G~
3 ¦ Since the turn-on criterion is a-M=l, the location of 4 the turn-on point can be controlled by relative modification of ¦ the transport factors aG and aM. Specifically, aG is established 6 according to the invention to be greater than aM, so t~at initial 7 device turn-on is constrained to occ~r in the gate region 40 and 8 along the inner portion of P-N junction 38.
9 An examination of equation (1) above indicates that aG
is physically dependent upon the charge-carrier diffusion length 11 Lp in the regions of interest. Equation (2) indicates that the 12 charge-carrier diffusion length ~p is directly dependent on ~3 charge-carrier lifetime ~p. Therefore, localized modification o 14 the charge-carrler li~etime ~p governs the location of device 15 turn-on. ' 16 FIGS. 2 and 3 illustraté possible methods for achieving 17 the desired control of localized carrier lifetime ~, and there-18 fore of the transport factor a, during fabrication of the '' lg thyristor device 10 illustrated in FIG. 1.
According to the inventive method of FIG. 2, a high 21 purity silicon wafer substrate 42 is first irradiated, for 22 example, with uniform electron irradiation 44 according to well-23 known methods in the art, as shown in (A) of FIG. 2. (See, for 24 example, Tarneia & Johnson, "Tailoring the recovered charge in power diodes using 2MeV electron irradiation," Electrochem.
26 Society Mtg., Paper 261 RNP 1975). This introduces lifetime 27 killing defect centers permeating the wafer 42. Thereafter, 28 the wafer 42 is subjected to localized heat annealling 46 in 2 the gate region 40, as shown in (B) of FIG. 2. The heat anneal-3 ling step 46 anneals out the lifetime killing defect centers in 3i the crystal structure of the wafer 18, thereby increasing 'the 32 lifetime T hence the transport factor a in the gate region 40.
. 9.
1 i ~he temperatures at which heat anneals out defects induced by 2 required irradiation levels for silicon are well known i~ the 3 art and in the literature. The results of the above-described 4 processing steps are localized variations in the charge-carrier lifetime of the silicon substr~te 42, a~ depicted in ~C) of 6 FIG. 2, which results in the relatively higher transport factor, 7 ~G' in the gate region 40.
8 FIG. 3 illl1strates an even simpler and somewhat more 9 versatile method for creating localized variation in the charge carrier lifetime in the silicon substrate 42. As depicted in (A) 11 of FIG. 3, a shield 48 is placed over the gate region 40, ~ ~ -12 whereupon the substrate is irradiated with electrcns or other ~3 defect inducing radiation. As a consequence, the gate region 40 14 under the shield 48 is protected against the creation of lifetime killing defects. The result is a silicon substrate 42 having 16 locally varying charge carrier lifetimes, as depicted in (~) of 17- FIG. 3. , 18 The shield 48 is preferably a removable mask such as 19 lead foil. The shield 48 may be mechanically held in place, a~
necessary.Should modification of the gate region lifetime be 21 desired, the shield 48 may be removed from the gate region 40 22 during a portion of the irradiation process. The method 23 illustrated in FIG. 3 is particularly versatile since the shield 24 48 can be provided for any length of time at any stage in the device fabrication process, but the method is performed most 26 conveniently after junction formation and metallization.
27 FIG. 4 illustrates a further method for creating a 28 desired localized variation in the charge carrier lifetime in 29 the silicon substrate 42. As depicted in (A), a patterned source of lifetime reducing impurities 51 is first deposited on the 31 surfacè of the substrate 42 except in the area of the gate region 32 40. The impurity material may comprise, for example, gold or ' 10, ~ .
;
108fà8~
platinum, and the layer may be emplaced by metal evaporiza-tion or by deposit of a CVD (chemical vapor deposition) glass or spun-on glass containing the impurity. General procedures for gold doping to control lifetime characteris-tics have been discussed in reference to particular applica-tions in the literature. See, for example, Fairfield &
Gokhale, "Control of diffused diode recovery time through ~old doping," Solid State Electronics, Vol. 9, pp. 905-907, 1~66. Such techniques may be adapted to the present method.
After deposition of the impurity layer, diffusion 50 is induced to urge the impurities to migrate into the substrate A2, which creates the desired lifetime-killing defects, as depicted in (B). The result is a substrate 42, depicted in (C), having a gate region of selective high lifetime.
Figure 5 illustrates a still further method for achieving the desired profile of charge carrier lifetime.
As depicted in (A) a layer of lifetime reducing impurity 52, such as gold or platinum, is deposited by ion implantation 53 on the surface of substrate 42 in the regions other than the gate regions 40. Thereafter, the impurity is diffused into the substrate 42, as depicted in (B). Consequently, a locally higher lifetime and hence a higher gate region transport factor is created, as depicted in (C).
Gold doping is a relatively straightforward means for controlling the lifetime. For example, in the fabrica-tion of a gold doped inverter type thyristor, control of the lifetime and thereby the base transport factor ~ may be achieved by merely assuring that the gate region 40 is not doped with gold.
Examples are hereafter presented to illustrate the :
;6 selection of appropriate gate region transport factor values for particular substrate doping profiles. Consider first a device substrate such as illustrated in Figure 1 having a constant carrier density of electron N = 3 x 10 3 electrons/cm3, a thickness of about 20 mils, a largeT pO (e.g., in excess of 30 usec), and P regions 24 and 26 formed by a 7 mil diffusion depth with a surface density Ns = 3 x 1016 carriers/ -~
cm3. Table I gives values for the multiplication factor of suitable accuracy for a substrate having this doping profile.
TABLE I
V M
3970 1.5 3870 1.25 3725 1.125 The lifetime~ M of layer 22 external of region 40 is reduced by the method of the invention to 15 ~sec., which is approximately one-half the lifetime in the gate region 40. This yields a minority carrier diffusion length of L =
approximately 5.3. mils. Where the imposed voltage across the thyristor 10 is V = 4050 volts, then the voltage across the main portion of N-P junction 32, VnbaSe~ is observed to be about 3350 volts. This corresponds to an undepleted base width of W(V)=5.3 mils. From equation (1), therefore,~ M
(4050) ~ 0.65 across the main portion of junction 32. The avalanche multiplication factor at the main portion of junc-tion 32, from Table I, is .~ (4050)~ 1.75. Therefore, the ~ ~ -12-..
8~i6 turn-on criterion ~M r~ = 1.13, indicating that the break-over voltage in the main portion of the thyristor 10 would be approximately 4000 volts.
After treatment according to the inventive m~thods, the minority carrier~ pO in the gate regions is adjusted to about 30 ~sec., or about twice as long as the time constant in the main portion of nbase layer 22. This yields a characteristic minority carrier length, L Yapproximately 7.5 mils. At 3900 volts, the junction voltage in gate region 40 of Figure 1 is about -12a-1~86866 ll ', 1 3200 volts. Therefore, by well-knswn relationships, W~V) - 5.6 2 mils. From equation (1), it follows that ~G (3900) ~ 1.37, from 3 Table I. It follows that the turn-on criterion is ~-M = 1.06,-4 indicating a breakover voltage in the gate emitter region 40 to be about 3850 volts, i.e., about 150 volts below the breakover 6 voltage in any other portion of the thyristor 10. Thus, device 7 breakover turn-on and current conduction ~hould occur in the gate 8 region 40 rather than in some other undesirable location.
9 It should, of course, be noted that these calculations .
assume that the edge region of the thyristor has a characteristic 11 breakdown voltage which is larger than 3850 volts. Relatively ~2 good edge passivation is maintained to this end, as is routinely 13¦ done in the industry.
14¦ ^ The concern about the breaXdown voltage at the edge of 15¦ the substrate 18 places an effective lower bound on the emitter 16¦ gate transport factor aG. For the breakover voltage to be higher --17-¦ in the main portion of the junction 32, a basic criterion is that 18¦ ~M be less than aG, which requires that the localized minority 19¦ diffusion length L in this region be reduced. Should ~M and L~l 201 be too low, however, a large increase in the forward voltage drop 21 may result.
22 On the other extreme, if ~G is increased substantially, 23 there is a resultant substantial increase in sensitivity to 24 leakage current and to the so-called dV/dt current in the gate region 40 which is increased by an amount proportional to the 26 gate region subtransistor gain and the area of gate region 40.
27 In order to minimize the change in the dV/dt rating of the 28 thyristor 10, gate region 40 may be reduced in area. .
29 The previous calculation was valid for a substrate characterized by an electron density constant of 3 x 1ol3~cm3.
31 For a device fabricated from a substrate 18 characterized by an 32 electron density of 5 x 1ol3 electron/cm , and 2 layer thickness 1l of 15 mils, utilizing equation (1) above and Table II below, 2 the breakover voltage on the junction 32 of the thyristor 10 3 external to region 4~ i9 calculated to ~e approximately 2800 4 volts with a charge-carrier lifetime T O - 5 ~sec- The break-over voltage in the gate region 40 is computed to be about 2500 6 volts with a carrier lifetime T Z 20 ~sec., or about four times 7 the lifetime in the main emitter region 28. Thus, the difference 8 ¦ in breakover voltage between the gate region 40 and the main 9 ¦ portion of the junction region 32 is approximately 300 volts.
T-AaLE II
11 V _ M
15 1 2880 1.5 16 I ~ 2775 1.25 171 2680 1.125 18¦ These calculations merely illustrate the magnitude of 19 ¦ difference in breakover voltage which may be obtained by local-20 ¦ ized control of the minority carrier lifetime T, upon which the 21 ¦ base transport factor , and thereby the turn-on criterion 22¦ a~M, is regulated.
23 ¦ Other specific embodiments of the inventive method will 24 ¦ be apparent in light of this disclosure. It is therefore not 25 ¦ intended that this invention be limited, except as indicated ~y za the ap ended clalms.
ll 14.
Claims (7)
1. A thyristor semiconductor device protected against voltage breakover failure, said device being for use in connection with means for applying voltage and for generating electrical currents and comprising a silicon substrate having on an obverse face an anode contact and on a reverse face a cathode contact and a gate contact, said gate contact being spaced laterally from said cathode contact, said substrate including a main thyristor region between the anode contact and the cathode contact, a gate subtransistor region between the anode contact and the gate contact and a gate emitter region substrate between the gate contact and the cathode contact establishing a pilot thyris-tor region, said pilot thyristor region being operatively coupled to said main thyristor region to turn on said main thyristor region when said pilot thyristor region is turned on, said gate subtransistor region being characterized by a locally longer minority carrier lifetime than the minority carrier lifetime in any area of the main thyristor region, such that excessive forward voltage causes currents ini-tially to flow only in the gate subtransistor region and act to turn on said pilot thyristor region.
2. A thyristor device according to claim 1 wherein the minority carrier lifetime in the gate region is at least about two times longer than elsewhere in said substrate.
3. A thyristor semiconductor device according to claim 1 wherein the gate subtransistor region includes a base region, said subtransistor base region having the maximum minority charge carrier lifetime in said substrate.
4. A semiconductor device protected against breakover turn-on failure and operative in connection with means for applying voltage and for generating electrical currents comprising a silicon base substrate having:
a main thyristor region with at least a main emitter area;
a gate region operatively associated with said main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in said gate region, said gate region including a localized subtransistor, said subtransistor being charac-terized by a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of said main thyristor region such that the location of initial current conduction under conditions of excessive forward voltage is limited to said gate region.
a main thyristor region with at least a main emitter area;
a gate region operatively associated with said main thyristor region for turning on currents in said main thyristor region in response to a condition turning on currents in said gate region, said gate region including a localized subtransistor, said subtransistor being charac-terized by a locally longer minority charge carrier lifetime than the minority charge carrier lifetime in all areas of said main thyristor region such that the location of initial current conduction under conditions of excessive forward voltage is limited to said gate region.
5. A semiconductor device according to claim 4 wherein said gate region is disposed within said main thyristor region.
6. A semiconductor device according to claim 4 wherein the minority charge carrier lifetime of said sub-transistor is at least twice the minority charge carrier lifetime than the minority charge carrier lifetime in all areas of said main thyristor region.
7. A semiconductor device according to claim 6 further including a pilot thyristor region operatively, coupled with said main thyristor region for turning on currents in said main thyristor region upon the turning on of currents in said subtransistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US77271277A | 1977-02-28 | 1977-02-28 | |
| US772,712 | 1977-02-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1086866A true CA1086866A (en) | 1980-09-30 |
Family
ID=25095976
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA280,370A Expired CA1086866A (en) | 1977-02-28 | 1977-06-13 | Self protection against breakover turn-on failure in thyristors |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS53106584A (en) |
| CA (1) | CA1086866A (en) |
| DE (1) | DE2738152A1 (en) |
| GB (1) | GB1588534A (en) |
| SE (1) | SE7707114L (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0108961B1 (en) * | 1982-11-15 | 1987-01-14 | Kabushiki Kaisha Toshiba | Thyristor device protected from an overvoltage |
| GB8717695D0 (en) * | 1987-07-25 | 1987-09-03 | Marconi Electronic Devices | Thyristors |
| DE3927899A1 (en) * | 1989-08-24 | 1991-02-28 | Eupec Gmbh & Co Kg | Thyristor module with main and auxiliary thyristors - has higher charge carrier life in auxiliary thyristor region |
| EP0419898B1 (en) * | 1989-09-28 | 2000-05-31 | Siemens Aktiengesellschaft | Method of enhancing the withstand voltage of a multilayered semiconductor device |
| DE10330571B8 (en) * | 2003-07-07 | 2007-03-08 | Infineon Technologies Ag | Vertical power semiconductor devices with injection damping agent in the edge area and manufacturing method therefor |
| CN110265510B (en) * | 2019-07-10 | 2024-04-05 | 兰州大学 | Deep junction avalanche multiplication light-operated thyristor and trigger control system thereof |
-
1977
- 1977-06-13 CA CA280,370A patent/CA1086866A/en not_active Expired
- 1977-06-20 SE SE7707114A patent/SE7707114L/en unknown
- 1977-06-27 GB GB26777/77A patent/GB1588534A/en not_active Expired
- 1977-08-24 DE DE19772738152 patent/DE2738152A1/en not_active Withdrawn
- 1977-09-13 JP JP11041477A patent/JPS53106584A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| SE7707114L (en) | 1978-08-29 |
| JPS53106584A (en) | 1978-09-16 |
| GB1588534A (en) | 1981-04-23 |
| DE2738152A1 (en) | 1978-08-31 |
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