GB1588534A - Protection against voltage breakover turn-on failure in thyristors - Google Patents

Protection against voltage breakover turn-on failure in thyristors Download PDF

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GB1588534A
GB1588534A GB26777/77A GB2677777A GB1588534A GB 1588534 A GB1588534 A GB 1588534A GB 26777/77 A GB26777/77 A GB 26777/77A GB 2677777 A GB2677777 A GB 2677777A GB 1588534 A GB1588534 A GB 1588534A
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7424—Thyristor-type devices, e.g. having four-zone regenerative action having a built-in localised breakdown/breakover region, e.g. self-protected against destructive spontaneous, e.g. voltage breakover, firing

Description

(54) PROTECTION AGAINST VOLTAGE BREAKOVER TURN-ON FAILURE IN THYRISTORS (71) We, ELECTRIC POWER RE SEARCH INSTITUTE, INC, a Corporation organised under the laws of the District of Columbia, United States of America of 3412 Hillview Avenue, Palo Alto, State of California, United States of America, do hereby declare the invention, for which we pray that a Patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to the protection of thyristor semiconductor devices against voltage breakover turn-on failure.
A thyristor is a solid state device having alternate layers of P type and N type semiconductor materials. A thyristor is typically a disc of four alternating layers of N and P type silicon, the layers and junctions between them being formed by precision gaseous diffusion, substrate fusion and/or alloying techniques. A thyristor has generally three electrodes, referred to as the cathode, the anode, and the gate, the gate being the control electrode for the device. During normal operation, the thyristor is turned on by at least momentary application of a forward bias gate-to-cathode voltage. The device remains on until the anode-to-cathode voltage is reduced to a value below that required to sustain regeneration, or forward current.
The thyristor may also be turned on without a voltage applied to the gate if the anode-tocathode voltage exceeds a value inherent in the device design. This phenomenon is known as voltage breakover turn-on. The main emitter area in the cathode of a thyristor is prone to failure during breakover turn-on initiated by such excess device voltage. The location of the tum-on point within the device is not usually subject to control. As a result, the turn-on point may often occur within the cathode emitter in a manner causing permanent device failure.
The device turn-on criterion, which is-based on the current gain of the transistor formed by the anode layer, the anode base layer and the cathode base layer of the thyristor device, is approximated to the first order as the product of the anode base transport factor aT and the avalanche multiplication factor M.
(Strictly speaking, the turn-on criterion is the product of the current gain factor, a:0, and the multiplication factor, M. However, because current gain, a0, is the product of the anode base transport factor, aT, and the emitter efficiency, yE, of the anode emitter, which is close to unity and does not vary strongly with voltage, to the first order 0o - T.
Therefore, the subscript may be ignored and the terms current gain and base transport factor may be used interchangeably.) Both the base transport factor and the avalanche multiplication factor are voltage sensitive parameters. An excess forward voltage will cause the product a M to prematurely exceed unity within selected regions of the thyristor, resulting in a local current gain approaching infinity. Device turn-on in this manner often causes device failure.
In the past, there have been two basic methods for protecting against voltage breakover turn-on failure. In the first method, external circuitry is connected between the anode and the gate which has a breakover voltage below that of the internal emitter to be protected. As voltage between the anode and cathode approaches the breakover level, the resulting avalanche current in the extenial circuitry becomes the gate current of the thyristor, thereby firing the thyristor normally.
One of the major shortcomings of this type of breakover protection is the need for additional external circuit components, with the resultant increased expense and system size.
A second method involves the use of internal auxiliary fabrication techniques, wherein the silicon wafer from which the N type base region is fabricated is prepared so that the highest donor concentration is located precisely below the area for the gate contact. This method is described in an article by Peter Voss, Solid State Electronics, Volume 27, page 265 (1974). In the Voss method, the dependence of the avalanche breakdown characteristic on donor concentration assures that the doped region is the first region in which breakdown can occur, thereby protecting against voltage breakover turn-on failure in any other region of the thyristor.
Thyristors and many other semiconductor devices are fabricated from a wafer of silicon, initially of high purity, which is characterized by a long charge carrier lifetime. In the course of fabrication it is common practice to uniformly irradiate the wafer or to introduce a lifetime reducing impurity uniformly into the wafer surface to modify the characteristic of the silicon wafer. This technique can be adapted to advantage as hereinafter described.
In accordance with one aspect of the present invention there is provided a thyristor semiconductor device protected against voltage breakdown turn-on failure having a main~thy- ristor region spaced apart from a gate subtransistor region associated with said main thyristor region for turning on said main thyristor region in response to a condition turning on said gate subtransistor region, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said suibtransistor region has greater current gain chaacteristics and a lower breakdown voltage than said main thyristor region.
According to a second aspect of the present invention there is provided a thyristor semiconductor device protected against voltage breakover turn-on failure comprising a silicon substrate having on an obverse face an anode contact and on a reverse face laterally spaced- apart cathode and gate contacts, said substrate including a main thyristor region between the anode and cathode contacts and a gate sulbtransistor region between the anode and gate contacts for turning on said main thyristor region in response to a condition turning on said gate sub transistor region, said gate sub- transistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region.
According to a third aspect of the present invention there is provided a thyristor semiconductor device protected against voltage breakover turn-on failure comprising a silicon substrate having on an obverse face an anode contact and on a reverse face laterally spacedapart cathode and gate contacts, said substrate including a main thyristor region between the anode and cathode contacts, a gate subtransistor region between the anode and gate contacts and a gate emitter region between the gate and cathode contacts establishing a pilot thyristor region which is operatively coupled to said main thyristor region to turn on said main thyristor region when said pilot thyristor region is turned on, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region, whereby excessive forward voltage causes current initially to flow only in the gate subtransistor region and act to turn on said pilot thyristor region.
The invention will now be described further, by way of example only, by reference to the accompanying drawings which illustrate several embodiments thereof and in which: FIG. 1 is a schematic cross-section illustrating a section of one form of an amplifying gate type thyristor device in accordance with the invention; FIG. 2 shows a cross-section of silicon wafers illustrating different stages in one method for fabrication of the device of Figure 1; FIG. 3 illustrates a second method for~fab- rication of the device of Figure 1; FIG. 4 illustrates a third method for fabo rication of the device of Fig. 1; and FIG. 5 illustrates a fourth method for fabrication of the device of Fig. 1.
The thyristor 10 of Flg. 1 comprises an anode contact 12, a cathode contact 14, and a gate contact 16 in ohmic contact with first and second sides of a generally disc shaped silicon wafer substrate 18. The gate contact 15 is typically located near the centre of the substrate 18, and in some designs it may be surrounded by an annular cathode contact 14.
The thyristor 10 comprises distinct joined semiconductor layers. The semiconductor layers are designated the anode base or wide base or simply the Nbase layer 22, the anode P or Panode layer 24, the cathode base or Phase layer 26 and discontinuous layers 28 and 30. The layer 28 is known as the main emitter layer 28 and the layer 30 which is between the cathode contact 14 and the gate contact 16 is known as the gate emitter or pilot thyristor emitter layer 30.
The anode base layer 22 is sandwiched between the anode layer 24 and the cathode base layer 26. The anode layer 24 is in ohmic contact through metallization of the anode contact 12. The emitter layers 28 and 30 may be a high dopant concentration N-type semiconductor fused or diffused over portions of the cathode base layer 26. The cathode base layer 26 is in ohmic contact with metallization of the cathode 14 through shorts in the main emitter layer 28 and with metallization of the gate contact 16. The anode base layer shares a relatively large semiconductor junction 32 with the cathode base layer 26 and a further relatively large semiconductor junction 34 with the anode layer 24. The cathode base layer shares semiconductor junctions 36 and 38 with emitter layers 28 and 30.
Thyristor 10 is further characterized by a number of operating regions. The region between the area of the gate contact 16 and the anode contact 12 which roughly corresponds to the area under the gate contact 16 is designated the gate region 40. The region roughly corresponding to the area under the gate emitter layer 30 is designated the gate or pilot thyristor region 41. The relatively broad region between the cathode contact 14 and the anode contact 12 is generally known as the main thyristor region 43.
Thyristor 10 shown in FIG. 1 is known as an amplifying gate thyristor because of the presence of the pilot thyristor region 41. A subtransistor is defined by gate region 40 as indicated by the phantom line through layers 26, 22 and 24. In proper operation, the gate or pilot thyristor 41 is initially turned on by the lateral flow of current between the gate contact 16 and the cathode contact 14. Once the pilot thyristor 41 is on, the main thyristor 43 is turned on by gate-to-cathode current plus current flowing between the anode contact 12 below the gate emitter region 30 and the cathode contact 14. Control of the local gain characteristics interior to the gate emitter region 30; i.e. in the gate region 40, inhibits device failure due to voltage breakover caused by excessive forward voltage between the anode 12 and the cathode 14. Regional gain control results in an operational geometry which causes the current through the subtransistor in gate region 40 first to turn on the pilot thyristor region 41 and thereafter the main thyristor region 43 if excessive forward voltage occurs. In structures omiting the pilot thyristor region the geometry is such that the main thyristor region 43 is turned on by the current resulting from the excessive forward current.
The operation of the thyristor 10 is defined by well-known localized semiconductor characteristics. For example, the turn-on point along the N-P junction 32 is determined by the product of the localized base transport factor g, which approximates the current gain characteristics, and of the avalanche multiplication factor M. At the point ,zz- M first equals or exceeds unity along the NP junction 32, avalanche current beings to flow.
The multiplication factor M and the transport factor are both voltage dependent. The transport factor is approximately by the equation:
where: W(V) is the undepleted base width at applied voltage; and L,is the base minority carrier diffusion length in the Nbase layer 22.
Lp is defined by the expression: Lp = (Dprp)l/2 (2) where: Dp is the characteristic minority chargecarrier diffusion coefficient in the Nbase material; and rp is the lifetime of excess minority charge cariers in the Abase layer 22.
The abrupt junction approximation for the multiplication factor M is given by the expression:
where: V is the applied voltage; and VBR is the characteristic breakdown voltage.
The abrupt junction approximation is insufficiently accurate in the case of most diffusion formed junctions. More exact expressions are found in the literature and may, for example be found in S.M. Sze, Physics of Semiconductar Devices, Wiley Interscience Press, 1969.
The avalanche multiplication factor M and the transport factor , may vary locally along the N-P junction 32. For the purposes of explanation, the multiplication factor along the N-P junction 32 external to region 40 is designated MX, the transport factor in the N base layer 22 external to region 40 is designated ax, the multiplication factor in the gate region 40 is designated MG, and the transport factor in the gate region 40 is designated SEG- Since the turn-on criterion is a M = 1, the location of the turn-on point can be controlled by relative modification of the transport factors IG and . Specifically, l2G is established to be greater than a, so that initial device turn-on is constrained to occur in the gate region 40 and along the inner portion of P-N junction 38.
An examination of equation (1) above indicates that 105G is dependent upon the chargecarrier diffusion length Lp in the regions of interest. Equation (2) indicates that the chargecarrier diffusion length L5 is directly dependent on charge-carrier lifetime Tp. Therefore, localized modification of the charge-carrier lifetime rp governs the location of device turn-on.
FIGS. 2 and 3 illustrate possible methods for achieving the desired control of localized carrier lifetime r, and therefore of the trans port factor a, during fabrication of the thyristor device 10 illustrated in FIG. 1.
In accordance with the method of FIG. 2, a high purity silicon wafer substrate 42 is first irradiated, for example, with uniform electron irradiation 44 according to wellanown methods in the art, as shown in (A) of FIG.
2. (See, for example, Tarneja & Johnsom, "Tailoring the recovered charge in power diodes using 2MeV electron irradiation," Electrochem. Society Mtg., Paper 261 RNP 1975). This introduces lifetime killing defect centers permeating the wafer 42 Thereafter, the wafer 42 is subjected to localized heat annealling 46 in the gate region 40, as shown in (B) of FIG. 2. The heat annealling step 46 anneals out the lifetime killing defect centers in the crystal structure of the wafer 18, thereby increasing the lifetime r hence the transport factor oe in the gate region 40. The temperatures at which heat anneals out defects induced by required irrad ation levels for silicon are well known in the art and in the literature. The results of the above-described processing steps are localized variations in the charge-carrier lifetime of the silicon substrate 42, as depicted in (C) of FIG. 2, which results in the relatively higher transport factor, ,obG, in the gate region 40.
FIG. 3 illustrates an even simper and somewhat more versatile method for creating localized variation in the charge carrier lifetime in the silicon substrate 42. As depicted in (A) of FIG. 3, a shield 48 is placed over the gate region 40, whereupon the substrate is irradiated with electrons or other defect inducing radiation. As a consequence, the gate region 40 under the shield 48 is protected against the creation of lifetime killing defects.
The result is a silicon substrate 42 ha\ring locally varying charge carrier lifetimes, as depicted in (B) of FIG, 3.
The shield 48 is preferably a removable mask such as lead foil. The shield 48 may be mechanically held in place, as necessary.
Should modification of the gate region lifetime be desired, the shield 48 may be re- moved from the gate region 40 during a portion of the irradiation process. The method illustrated in FIG. 3 is particularly versatile since the shield 48 can be provided for any length of time at any stage in the device fabrication process, but the method is performed most conveniently after junction formation and metallization.
FIG. 4 illustrates a further method for creating a desired localized variation in the charge carrier lifetime in the silicon substrate 42. As depicted in (A), a patterned source of lifetime reducing impurities 51 is first deposited on thesurface 6 the substrate 42 except in the area of the gate region 40. The impurity material may comprise, for example, gold or platinum, and the layer may be emplaced by metal vaporization or by deposit of a CVD (chemical vapour deposition) glass or spun-on glass containing the impurity.
General procedures for gold doping to control lifetime characteristics have been discussed in reference to particular applications in the literature. See, for example, Fairfield B Gokhale, "Control of diffused diode recovery time through gold doping," Solid State Elec tronics, Vol. 9 pp. 905-907, 1966. Such techniques may be adapted to the present method. After deposition of the impurity layer, diffusion 50 is induced to urge the impurities to migrate into the substrate 42, which creates the desired lifetime-killing de fects, as depicted in (B). The result is a sub strate 42, depicted in (C), having a gate region of selective high lifetime.
FIG. 5 illustrates a still further method for achieving the desired profile of charge carrier lifetime. As depicted in (A) a layer of a lifetime reducing impurity 52, such as gold or platinum, is deposited by ion implantation 53 in the surface of substrate 42 in the regions other than the gate region 40. Thereafter, the impurity is diffused into the substrate 42, as depicted in (B). Consequently, a locally higher lifetime and hence a higher gate region trans port factor is created, as depicted in (C).
Gold doping is a relatively straightforward means for controlling the lifetime. For ex ample, in the fabrication of a gold doped in verter type thyristor, control of the lifetime and thereby the base transport factor , may be achieved by merely assuring that the gate region 40 is not doped with gold.
Examples are hereafter presented to i US- trate the selection of appropriate gate region transport factor values for particular substrate doping profiles. Consider first a device sub strate such as illustrated in FIG. 1 having a constant carrier density of electron N = 3 X 1013 electrons/cm3, a thickness of about 20 mails, a large 7,, (e.g., in excess of 30 Lsec), and P regions 24 and 26 formed by a 7 mil diffusion depth with a surface density Ns = 3 X 1016 carriersXcm3 Table I gives values for the multiplication factor of suitable accuracy for a substrate having this doping profile.
TABLE f.
V M 4520 4220 8 4190 4 4100 2 3970 1.5 3870 1.25 3725 1.125 The lifetime rDI of layer 22 external of region 40 is reduced to 15 ,u sec., which is approximately one-half the lifetime in the gate region 40. This yields a minority carrier diffusion length of L = approximately 5.3 mils. Where the imposed voltage across the thyristor 10 is V = 4050 volts, then the voltage across the main portion of N-P junction 32, Vnbase, is observed to be about 3350 volts. This corresponds to an undepleted base width d -W(V) = 5.3 mils. From equation (1), therefore, a G050) -- 0.65 across the main portion of junction 32. The avalanche multiplication factor at the main Iportion of junction 32, from Table I, is MM(4050)# 1.75.
Therefore, the turn-on criterion 10rX MM = 1.13, indicating that the breakover voltage in the main portion of the thyristor 10 would be approximately 4000 volts After treatment, the minority carrier rpO in the gate region is adjusted to about 30 lysec., or about twice as long as the time constant in the main portion of abase layer 22. This yields a characteristic minority carrier diffusion length, L ~ approximately 7.5 mils. At 3900 volts, the junction voltage in gate region 40 of FIG. 1 is about 3200 volts. Therefore, by well-known relationshipls, W(V) ~ 5.6 rails.
From equation (1), it follows that αG (3900) 1.37, from Table I. It follows that the turnon criterion is la M = 1.06, indicating a breakover voltage in the gate emitter region 40 to be about 3850 volts, i.e., about 150 volts below the breakover voltage in any other portion of the thyristor 10. Thus, device breakover turn-on and current conduction should occur in the gate region 40 rather than in some other undesirable location.
It should, of course, be noted that these calculations assume that the edge region of the thyristor has a characteristic breakdown voltage which is larger than 38501 volts.
Relatively good edge passivation is maintained to this end, as is routinely done in the industry.
The concern about the breakdown voltage at the edge of the substrate 18 places ~ an effective lower bound on the emitter gate transport factor Ices. For the breakover voltage to be higher in the main portion of the junction 32, a basic criterion is that sgx be less than mc, which requires that the localized minority diffusion length L in this region be reduced.
Should X and LM be too low, however, a large increase in the forward voltage drop may result.
On the other extreme, if louG is increased substantially, there is a resultant substantial increase in sensitivity to leakage current and to the so-called dV/dt current in the gate region 40 which is increased by an amount proportional to the gate region subtransistor gain and the area of gate region 40. In order to minimize the change in the dVjdt faYmg of the thyristor 10, gate region 40 may be reduced in area.
The previous calculation was valid for a substrate characterized by an electron density constant of 3 X 10 /cm3. For a device fabricated from a substrate 18 characterized by an electron density of 5 X 10l3 electron/ cm3, and a layer thickness of 15 rails, utilizing equation (1) above and Table II below, the breakover voltage on the junction 32 of the thyristor 10 external to region 40 is calculated to be approximately 2800 volts with a chargecarrier lifetime 7no = 5 Fsec. The breakover voltage in the gate region 40 is computed to be about 2500 volts with a carrier lifetime = = 20 lysec., or about four times the life- time in the main emitter region 28. Thus, the difference in breakover voltage between the gate region 40 and the main portion of the junction region 32 is approximately 300 volts.
TABLE II.
V M 30170 8 30401 44 2960 2 2880 1.5 2775 1.25 2680 1.125 These calculations merely illustrate the magnitude of difference in breakover voltage which may ibe obtained by localized control of the minority carrier lifetime r, upon which the base transport factor a, and thereby the turn-on criterion os- M, is regulated.
WHAT WE CLAIM IS: 1. A thyristor semiconductor device protected against voltage breakover turn-on failure having a main thyristor region spaced apart from a gate subtransistor region associated with said main thyristor region for turning on said main thyristor region in response to a condition turning on said gate subtransistor region, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region.
2. A thyristor semiconductor device protected against voltage breakover turn-on failure comprising a silicon substrate having on an obverse face an anode contact and on a reverse face laterally spaced-apart cathode and gate contacts, said substrate including a main thyristor region between the anode and cathode contacts and a gate sub transistor region between the anode and gate contacts for turning on said main thyristor region in response to a condition turning on said gate subtransistor region, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main
**WARNING** end of DESC field may overlap start of CLMS **.

Claims (7)

  1. **WARNING** start of CLMS field may overlap end of DESC **.
    diffusion length of L = approximately 5.3 mils. Where the imposed voltage across the thyristor 10 is V = 4050 volts, then the voltage across the main portion of N-P junction 32, Vnbase, is observed to be about 3350 volts. This corresponds to an undepleted base width d -W(V) = 5.3 mils. From equation (1), therefore, a G050) -- 0.65 across the main portion of junction 32. The avalanche multiplication factor at the main Iportion of junction 32, from Table I, is MM(4050)# 1.75.
    Therefore, the turn-on criterion 10rX MM = 1.13, indicating that the breakover voltage in the main portion of the thyristor 10 would be approximately 4000 volts After treatment, the minority carrier rpO in the gate region is adjusted to about 30 lysec., or about twice as long as the time constant in the main portion of abase layer 22. This yields a characteristic minority carrier diffusion length, L ~ approximately 7.5 mils. At 3900 volts, the junction voltage in gate region 40 of FIG. 1 is about 3200 volts. Therefore, by well-known relationshipls, W(V) ~ 5.6 rails.
    From equation (1), it follows that αG (3900) 1.37, from Table I. It follows that the turnon criterion is la M = 1.06, indicating a breakover voltage in the gate emitter region 40 to be about 3850 volts, i.e., about 150 volts below the breakover voltage in any other portion of the thyristor 10. Thus, device breakover turn-on and current conduction should occur in the gate region 40 rather than in some other undesirable location.
    It should, of course, be noted that these calculations assume that the edge region of the thyristor has a characteristic breakdown voltage which is larger than 38501 volts.
    Relatively good edge passivation is maintained to this end, as is routinely done in the industry.
    The concern about the breakdown voltage at the edge of the substrate 18 places ~ an effective lower bound on the emitter gate transport factor Ices. For the breakover voltage to be higher in the main portion of the junction 32, a basic criterion is that sgx be less than mc, which requires that the localized minority diffusion length L in this region be reduced.
    Should X and LM be too low, however, a large increase in the forward voltage drop may result.
    On the other extreme, if louG is increased substantially, there is a resultant substantial increase in sensitivity to leakage current and to the so-called dV/dt current in the gate region 40 which is increased by an amount proportional to the gate region subtransistor gain and the area of gate region 40. In order to minimize the change in the dVjdt faYmg of the thyristor 10, gate region 40 may be reduced in area.
    The previous calculation was valid for a substrate characterized by an electron density constant of 3 X 10 /cm3. For a device fabricated from a substrate 18 characterized by an electron density of 5 X 10l3 electron/ cm3, and a layer thickness of 15 rails, utilizing equation (1) above and Table II below, the breakover voltage on the junction 32 of the thyristor 10 external to region 40 is calculated to be approximately 2800 volts with a chargecarrier lifetime 7no = 5 Fsec. The breakover voltage in the gate region 40 is computed to be about 2500 volts with a carrier lifetime = = 20 lysec., or about four times the life- time in the main emitter region 28. Thus, the difference in breakover voltage between the gate region 40 and the main portion of the junction region 32 is approximately 300 volts.
    TABLE II.
    V M 30170 8 30401 44 2960 2
    2880 1.5
    2775 1.25
    2680 1.125 These calculations merely illustrate the magnitude of difference in breakover voltage which may ibe obtained by localized control of the minority carrier lifetime r, upon which the base transport factor a, and thereby the turn-on criterion os- M, is regulated.
    WHAT WE CLAIM IS: 1. A thyristor semiconductor device protected against voltage breakover turn-on failure having a main thyristor region spaced apart from a gate subtransistor region associated with said main thyristor region for turning on said main thyristor region in response to a condition turning on said gate subtransistor region, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region.
  2. 2. A thyristor semiconductor device protected against voltage breakover turn-on failure comprising a silicon substrate having on an obverse face an anode contact and on a reverse face laterally spaced-apart cathode and gate contacts, said substrate including a main thyristor region between the anode and cathode contacts and a gate sub transistor region between the anode and gate contacts for turning on said main thyristor region in response to a condition turning on said gate subtransistor region, said gate subtransistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main
    thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region.
  3. 3. A thyristor semiconductor device protected against voltage breakover turn-on failure comprising a silicon substrate having on an obverse face an anode contact and on a reverse face laterally spaced-apart cathode and gate contacts, said substrate including a main thyristor region between the anode and cathode contacts, a gate subtransistor region between the anode and gate contacts and a gate emitter region between the gate and cathode contacts establishing a pilot thyristor region which is operatively coupled to said main thyristor region to turn on said main thyristor region when said pilot thyristor region is turned on, said gate sub transistor region being characterized by a minority charge carrier lifetime which is longer than the minority charge carrier lifetime in the entire area of the main thyristor region so that said subtransistor region has greater current gain characteristics and a lower breakdown voltage than said main thyristor region, whereby excessive forward voltage causes current initially to flow only in the gate subtransistor region and act to turn on said pilot thyristor region.
  4. 4. A thyristor semiconductor device according to any one of claims 1 to 3, wherein said gate region is disposed within said main thyristor region.
  5. 5. A thyristor semiconductor device according to any one of claims 1 to 4, wherein the minority charge carrier lifetime of said gate subtransistor region is at least twice the rninority charge carrier lifetime elsewhere in said device.
  6. 6. A thyristor semiconductor device according to any one of daims 1 to 5, wherein the gate subtransistor region includes a base region, said base region having the maximum minority charge carrier lifetime in said substrate.
  7. 7. A thyristor semiconductor device substantially as hereinbefore described with reference to and as illustrated in the various figures of the accompanying drawings.
GB26777/77A 1977-02-28 1977-06-27 Protection against voltage breakover turn-on failure in thyristors Expired GB1588534A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207552A (en) * 1987-07-25 1989-02-01 Marconi Electronic Devices Thyristors
CN110265510A (en) * 2019-07-10 2019-09-20 兰州大学 A kind of knot avalanche multiplication photo thyristor and its Triggering Control System deeply

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3369234D1 (en) * 1982-11-15 1987-02-19 Toshiba Kk Thyristor device protected from an overvoltage
DE3927899A1 (en) * 1989-08-24 1991-02-28 Eupec Gmbh & Co Kg Thyristor module with main and auxiliary thyristors - has higher charge carrier life in auxiliary thyristor region
EP0419898B1 (en) * 1989-09-28 2000-05-31 Siemens Aktiengesellschaft Method of enhancing the withstand voltage of a multilayered semiconductor device
DE10330571B8 (en) 2003-07-07 2007-03-08 Infineon Technologies Ag Vertical power semiconductor devices with injection damping agent in the edge area and manufacturing method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2207552A (en) * 1987-07-25 1989-02-01 Marconi Electronic Devices Thyristors
GB2207552B (en) * 1987-07-25 1990-10-03 Marconi Electronic Devices Thyristors
CN110265510A (en) * 2019-07-10 2019-09-20 兰州大学 A kind of knot avalanche multiplication photo thyristor and its Triggering Control System deeply
CN110265510B (en) * 2019-07-10 2024-04-05 兰州大学 Deep junction avalanche multiplication light-operated thyristor and trigger control system thereof

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CA1086866A (en) 1980-09-30
DE2738152A1 (en) 1978-08-31
SE7707114L (en) 1978-08-29
JPS53106584A (en) 1978-09-16

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