CA1060993A - Nonvolatile semiconductor memory - Google Patents
Nonvolatile semiconductor memoryInfo
- Publication number
- CA1060993A CA1060993A CA208,942A CA208942A CA1060993A CA 1060993 A CA1060993 A CA 1060993A CA 208942 A CA208942 A CA 208942A CA 1060993 A CA1060993 A CA 1060993A
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- Prior art keywords
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- substrate
- gate
- drain
- drain regions
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 230000005669 field effect Effects 0.000 claims abstract description 3
- 238000009413 insulation Methods 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 238000013459 approach Methods 0.000 claims description 9
- 239000000969 carrier Substances 0.000 claims description 6
- 238000010893 electron trap Methods 0.000 claims description 5
- 230000009183 running Effects 0.000 claims 2
- 230000003334 potential effect Effects 0.000 claims 1
- 230000015654 memory Effects 0.000 description 46
- 238000002347 injection Methods 0.000 description 12
- 239000007924 injection Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 238000002474 experimental method Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VLQGDKKHHCKIOJ-UHFFFAOYSA-N NNOS Chemical compound NNOS VLQGDKKHHCKIOJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Abstract of the Disclosure A nonvolatile semiconductor memory having an insulated gate field effect transistor whose structure is so made as to permit, during the write operation, a substrate surface region below the gate to be substantially enclosed by depletion layers extended from the source and drain regions or by said depletion layers and a channel formed between said regions, thereby increasing a resistance between the substrate and said substrate surface region to decrease the writing current in amount and the writing voltage in level.
Description
~060993 This invention relates to a nonvolatile semicona~ctof mcmory having~n insulatedgate fieldeffect transistor constructian~
The present invention will be illustrated by way of drawings, in which:
Fig. 1 is a sectional view illustrating the construc-tion of a prior art MNOS memory;
Fig. 2 is a sectional view for explaining the flow of an avalanche current in ef~ecting the writing of information in a prior art memory shown in Fig. 3, taken along the line II-II
of Fig. 3;
Fig.3 isa plan view of said prior art memory ofFig. 2;
Fig. 4 is a sectional view of another memory devised by the present invention;
Fig. 5 is a plan view of nonvolatile semiconductor memory according to an embodiment of the invention; - ~
Fig. 6 is a sectional view taken along the line VI-VI ~ -of Fig. 5;
Fig. 7 graphically shows the relationship between the writing voltage value and the threshold voltage value after com-pletion of the write operation, with respect to the presentmemory and the prior art memory;
Fig. 8 is a plan view o a memory according to another embodiment of the invention;
Fig. 9 is a sectional view taken along the line IX-IX
of Fig. S as viewed in an arrow-indicated direction; and Fig. 10 is a sectional view illustrating the main part of a modification according to the embodiment of Fig. 8.
A so-called MNOS memory is known as a typical example of this type of semiconductor memory. This semiconductor memory is a metal-nitride-oxide-semiconductor (MNOS) memory so construc-ted as to have a p+ type source region 2 and drain region 3 in an n type silicon substrate 1, a gate insulation Sl -- 1 --film bri~g~d between said both regions, 2, 3 and prepared by laminating an oxide film (SiO2) 4 having an extremely small ~ ~S i3 ~
thickness and a silicon-nitride film ~ 5, and further source, gate and drain electrodes 6, 7 and 8, as shown in Fig. 1.
The writing of information in said MNOS memory is performed utilizing together the avalanche effect and tunnel effect, that is avalanche-tunnel injection, as follows. Namely, the n-type substrate 1 ~nd gate are grounded while a negative voltage having a prescribed level is applied to the drain 1 and source r
The present invention will be illustrated by way of drawings, in which:
Fig. 1 is a sectional view illustrating the construc-tion of a prior art MNOS memory;
Fig. 2 is a sectional view for explaining the flow of an avalanche current in ef~ecting the writing of information in a prior art memory shown in Fig. 3, taken along the line II-II
of Fig. 3;
Fig.3 isa plan view of said prior art memory ofFig. 2;
Fig. 4 is a sectional view of another memory devised by the present invention;
Fig. 5 is a plan view of nonvolatile semiconductor memory according to an embodiment of the invention; - ~
Fig. 6 is a sectional view taken along the line VI-VI ~ -of Fig. 5;
Fig. 7 graphically shows the relationship between the writing voltage value and the threshold voltage value after com-pletion of the write operation, with respect to the presentmemory and the prior art memory;
Fig. 8 is a plan view o a memory according to another embodiment of the invention;
Fig. 9 is a sectional view taken along the line IX-IX
of Fig. S as viewed in an arrow-indicated direction; and Fig. 10 is a sectional view illustrating the main part of a modification according to the embodiment of Fig. 8.
A so-called MNOS memory is known as a typical example of this type of semiconductor memory. This semiconductor memory is a metal-nitride-oxide-semiconductor (MNOS) memory so construc-ted as to have a p+ type source region 2 and drain region 3 in an n type silicon substrate 1, a gate insulation Sl -- 1 --film bri~g~d between said both regions, 2, 3 and prepared by laminating an oxide film (SiO2) 4 having an extremely small ~ ~S i3 ~
thickness and a silicon-nitride film ~ 5, and further source, gate and drain electrodes 6, 7 and 8, as shown in Fig. 1.
The writing of information in said MNOS memory is performed utilizing together the avalanche effect and tunnel effect, that is avalanche-tunnel injection, as follows. Namely, the n-type substrate 1 ~nd gate are grounded while a negative voltage having a prescribed level is applied to the drain 1 and source r
2 junctions. As the result, an avalanche breakdown occurs at the surface portions of the source and drain junctions, and hot electrons produced due to this avalanche breakdown are injected into electron traps within a portion of the silicon-nitride film 5 in the neighbourhood of the interface between the films 4 and 5, thereby increasing an electron concentration in the traps near the source and drain regions. Simultaneously, a current is flowed from the avalanche breakdown region to the interior of r the substrate 1 due to the production of avalanche plasma at the surface of the substrate 1, thereby producing a voltage drop, so that the potential of the surface region of the substrate right below the gate electrode approaches that of a voltage applied to the source and drain regions 2 and 3. As the result, electrons are also injected into traps in the vicinity of the center of the gate electrode, far from the source and drain regions 2 and
3 due to the tunnel effect produced in the silicon-oxide film 4.
In this manner, injection of electrons into traps within the silicon-nitride film 5 extending along the entire length of the r gate electrode region is effected to cause the .
' - la -~.~ ,...
; ~060993 .
threshold volta~e of the gate elec~rode to be shifted in a posi-tive direction. If this threshold voltage shifted in a positive direction is defined as, for example, "1", and the threshold voltage shifted in a negative direction is defined as, for example, "0", two values of information "1" and "0" will be stored in the semiconductor memory in a nonvolatile state due to the difference between said both threshold voltages.
The condition in~which the information value "1" is written in the semiconductor memory of Fig. 1 is restored to the "0" condition by applying a voltage having a potential of zero to the source and drain electrodes 6 and 8 and applying a nega-tive voltage to the gate electrode. That is, restoration to the "0" condition is executed by causing electrons injected into the electron traps of the silicon-nitride film 5 to be ejected into the substrate 1 through the oxide film 4 utilizing the tunnel effect. The MNOS memory based on the use of a writing method utilizing the tunnel effect produced as the surface potential of the substrate 1 approaches the potential of the source and drain regions 2 and 3 due to the afores~id avalanche effect (namely, the writing method utilizing the avalanche-tunnel injection) has the following drawbacks. First, where a usual substrate having a resistivity of several ohm.cm is used, it is necessary that a large current is flowed in the source and drain junctions and also that a high writing voltage is applied to these junctions.
This fact becomes a great obstruction when this type of memory is integrated into a large scale memory. Particularly, the fact that a large avalanche current is required means that when con-sideration is given to the number of memory elements or MOS tran-sistors series-connected to one memory element, the construction of a large scale integrated circuit (LSI) re~uires an extremely high power source voltage and simultaneously imposes a limitation on the writing-in speed.
- ~0~0993 Whcre it is dcsired to eliminatc the forcgoing draw-backs, a substrate having as high a resistivity as, for example, approximatcly ., ' .
: , .
~0 ~0609~3 200 ohm-cr. can be used as the n type substrate. The use of such substrate causes a large decrease in voltage due to the flow of a current produced on account of the avalanche breakdown, thereby causing the potential of the surface portion of the substrate 1 right below the qate electrode region to approach readily that of a voltage applied to the source and drain regions, so that the tunnel effect becomes likely to be easily produced. Namely, a sufficient degree of voltage ~ecrease necessary for the writing operation is attained with a slight amount of avalanche currentO If the avalanche withstand voltage in the "0" conditi.on is lower than a voltage necessary or the write operation due to the tunnel effect, the writinq of information in accordance with the avalanche-tunnel injection will be executed with the suhstantially same level of voltage as that of a voltage necessary for the write operation due to the tunnel effectu The use of the above-mentioned high resistivity substrate, however~ produces an inconvenience in forming the peripheral circuit of the memory on the same substrate by integrated circuits. For example~ in the case of the high resistivity substrate, the depletion layer is enlarged to cause an interference between the P+ diffusion layers, and for the purpose of suppressing the enlargement of the depletion layer it becomes necessary to form an n+ layer on the same chip by the ion implantation process in forming an LSI memory.
In order to solve the problems concerning the above-stated complication of the manufacturing process and memory construction let us consider here what phenomena take place in effecting the writing-in of information with respect to the MNOS memory using an n type substrate having a resistivity of several ohmcmO
Where the channel length is large, the depletion layers spread from the source and drain regions 2 and 3 are spaced as indicated by dotted lines of ~ig. 2 in the write operation using avalanche-tunnel injection. An avalanche current indicated by the flow of electrons in arrow-indicated directions is freely flowed in the direction of the thickness of the su~strate 1, and simultaneously is flowed through the surface of the substrate 1 in the direction of the channel width as indicated by arrows e of Fig. 3. For this reason, the avalanche current path is enlarged to cause a decrease in resistance, so that it b~comes difficult because of a small voltage drop due to the avalanche current that the sur-face potential of the substrate 1 right below the gate electrode G and in the proximity of the channel center approaches that of a voltage applied to the source and drain regions 2 and 3. Where, for example, an n type substrate having a resistivity of S ohm-cm is used, a rectangular parallelepiped substrate having a size of l~m x l~m x l~m has a resistance of 50 kilo-ohm.
On the other hand, where the channel length is rendered small, a current passage extending from the surface of the sub-strate into the interior thereof is shielded by depletion layers spread from both the source and drain regions 2 and 3 as shown by dotted lines of Fig. 4. However, also in this case, a current passage along the direction of the channel width exists in the surface of the substrate 1 similarly to the case shown ln Figs.
2 and 3. According to experiments, in a memory 5~ in channel length and 36~ in channel width, a writing-in voltase necessary for the avalanche-tunnel injection is required to have a level ten or ten-odd volts higher than a voltage necessary for the write operation by the usual tunnel injection, and an avalanche current flowed at this time in the source and drain junctions is required to be about 1 to several milliamperes. Further, in a memory large in channel width, a clear difference is considered to be produced between the proximity of the center of the gate electrode and the proximity of the end portions of the gate as viewed in the direction of the channel width, i~n respect of the amount of electrons injected into the traps due to the voltage reduction caused by the current flow. This can be confirmed by ,, ~ - 4 -` 1060993 the fact that, according to experiments, the MNOS memory has a small~r mutual conductance gm after the write .j , .
i , .
.
.'~ ' , , ' , ' "`.
`;
: ~ 4a -operation by the avalanche-tunnel injection than after the usual write operation executed by applying a positive voltage to the gate electrode with respect to the substrate, and it is substan- ,~
tiated from the above that the foregoing consideration is qualitatively right.
This invention has been achieved in accordance with the foregoing consideration and is intended to provide a nonvolatile ~.
semiconductor memory by means of avalanche-tunnel injeetion ;~
which only requires a smaller amount of avalanehe current neces-sary for the write operation and a lower level of voltage neces-sary therefor.
~ his invention provides a nonvolatile semiconductor memory which is constructed such that during the write operation, r a substrate portion below a substrate surface region right below the gate electrode is shielded by a depletion layer spread from the source and drain regions and simultaneously portions of said substrate surface region along the direetion of the ehannel width are also shielded by depletion layers as above spread or by ehannels formed separately, thereby isolating said substrate surfaee region from the remaining substrate portion to inerease a resistanee for the avalanehe eurrent, thus eausing the potential of the eentral portion of the surfaee region to readily approaeh that of the souree and drain regions due to the action of only a small amount of current. According to the present invention there is provided a nonvolatile semieonduetor memory eomprising a semieonduetor substrate of one eonductivity type; souree and drain regions of the other eonduetivity type formed apart from eaeh other in surfaee regions on one side of said substrate; a gate insulation film eonsisting of a very thin oxide film formed on said substrate surfaee between said souree and drain regions and a nitride film formed on said oxide film; souree, drain and first gate eleetrodes respeetively -- ~06Q993 formed on said source and drain regions and said gate insulation film; and means for effecting writing-in of information by eject-ing carriers ~rom said s-lbstrate surface region between said source and drain regions into electron traps in said silicon ni-tride film which means includes means for impressing ground potential to the semiconductor substrate and the first gate electrode and a predetermined negative voltage to the source and t' drain electrodes so as to form depletion layers; said memory fur- L~
ther comprising means for forming a depletion layer which sur- f rounds completely the substrate surface region right under the gate insulation film at the time of effecting writing-in of in-formation; means for allowing the potential of said substrate ~;
surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting car-riers into said surface region.
Referring to Figs. 5 and 6, an island-shaped p type source region 22 and an annular p+ type drain region 23 enclosing said source region 22 are formed in an n type silicon substrate 21 having a resistance of several, for example, five ohm-cm by the conventional process. A silicon oxide layer ~ having an extremely small thickness of less than 35 angstroms, or prefer-ably less than 20 angstroms and a silicon nitride film 25 having a thickness of, for example, 500 angstroms are laminated in turn on a prescribed portion between the source region 22 and the drain region 23 in a manner bridged therebetween. Further, a source electrode 26, drain electrode 27 and gate electrode 28 are arranged in the illustrated form. Thus is formed an MNOS
memory. The surface of the substrate 21 is insulated from the source electrode 26 and from the drain electrode 27, respective, ly, by a laminated mass consisting of a silicon oxide layer 30 and a silicon nitride layer 31.
For the purpose of effecting the avalanche-tunnel in-jection in the above-constructed MNOS memory, the gate electrode !, ~ -- 6 .
--" 1060993 injection in the above-constructed MNOS memory, the gate electrode 28 and the substrate 21 are respectively grounded as shown in Fig. 6, and a : - r ~ 6a -, , ~.
~060993 switch 32 is closed to apply a negative voltage to both the source and drain electrodes 26 and 27 from a power source 33, which causes an surface avalanche breakdown near the junctions between the substrate 21 and the source region 22 and between the substrate and the drain region 23. At this time, a surface region I of the substrate 21 right below the gate layers 24 and 25 of the MNOS
memory, that is, the downward directions of the channel are shielded from the remaining region II of the substrate 21 by a dotted lines-indicated depletion layer 34 spread from the source region 22 and the drain region 23. On the other hand~ a portion of said surface region I along the direction of the channel width constitutes an annular closing region defined by the source and drain regions 22 and 23, so that a portion of said surface region I right below the gate electrode 28 is also wholly isolated from the substrate region II by the depletion layer. Accordingly, the resistance of the substrate 21 for an avalanche current flowed from the region I to the region II due to the avalanche breakdown taking place in the source and drain junctions becomes extremely high, so that the voltage drop sufficient to permit the potential of the region I to approach that of the source and drain regions can readily be attained by the decrease in the write voltage 33 and the decrease in the amount of a current flowed in the depletion layer 34. That is, the writing of info~mation by the avalanche-tunnel can be executed with a small amount of current and a low level of voltage.
Explanation will hereinafter be given of to what extent the characteristics of the semiconductor memory have actually been improved by the present invention, while comparing the experimental results concerning a prior art NNOS memory having the construction ; of Fig. 1 with those concerning an MNOS memory according to the embodiment shown in Figs. 5 and 6, when said both memories being prepared on the same chip. The experiment was made for an NNOS
memory which gate portion has a channel length of 5~ and a channel width of 20~ and which substrate has an impurity concentration of ~0609C~3 /cm , as any of the prior art and the present MNOS memery. The silicon-oxide film and silicon-nitride film constituting the laminated insulation layer of the gate portion are respectively 15.4 ~ and 400 ~ thick, in which respect the present invention was ~ade identical to the prior art.
While the substrate, source region and drain region were respec-tively grounded, a DC voltage of -30 volts was impressed upon the gate to obtain a threshold value, i.e., initial value of -7 volts, and thereafter the following experiments were made. The curves A, B and C of Fig. 7 respectively represent the threshold voltage values of both the prior art and the present MNOS memory after the write operations, which were executed with a volta~e pulse having a pulse amplitude plotted on the abscissa and with a pulse time width of 10 microseconds~ after setting said both MNOS memories at an initial value of -7 volts. This pulse width of 10 microseconds is obtained correspondingly to the width of a time during which the switch 32 of Fig. 6 is closed. The curve C of Fig. 7 represents the threshold voltage values of the memory after the write operation using the usual tunnel injection with a positive gate voltage pulse whose amplitude was plotted on the abscissa, and whose pulse width was 10 microseconds. In the write mode, the positive voltage pulse has been applied to the gate while the substrate, source region and drain region of either one of the prior art MNOS memory of Fig. 1 and the present MNOS memory of Figs. 5 and 6 are respectively grounded. The characteristic indicated by the curve C applies to ; both of the prior art and the present MNOS memory. The curves A
and B of Fig. 7 represent changes in the threshold voltages of the present and the prior art MNOS memory, repsectively, after applying a negative voltage having an amplitude plotted on the abscissa and a pulse width of 10 microseconds commonly upon the drain and source regions with the gate and the substrate grounded.
As is understood from the curve C of Fig. 7, where it is desired to increase the threshold voltage up to a level of, for - 8 _ example, -1 volt, a voltage of +25 volts is only required for any of both memories in the case of the usual write operation by applying a positive voltage to the gate. ~s is understood from thè curves A
and B of Fig. 7, where the avalanche-tunnel in~ection method is utilized, the increase of the threshold voltage up to a level of -1 volt requires a voltage of -29.6 volts (see the curve A denoting the present case) and a voltage of -35.3 volts (see the curve B
indicating the prior art case~, respectively. As a result, according to the invention, reduction in writing-in voltage by the extent of approximately 5.7 volts is possible. Further, in the case of impressing a negative voltage upon the gate it is possible to execute the write operation with an increase in voltage by the extent of
In this manner, injection of electrons into traps within the silicon-nitride film 5 extending along the entire length of the r gate electrode region is effected to cause the .
' - la -~.~ ,...
; ~060993 .
threshold volta~e of the gate elec~rode to be shifted in a posi-tive direction. If this threshold voltage shifted in a positive direction is defined as, for example, "1", and the threshold voltage shifted in a negative direction is defined as, for example, "0", two values of information "1" and "0" will be stored in the semiconductor memory in a nonvolatile state due to the difference between said both threshold voltages.
The condition in~which the information value "1" is written in the semiconductor memory of Fig. 1 is restored to the "0" condition by applying a voltage having a potential of zero to the source and drain electrodes 6 and 8 and applying a nega-tive voltage to the gate electrode. That is, restoration to the "0" condition is executed by causing electrons injected into the electron traps of the silicon-nitride film 5 to be ejected into the substrate 1 through the oxide film 4 utilizing the tunnel effect. The MNOS memory based on the use of a writing method utilizing the tunnel effect produced as the surface potential of the substrate 1 approaches the potential of the source and drain regions 2 and 3 due to the afores~id avalanche effect (namely, the writing method utilizing the avalanche-tunnel injection) has the following drawbacks. First, where a usual substrate having a resistivity of several ohm.cm is used, it is necessary that a large current is flowed in the source and drain junctions and also that a high writing voltage is applied to these junctions.
This fact becomes a great obstruction when this type of memory is integrated into a large scale memory. Particularly, the fact that a large avalanche current is required means that when con-sideration is given to the number of memory elements or MOS tran-sistors series-connected to one memory element, the construction of a large scale integrated circuit (LSI) re~uires an extremely high power source voltage and simultaneously imposes a limitation on the writing-in speed.
- ~0~0993 Whcre it is dcsired to eliminatc the forcgoing draw-backs, a substrate having as high a resistivity as, for example, approximatcly ., ' .
: , .
~0 ~0609~3 200 ohm-cr. can be used as the n type substrate. The use of such substrate causes a large decrease in voltage due to the flow of a current produced on account of the avalanche breakdown, thereby causing the potential of the surface portion of the substrate 1 right below the qate electrode region to approach readily that of a voltage applied to the source and drain regions, so that the tunnel effect becomes likely to be easily produced. Namely, a sufficient degree of voltage ~ecrease necessary for the writing operation is attained with a slight amount of avalanche currentO If the avalanche withstand voltage in the "0" conditi.on is lower than a voltage necessary or the write operation due to the tunnel effect, the writinq of information in accordance with the avalanche-tunnel injection will be executed with the suhstantially same level of voltage as that of a voltage necessary for the write operation due to the tunnel effectu The use of the above-mentioned high resistivity substrate, however~ produces an inconvenience in forming the peripheral circuit of the memory on the same substrate by integrated circuits. For example~ in the case of the high resistivity substrate, the depletion layer is enlarged to cause an interference between the P+ diffusion layers, and for the purpose of suppressing the enlargement of the depletion layer it becomes necessary to form an n+ layer on the same chip by the ion implantation process in forming an LSI memory.
In order to solve the problems concerning the above-stated complication of the manufacturing process and memory construction let us consider here what phenomena take place in effecting the writing-in of information with respect to the MNOS memory using an n type substrate having a resistivity of several ohmcmO
Where the channel length is large, the depletion layers spread from the source and drain regions 2 and 3 are spaced as indicated by dotted lines of ~ig. 2 in the write operation using avalanche-tunnel injection. An avalanche current indicated by the flow of electrons in arrow-indicated directions is freely flowed in the direction of the thickness of the su~strate 1, and simultaneously is flowed through the surface of the substrate 1 in the direction of the channel width as indicated by arrows e of Fig. 3. For this reason, the avalanche current path is enlarged to cause a decrease in resistance, so that it b~comes difficult because of a small voltage drop due to the avalanche current that the sur-face potential of the substrate 1 right below the gate electrode G and in the proximity of the channel center approaches that of a voltage applied to the source and drain regions 2 and 3. Where, for example, an n type substrate having a resistivity of S ohm-cm is used, a rectangular parallelepiped substrate having a size of l~m x l~m x l~m has a resistance of 50 kilo-ohm.
On the other hand, where the channel length is rendered small, a current passage extending from the surface of the sub-strate into the interior thereof is shielded by depletion layers spread from both the source and drain regions 2 and 3 as shown by dotted lines of Fig. 4. However, also in this case, a current passage along the direction of the channel width exists in the surface of the substrate 1 similarly to the case shown ln Figs.
2 and 3. According to experiments, in a memory 5~ in channel length and 36~ in channel width, a writing-in voltase necessary for the avalanche-tunnel injection is required to have a level ten or ten-odd volts higher than a voltage necessary for the write operation by the usual tunnel injection, and an avalanche current flowed at this time in the source and drain junctions is required to be about 1 to several milliamperes. Further, in a memory large in channel width, a clear difference is considered to be produced between the proximity of the center of the gate electrode and the proximity of the end portions of the gate as viewed in the direction of the channel width, i~n respect of the amount of electrons injected into the traps due to the voltage reduction caused by the current flow. This can be confirmed by ,, ~ - 4 -` 1060993 the fact that, according to experiments, the MNOS memory has a small~r mutual conductance gm after the write .j , .
i , .
.
.'~ ' , , ' , ' "`.
`;
: ~ 4a -operation by the avalanche-tunnel injection than after the usual write operation executed by applying a positive voltage to the gate electrode with respect to the substrate, and it is substan- ,~
tiated from the above that the foregoing consideration is qualitatively right.
This invention has been achieved in accordance with the foregoing consideration and is intended to provide a nonvolatile ~.
semiconductor memory by means of avalanche-tunnel injeetion ;~
which only requires a smaller amount of avalanehe current neces-sary for the write operation and a lower level of voltage neces-sary therefor.
~ his invention provides a nonvolatile semiconductor memory which is constructed such that during the write operation, r a substrate portion below a substrate surface region right below the gate electrode is shielded by a depletion layer spread from the source and drain regions and simultaneously portions of said substrate surface region along the direetion of the ehannel width are also shielded by depletion layers as above spread or by ehannels formed separately, thereby isolating said substrate surfaee region from the remaining substrate portion to inerease a resistanee for the avalanehe eurrent, thus eausing the potential of the eentral portion of the surfaee region to readily approaeh that of the souree and drain regions due to the action of only a small amount of current. According to the present invention there is provided a nonvolatile semieonduetor memory eomprising a semieonduetor substrate of one eonductivity type; souree and drain regions of the other eonduetivity type formed apart from eaeh other in surfaee regions on one side of said substrate; a gate insulation film eonsisting of a very thin oxide film formed on said substrate surfaee between said souree and drain regions and a nitride film formed on said oxide film; souree, drain and first gate eleetrodes respeetively -- ~06Q993 formed on said source and drain regions and said gate insulation film; and means for effecting writing-in of information by eject-ing carriers ~rom said s-lbstrate surface region between said source and drain regions into electron traps in said silicon ni-tride film which means includes means for impressing ground potential to the semiconductor substrate and the first gate electrode and a predetermined negative voltage to the source and t' drain electrodes so as to form depletion layers; said memory fur- L~
ther comprising means for forming a depletion layer which sur- f rounds completely the substrate surface region right under the gate insulation film at the time of effecting writing-in of in-formation; means for allowing the potential of said substrate ~;
surface regions completely enclosed by said depletion layer to approach that of said source and drain regions by injecting car-riers into said surface region.
Referring to Figs. 5 and 6, an island-shaped p type source region 22 and an annular p+ type drain region 23 enclosing said source region 22 are formed in an n type silicon substrate 21 having a resistance of several, for example, five ohm-cm by the conventional process. A silicon oxide layer ~ having an extremely small thickness of less than 35 angstroms, or prefer-ably less than 20 angstroms and a silicon nitride film 25 having a thickness of, for example, 500 angstroms are laminated in turn on a prescribed portion between the source region 22 and the drain region 23 in a manner bridged therebetween. Further, a source electrode 26, drain electrode 27 and gate electrode 28 are arranged in the illustrated form. Thus is formed an MNOS
memory. The surface of the substrate 21 is insulated from the source electrode 26 and from the drain electrode 27, respective, ly, by a laminated mass consisting of a silicon oxide layer 30 and a silicon nitride layer 31.
For the purpose of effecting the avalanche-tunnel in-jection in the above-constructed MNOS memory, the gate electrode !, ~ -- 6 .
--" 1060993 injection in the above-constructed MNOS memory, the gate electrode 28 and the substrate 21 are respectively grounded as shown in Fig. 6, and a : - r ~ 6a -, , ~.
~060993 switch 32 is closed to apply a negative voltage to both the source and drain electrodes 26 and 27 from a power source 33, which causes an surface avalanche breakdown near the junctions between the substrate 21 and the source region 22 and between the substrate and the drain region 23. At this time, a surface region I of the substrate 21 right below the gate layers 24 and 25 of the MNOS
memory, that is, the downward directions of the channel are shielded from the remaining region II of the substrate 21 by a dotted lines-indicated depletion layer 34 spread from the source region 22 and the drain region 23. On the other hand~ a portion of said surface region I along the direction of the channel width constitutes an annular closing region defined by the source and drain regions 22 and 23, so that a portion of said surface region I right below the gate electrode 28 is also wholly isolated from the substrate region II by the depletion layer. Accordingly, the resistance of the substrate 21 for an avalanche current flowed from the region I to the region II due to the avalanche breakdown taking place in the source and drain junctions becomes extremely high, so that the voltage drop sufficient to permit the potential of the region I to approach that of the source and drain regions can readily be attained by the decrease in the write voltage 33 and the decrease in the amount of a current flowed in the depletion layer 34. That is, the writing of info~mation by the avalanche-tunnel can be executed with a small amount of current and a low level of voltage.
Explanation will hereinafter be given of to what extent the characteristics of the semiconductor memory have actually been improved by the present invention, while comparing the experimental results concerning a prior art NNOS memory having the construction ; of Fig. 1 with those concerning an MNOS memory according to the embodiment shown in Figs. 5 and 6, when said both memories being prepared on the same chip. The experiment was made for an NNOS
memory which gate portion has a channel length of 5~ and a channel width of 20~ and which substrate has an impurity concentration of ~0609C~3 /cm , as any of the prior art and the present MNOS memery. The silicon-oxide film and silicon-nitride film constituting the laminated insulation layer of the gate portion are respectively 15.4 ~ and 400 ~ thick, in which respect the present invention was ~ade identical to the prior art.
While the substrate, source region and drain region were respec-tively grounded, a DC voltage of -30 volts was impressed upon the gate to obtain a threshold value, i.e., initial value of -7 volts, and thereafter the following experiments were made. The curves A, B and C of Fig. 7 respectively represent the threshold voltage values of both the prior art and the present MNOS memory after the write operations, which were executed with a volta~e pulse having a pulse amplitude plotted on the abscissa and with a pulse time width of 10 microseconds~ after setting said both MNOS memories at an initial value of -7 volts. This pulse width of 10 microseconds is obtained correspondingly to the width of a time during which the switch 32 of Fig. 6 is closed. The curve C of Fig. 7 represents the threshold voltage values of the memory after the write operation using the usual tunnel injection with a positive gate voltage pulse whose amplitude was plotted on the abscissa, and whose pulse width was 10 microseconds. In the write mode, the positive voltage pulse has been applied to the gate while the substrate, source region and drain region of either one of the prior art MNOS memory of Fig. 1 and the present MNOS memory of Figs. 5 and 6 are respectively grounded. The characteristic indicated by the curve C applies to ; both of the prior art and the present MNOS memory. The curves A
and B of Fig. 7 represent changes in the threshold voltages of the present and the prior art MNOS memory, repsectively, after applying a negative voltage having an amplitude plotted on the abscissa and a pulse width of 10 microseconds commonly upon the drain and source regions with the gate and the substrate grounded.
As is understood from the curve C of Fig. 7, where it is desired to increase the threshold voltage up to a level of, for - 8 _ example, -1 volt, a voltage of +25 volts is only required for any of both memories in the case of the usual write operation by applying a positive voltage to the gate. ~s is understood from thè curves A
and B of Fig. 7, where the avalanche-tunnel in~ection method is utilized, the increase of the threshold voltage up to a level of -1 volt requires a voltage of -29.6 volts (see the curve A denoting the present case) and a voltage of -35.3 volts (see the curve B
indicating the prior art case~, respectively. As a result, according to the invention, reduction in writing-in voltage by the extent of approximately 5.7 volts is possible. Further, in the case of impressing a negative voltage upon the gate it is possible to execute the write operation with an increase in voltage by the extent of
4.6 volts in terms of the absolute value as compared with the case where information is written by applying a positive voltage to the gate.
In the embodiment shown in Figs. 8 and 9, the same parts and sections as those of Figs. 5 and 6 are denoted by the same reference numerals. This embodiment is intended to shield the substrate surface region below the gate electrode 28 along the direction of the channel width oy means of two MOS transistors Ml and M2, That is, elongate p+ type regions 22a and 23a are formed in the surface portion of the n type substrate 21, and are used as the source and drain regions, respectively. The source electrode 26 and the drain electrode 27 are respectively formed on the ends at one side of the source region 22a and drain region 23a. Another electrode 28 is formed in a manner bridged between the source region 22a and the drain region 23a, and are used as the MNOS memory gate electrode.
A letter "C"-shaped electrode 40 is formed bridged between the source region 22a and the drain region 23a in a manner surrounding the gate electrode 28. Thus, said two MOS transistors Ml and M2 are formed in the width direction of a channel formed below the gate electrode 28.
If, in the memory constructed as mentioned above, at the time _ 9 _ . . :, : -. : ~ -1~60993 of e~ecuting the write operation using avalanche-tunnel injection, a negative voltage is impressed upon the source electrode 26 and drain electrode 27, respectively~ and simultaneously upon the control gate electrode 40 of the MOS transistors Ml and M2 from the power source 42, the lengthwise and the downward direction of a channel 43 of the MNOS memory will be shielded by a depletion layer 34 spread from the source re~ion 22a and drain region 23a, and the width direction of the channel 43 will be shielded by the depletion layer and the channels 44 formed below the gates of the MOS tran-sistors Ml and M2, whereby a substrate surface region below thegate is shielded from the remaining portion of the substrate 21.
Accordingly, similarly to the embodiment shown in Figs. 5 and 6, the potential of a surface region of the substrate 21 beneath the gate of the MNOS memory readily approaches that of the source and drain regions due to a voltage reduction caused by an avalanche breakdown current, thereby enabling the writing-in of information by the avalanche-tunnel injection to be executed with a low level of voltage and a small amount of current.
Fig. 10 illustrates a modification of the MOS transistor M
shown in Fig. 9. Also where~ in this modification, the control gate electrode 40 is formed on an insulation layer 41a having a uniform thickness, and a negative voltage is applied to the electrode 40 from the power source 42, the formation of a depletion layer or channel is effected similarly to Fig. 9 to obtain a similar shielding effect. It should be noted that the use of a so-called parasitic MOS transistor as the foregoing MOS transistor also causes a similar effect to be obtained.
As apparent from the foregoing description, this invention enables a voltage necessary for the write operation by the avalanche-tunnel in~ection to be reduced as a principle in level-substantially to a voltage necessary for the write operation by the tunnel inject-tion. Further, a current necessary for the avalanche-tunnel in~ection has only to have a value required to charge the isolated substrate 106~9C~3 surface region beneath the gate, for example, an avalanche current value of approximately 10 microampheres. The fact that the writing-in of information can be executed with a low level of voltage and a small amount of current means that a low level of power source voltage is only required in forming a large scale integrated circuit memory and that the information writing-in speed is increased.
Further, the fact that a substrate having a low specific resistance can be used is advantageous to the high density integration because of little mutual interference being made due to the spread of the lQ depletion layer.
The nonvolatile semiconductor memory of the invention can of course be formed not only of the p channel MNOS memory but also of an n channel MNOS memory.
., .
In the embodiment shown in Figs. 8 and 9, the same parts and sections as those of Figs. 5 and 6 are denoted by the same reference numerals. This embodiment is intended to shield the substrate surface region below the gate electrode 28 along the direction of the channel width oy means of two MOS transistors Ml and M2, That is, elongate p+ type regions 22a and 23a are formed in the surface portion of the n type substrate 21, and are used as the source and drain regions, respectively. The source electrode 26 and the drain electrode 27 are respectively formed on the ends at one side of the source region 22a and drain region 23a. Another electrode 28 is formed in a manner bridged between the source region 22a and the drain region 23a, and are used as the MNOS memory gate electrode.
A letter "C"-shaped electrode 40 is formed bridged between the source region 22a and the drain region 23a in a manner surrounding the gate electrode 28. Thus, said two MOS transistors Ml and M2 are formed in the width direction of a channel formed below the gate electrode 28.
If, in the memory constructed as mentioned above, at the time _ 9 _ . . :, : -. : ~ -1~60993 of e~ecuting the write operation using avalanche-tunnel injection, a negative voltage is impressed upon the source electrode 26 and drain electrode 27, respectively~ and simultaneously upon the control gate electrode 40 of the MOS transistors Ml and M2 from the power source 42, the lengthwise and the downward direction of a channel 43 of the MNOS memory will be shielded by a depletion layer 34 spread from the source re~ion 22a and drain region 23a, and the width direction of the channel 43 will be shielded by the depletion layer and the channels 44 formed below the gates of the MOS tran-sistors Ml and M2, whereby a substrate surface region below thegate is shielded from the remaining portion of the substrate 21.
Accordingly, similarly to the embodiment shown in Figs. 5 and 6, the potential of a surface region of the substrate 21 beneath the gate of the MNOS memory readily approaches that of the source and drain regions due to a voltage reduction caused by an avalanche breakdown current, thereby enabling the writing-in of information by the avalanche-tunnel injection to be executed with a low level of voltage and a small amount of current.
Fig. 10 illustrates a modification of the MOS transistor M
shown in Fig. 9. Also where~ in this modification, the control gate electrode 40 is formed on an insulation layer 41a having a uniform thickness, and a negative voltage is applied to the electrode 40 from the power source 42, the formation of a depletion layer or channel is effected similarly to Fig. 9 to obtain a similar shielding effect. It should be noted that the use of a so-called parasitic MOS transistor as the foregoing MOS transistor also causes a similar effect to be obtained.
As apparent from the foregoing description, this invention enables a voltage necessary for the write operation by the avalanche-tunnel in~ection to be reduced as a principle in level-substantially to a voltage necessary for the write operation by the tunnel inject-tion. Further, a current necessary for the avalanche-tunnel in~ection has only to have a value required to charge the isolated substrate 106~9C~3 surface region beneath the gate, for example, an avalanche current value of approximately 10 microampheres. The fact that the writing-in of information can be executed with a low level of voltage and a small amount of current means that a low level of power source voltage is only required in forming a large scale integrated circuit memory and that the information writing-in speed is increased.
Further, the fact that a substrate having a low specific resistance can be used is advantageous to the high density integration because of little mutual interference being made due to the spread of the lQ depletion layer.
The nonvolatile semiconductor memory of the invention can of course be formed not only of the p channel MNOS memory but also of an n channel MNOS memory.
., .
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A metal-nitride-oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elon-gated p-type drain region in the surface of said substrate run-ning parallel to said elongated source region; a first gate insulation film consisting of a thin oxide film formed on a sub-strate surface region between said elongated source and drain regions; a silicon-nitride film formed on said first gate insula-tion film; first and second metal-oxide-semiconductor field-effect transistors, the source and drain of each of said tran-sistors being said elongated source and drain regions, said transistors being positioned respectively on either side of said first gate insulation film and having respectively second and third gate insulation films between said elongated source and drain regions; source, drain, and first, second and third gate electrodes respectively formed on said elongated source and drain regions, and said silicon nitride, second and third gate insulation film, said second and third gate electrodes being separated from said first gate electrode; means for effecting an initial threshold value at said first gate electrode by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground potential to said sub-strate and to said first gate electrode and a predetermined nega-tive potential to said source, drain and second and third gate electrodes so as to form a depletion layer which surrounds com-pletely the substrate surface region under said first gate insul-ation film at the time of effecting writing-in of information;
and means for allowing the potential of said substrate surface region completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
and means for allowing the potential of said substrate surface region completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
2. A metal-nitride oxide semiconductor memory device comprising: a semiconductor n-type substrate; an elongated p-type source region in the surface of said substrate; an elongated p-type drain region in the surface of said substrate running parallel to said elongated source region; a gate insulation film consisting of a thin oxide film formed on a substrate surface region between said elongated source and drain regions; a silicon-nitride film formed on said gate insulation film; first and second electrode insulation films extending between said elon-gated source and drain regions, said first and second electrode insulation films being positioned respectively on either side of said gate insulation film; source, drain, gate, and first and second control electrodes respectively formed on said elongated source and drain regions, said silicon nitride and said first and second electrode insulation films, said first and second control electrodes being separated from said gate electrode;
means for effecting an initial threshold value at said first gate electrode by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground poten-tial to said substrate and to said first gate electrode and a predetermined negative potential to said source, said drain and said first and second control electrodes so as to form a deple-tion layer which surrounds completely the substrate surface region under said gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface region completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
means for effecting an initial threshold value at said first gate electrode by ejecting carriers from said substrate surface region between said source and drain regions into electron traps in said silicon-nitride film; means for impressing ground poten-tial to said substrate and to said first gate electrode and a predetermined negative potential to said source, said drain and said first and second control electrodes so as to form a deple-tion layer which surrounds completely the substrate surface region under said gate insulation film at the time of effecting writing-in of information; and means for allowing the potential of said substrate surface region completely enclosed by said depletion layer to approach that of said source and drain regions by injecting carriers into said surface region.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10679373A JPS5613029B2 (en) | 1973-09-21 | 1973-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1060993A true CA1060993A (en) | 1979-08-21 |
Family
ID=14442758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA208,942A Expired CA1060993A (en) | 1973-09-21 | 1974-09-11 | Nonvolatile semiconductor memory |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS5613029B2 (en) |
| CA (1) | CA1060993A (en) |
| DE (1) | DE2444906C3 (en) |
| GB (1) | GB1474745A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5458376A (en) * | 1977-10-19 | 1979-05-11 | Agency Of Ind Science & Technol | Semiconductor memory unit and its writing method |
| US4375087C1 (en) * | 1980-04-09 | 2002-01-01 | Hughes Aircraft Co | Electrically erasable programmable read-only memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1175601A (en) * | 1966-03-28 | 1969-12-23 | Matsushita Electronics Corp | Insulated-Gate Field-Effect Transistor |
| DE2201028C3 (en) * | 1971-01-15 | 1981-07-09 | Intel Corp., Mountain View, Calif. | Method for operating a field effect transistor and field effect transistor for carrying out this method |
-
1973
- 1973-09-21 JP JP10679373A patent/JPS5613029B2/ja not_active Expired
-
1974
- 1974-09-09 GB GB3924474A patent/GB1474745A/en not_active Expired
- 1974-09-11 CA CA208,942A patent/CA1060993A/en not_active Expired
- 1974-09-19 DE DE19742444906 patent/DE2444906C3/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2444906B2 (en) | 1981-05-27 |
| DE2444906A1 (en) | 1975-04-24 |
| DE2444906C3 (en) | 1982-02-04 |
| GB1474745A (en) | 1977-05-25 |
| JPS5613029B2 (en) | 1981-03-25 |
| JPS5057779A (en) | 1975-05-20 |
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