CA1023876A - Methode permettant la realisation d'interconnexions electroniques a l'epreuve de la corrosion - Google Patents

Methode permettant la realisation d'interconnexions electroniques a l'epreuve de la corrosion

Info

Publication number
CA1023876A
CA1023876A CA210,639A CA210639A CA1023876A CA 1023876 A CA1023876 A CA 1023876A CA 210639 A CA210639 A CA 210639A CA 1023876 A CA1023876 A CA 1023876A
Authority
CA
Canada
Prior art keywords
formation
corrosion resistant
resistant electronic
electronic interconnections
interconnections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA210,639A
Other languages
English (en)
Other versions
CA210639S (en
Inventor
Herbert C. Cook
Paul A. Farrar
Robert L. Hallen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA1023876A publication Critical patent/CA1023876A/fr
Expired legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physical Vapour Deposition (AREA)
  • Laminated Bodies (AREA)
CA210,639A 1973-10-12 1974-10-03 Methode permettant la realisation d'interconnexions electroniques a l'epreuve de la corrosion Expired CA1023876A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US406125A US3881884A (en) 1973-10-12 1973-10-12 Method for the formation of corrosion resistant electronic interconnections

Publications (1)

Publication Number Publication Date
CA1023876A true CA1023876A (fr) 1978-01-03

Family

ID=23606638

Family Applications (1)

Application Number Title Priority Date Filing Date
CA210,639A Expired CA1023876A (fr) 1973-10-12 1974-10-03 Methode permettant la realisation d'interconnexions electroniques a l'epreuve de la corrosion

Country Status (11)

Country Link
US (1) US3881884A (fr)
JP (1) JPS5310430B2 (fr)
BR (1) BR7408490D0 (fr)
CA (1) CA1023876A (fr)
CH (1) CH569363A5 (fr)
DE (1) DE2440481C3 (fr)
FR (1) FR2247820B1 (fr)
GB (1) GB1448034A (fr)
IT (1) IT1020141B (fr)
NL (1) NL7413310A (fr)
SE (1) SE401291B (fr)

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JPS5534414A (en) * 1978-09-01 1980-03-11 Sumitomo Bakelite Co Method of manufacturing printed circuit board
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
US4290079A (en) * 1979-06-29 1981-09-15 International Business Machines Corporation Improved solder interconnection between a semiconductor device and a supporting substrate
US4360142A (en) * 1979-06-29 1982-11-23 International Business Machines Corporation Method of forming a solder interconnection capable of sustained high power levels between a semiconductor device and a supporting substrate
US4319264A (en) 1979-12-17 1982-03-09 International Business Machines Corporation Nickel-gold-nickel conductors for solid state devices
US4335506A (en) * 1980-08-04 1982-06-22 International Business Machines Corporation Method of forming aluminum/copper alloy conductors
JPS57141942A (en) * 1981-02-27 1982-09-02 Fuji Electric Corp Res & Dev Ltd Formation of bump electrode
DE3107857C2 (de) * 1981-03-02 1984-08-23 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung von Dünnfilmschaltungen mit sehr gut lötbaren Leiterbahnschichtsystemen
DE3107943A1 (de) * 1981-03-02 1982-09-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung von loetbaren und temperfaehigen edelmetallfreien duennschichtleiterbahnen
US4505029A (en) * 1981-03-23 1985-03-19 General Electric Company Semiconductor device with built-up low resistance contact
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
US4396900A (en) * 1982-03-08 1983-08-02 The United States Of America As Represented By The Secretary Of The Navy Thin film microstrip circuits
DE3343362A1 (de) * 1983-11-30 1985-06-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zur galvanischen herstellung metallischer, hoeckerartiger anschlusskontakte
US4606788A (en) * 1984-04-12 1986-08-19 Moran Peter L Methods of and apparatus for forming conductive patterns on a substrate
US4851895A (en) * 1985-05-06 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Metallization for integrated devices
US4725877A (en) * 1986-04-11 1988-02-16 American Telephone And Telegraph Company, At&T Bell Laboratories Metallized semiconductor device including an interface layer
US4711791A (en) * 1986-08-04 1987-12-08 The Boc Group, Inc. Method of making a flexible microcircuit
JP2500523B2 (ja) * 1990-12-28 1996-05-29 日本電装株式会社 基板および基板の製造方法
GB2255672B (en) * 1991-05-10 1994-11-30 Northern Telecom Ltd Opto-electronic components
US5288541A (en) * 1991-10-17 1994-02-22 International Business Machines Corporation Method for metallizing through holes in thin film substrates, and resulting devices
EP2270845A3 (fr) 1996-10-29 2013-04-03 Invensas Corporation Circuits intégrés et leurs procédés de fabrication
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
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SE7412333L (fr) 1975-04-14
DE2440481A1 (de) 1975-04-24
DE2440481C3 (de) 1978-08-03
JPS5068082A (fr) 1975-06-07
IT1020141B (it) 1977-12-20
DE2440481B2 (de) 1977-12-01
NL7413310A (nl) 1975-04-15
CH569363A5 (fr) 1975-11-14
SE401291B (sv) 1978-04-24
GB1448034A (en) 1976-09-02
FR2247820A1 (fr) 1975-05-09
US3881884A (en) 1975-05-06
BR7408490D0 (pt) 1975-07-29
JPS5310430B2 (fr) 1978-04-13
FR2247820B1 (fr) 1976-10-22

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