CA1017069A - Microprocessor input/output - Google Patents

Microprocessor input/output

Info

Publication number
CA1017069A
CA1017069A CA209,185A CA209185A CA1017069A CA 1017069 A CA1017069 A CA 1017069A CA 209185 A CA209185 A CA 209185A CA 1017069 A CA1017069 A CA 1017069A
Authority
CA
Canada
Prior art keywords
output
microprocessor input
microprocessor
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA209,185A
Other languages
English (en)
Other versions
CA209185S (en
Inventor
Richard A. Garlic
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xerox Corp
Original Assignee
Xerox Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xerox Corp filed Critical Xerox Corp
Priority to CA264,698A priority Critical patent/CA1018667A/en
Priority to CA264,697A priority patent/CA1018666A/en
Application granted granted Critical
Publication of CA1017069A publication Critical patent/CA1017069A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
CA209,185A 1973-12-26 1974-09-13 Microprocessor input/output Expired CA1017069A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA264,698A CA1018667A (en) 1973-12-26 1976-11-02 Microprocessor input/output
CA264,697A CA1018666A (en) 1973-12-26 1976-11-02 Microprocessor input/output

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/428,597 US3938098A (en) 1973-12-26 1973-12-26 Input/output connection arrangement for microprogrammable computer

Publications (1)

Publication Number Publication Date
CA1017069A true CA1017069A (en) 1977-09-06

Family

ID=23699598

Family Applications (1)

Application Number Title Priority Date Filing Date
CA209,185A Expired CA1017069A (en) 1973-12-26 1974-09-13 Microprocessor input/output

Country Status (5)

Country Link
US (1) US3938098A (enExample)
JP (1) JPS5097245A (enExample)
CA (1) CA1017069A (enExample)
DE (1) DE2452255A1 (enExample)
GB (1) GB1493818A (enExample)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2364253A1 (de) * 1973-12-22 1975-06-26 Olympia Werke Ag Schaltungsanordnung fuer mikroprogrammierte geraete der datenverarbeitung
US4050058A (en) * 1973-12-26 1977-09-20 Xerox Corporation Microprocessor with parallel operation
GB1507178A (en) * 1974-10-30 1978-04-12 Motorola Inc Microprocessor integrated circuit and chip
US4030079A (en) * 1974-10-30 1977-06-14 Motorola, Inc. Processor including incrementor and program register structure
US4263650B1 (en) * 1974-10-30 1994-11-29 Motorola Inc Digital data processing system with interface adaptor having programmable monitorable control register therein
GB1505535A (en) * 1974-10-30 1978-03-30 Motorola Inc Microprocessor system
US4032896A (en) * 1974-10-30 1977-06-28 Motorola, Inc. Microprocessor having index register coupled to serial-coupled address bus sections and to data bus
DE2638125A1 (de) * 1975-09-04 1977-03-17 Tokyo Shibaura Electric Co Datenverarbeitungssystem
US4071887A (en) * 1975-10-30 1978-01-31 Motorola, Inc. Synchronous serial data adaptor
DE2554425C3 (de) * 1975-12-03 1984-01-12 Siemens AG, 1000 Berlin und 8000 München Anordnung zum gegenseitigen Anpassen von Steuersignale austauschenden Geräten
US4225917A (en) * 1976-02-05 1980-09-30 Motorola, Inc. Error driven interrupt for polled MPU systems
US4045782A (en) * 1976-03-29 1977-08-30 The Warner & Swasey Company Microprogrammed processor system having external memory
US4042914A (en) * 1976-05-17 1977-08-16 Honeywell Information Systems Inc. Microprogrammed control of foreign processor control functions
JPS5352029A (en) * 1976-10-22 1978-05-12 Fujitsu Ltd Arithmetic circuit unit
US4213176A (en) * 1976-12-22 1980-07-15 Ncr Corporation System and method for increasing the output data throughput of a computer
US4217638A (en) * 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
US4144562A (en) * 1977-06-23 1979-03-13 Ncr Corporation System and method for increasing microprocessor output data rate
US4228498A (en) * 1977-10-12 1980-10-14 Dialog Systems, Inc. Multibus processor for increasing execution speed using a pipeline effect
JPS5474651A (en) * 1977-11-28 1979-06-14 Toshiba Corp Stack control system
JPS54104251A (en) * 1978-02-02 1979-08-16 Toshiba Corp Data processor
JPS54107643A (en) * 1978-02-13 1979-08-23 Toshiba Corp Operation control method and unit executing structured program
US4314353A (en) * 1978-03-09 1982-02-02 Motorola Inc. On chip ram interconnect to MPU bus
US4213177A (en) * 1978-04-24 1980-07-15 Texas Instruments Incorporated Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards
US4375665A (en) * 1978-04-24 1983-03-01 Texas Instruments Incorporated Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards
US4214302A (en) * 1978-04-24 1980-07-22 Texas Instruments Incorporated Eight bit standard connector bus for sixteen bit microcomputer
US4446533A (en) * 1978-09-07 1984-05-01 National Research Development Corporation Stored program digital data processor
US4648063A (en) * 1978-10-30 1987-03-03 Phillips Petroleum Company Programming a peripheral computer
US4263649A (en) * 1979-01-05 1981-04-21 Mohawk Data Sciences Corp. Computer system with two busses
US4365293A (en) * 1980-03-28 1982-12-21 Pitney Bowes Inc. Serial communications bus for remote terminals
IT1149809B (it) * 1980-06-12 1986-12-10 Honeywell Inf Systems Sequenziatore per unita' di controllo microprogrammata
JPS5757345A (en) * 1980-09-24 1982-04-06 Toshiba Corp Data controller
US4939640A (en) * 1981-05-22 1990-07-03 Data General Corporation Data processing system having unique microinstruction control and stack means
US4551835A (en) * 1983-06-27 1985-11-05 International Business Machines Corporation X.21 Switching system
JPS62126440A (ja) * 1985-11-27 1987-06-08 Nec Corp 情報処理装置
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US4855899A (en) * 1987-04-13 1989-08-08 Prime Computer, Inc. Multiple I/O bus virtual broadcast of programmed I/O instructions
US5018098A (en) * 1987-05-07 1991-05-21 Fujitsu Limited Data transfer controlling apparatus for direct memory access
JPH0648461B2 (ja) * 1987-07-09 1994-06-22 日本電気株式会社 マイクロプログラムの転送レジスタ指定方式
US5230067A (en) * 1988-05-11 1993-07-20 Digital Equipment Corporation Bus control circuit for latching and maintaining data independently of timing event on the bus until new data is driven onto
US5121487A (en) * 1989-02-21 1992-06-09 Sun Microsystems, Inc. High speed bus with virtual memory data transfer capability using virtual address/data lines
AU6642290A (en) * 1989-10-17 1991-05-31 Maurice E. Mitchell A microcomputer with disconnected, open, independent, bimemory architecture

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3462744A (en) * 1966-09-28 1969-08-19 Ibm Execution unit with a common operand and resulting bussing system
US3517171A (en) * 1967-10-30 1970-06-23 Nasa Self-testing and repairing computer
US3646522A (en) * 1969-08-15 1972-02-29 Interdata Inc General purpose optimized microprogrammed miniprocessor
JPS514381B1 (enExample) * 1969-11-24 1976-02-10
US3737861A (en) * 1970-04-01 1973-06-05 Honeywell Inc Input/output bus
US3815099A (en) * 1970-04-01 1974-06-04 Digital Equipment Corp Data processing system
US3745532A (en) * 1970-05-27 1973-07-10 Hughes Aircraft Co Modular digital processing equipment
US3761893A (en) * 1970-07-02 1973-09-25 Modicon Corp Digital computer
US3702988A (en) * 1970-09-14 1972-11-14 Ncr Co Digital processor
US3698007A (en) * 1970-11-30 1972-10-10 Honeywell Inc Central processor unit having simulative interpretation capability
US3757306A (en) * 1971-08-31 1973-09-04 Texas Instruments Inc Computing systems cpu
US3813651A (en) * 1971-12-29 1974-05-28 Tokyo Shibaura Electric Co Data processing system
US3748649A (en) * 1972-02-29 1973-07-24 Bell Telephone Labor Inc Translator memory decoding arrangement for a microprogram controlled processor
US3753236A (en) * 1972-03-31 1973-08-14 Honeywell Inf Systems Microprogrammable peripheral controller
US3815104A (en) * 1973-01-18 1974-06-04 Lexitron Corp Information processing system

Also Published As

Publication number Publication date
JPS5097245A (enExample) 1975-08-02
US3938098A (en) 1976-02-10
DE2452255A1 (de) 1975-07-10
GB1493818A (en) 1977-11-30

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