CA1013867A - Integrated circuit isolation structure and manufacture - Google Patents
Integrated circuit isolation structure and manufactureInfo
- Publication number
- CA1013867A CA1013867A CA192,912A CA192912A CA1013867A CA 1013867 A CA1013867 A CA 1013867A CA 192912 A CA192912 A CA 192912A CA 1013867 A CA1013867 A CA 1013867A
- Authority
- CA
- Canada
- Prior art keywords
- manufacture
- integrated circuit
- isolation structure
- circuit isolation
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H10P50/644—
-
- H10P95/00—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US33449873A | 1973-02-21 | 1973-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1013867A true CA1013867A (en) | 1977-07-12 |
Family
ID=23307490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA192,912A Expired CA1013867A (en) | 1973-02-21 | 1974-02-19 | Integrated circuit isolation structure and manufacture |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS49115688A (en:Method) |
| CA (1) | CA1013867A (en:Method) |
| DE (1) | DE2408402A1 (en:Method) |
| GB (1) | GB1461943A (en:Method) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55153345A (en) * | 1979-05-18 | 1980-11-29 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS56160050A (en) * | 1980-05-14 | 1981-12-09 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US4394196A (en) * | 1980-07-16 | 1983-07-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
| JPS5743438A (en) * | 1980-08-29 | 1982-03-11 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US4630343A (en) * | 1981-03-16 | 1986-12-23 | Fairchild Camera & Instrument Corp. | Product for making isolated semiconductor structure |
| DE3273863D1 (en) * | 1981-03-16 | 1986-11-20 | Fairchild Camera Instr Co | Low temperature melting binary glasses for leveling surfaces of integrated circuits containing isolation grooves |
| US4492717A (en) * | 1981-07-27 | 1985-01-08 | International Business Machines Corporation | Method for forming a planarized integrated circuit |
| KR19980701728A (ko) * | 1995-01-30 | 1998-06-25 | 로렌스 제이.쉬뢰퍼 | 전자장치 및 그의 제조방법 |
-
1974
- 1974-02-01 GB GB482174A patent/GB1461943A/en not_active Expired
- 1974-02-19 CA CA192,912A patent/CA1013867A/en not_active Expired
- 1974-02-20 JP JP49019551A patent/JPS49115688A/ja active Pending
- 1974-02-21 DE DE19742408402 patent/DE2408402A1/de active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB1461943A (en) | 1977-01-19 |
| JPS49115688A (en:Method) | 1974-11-05 |
| DE2408402A1 (de) | 1974-08-22 |
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