CA1003562A - Deskewing buffer arrangement which includes means for detecting and correcting channel errors - Google Patents
Deskewing buffer arrangement which includes means for detecting and correcting channel errorsInfo
- Publication number
- CA1003562A CA1003562A CA184,705A CA184705A CA1003562A CA 1003562 A CA1003562 A CA 1003562A CA 184705 A CA184705 A CA 184705A CA 1003562 A CA1003562 A CA 1003562A
- Authority
- CA
- Canada
- Prior art keywords
- detecting
- includes means
- channel errors
- buffer arrangement
- correcting channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/20—Signal processing not specific to the method of recording or reproducing; Circuits therefor for correction of skew for multitrack recording
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Error Detection And Correction (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US32109473A | 1973-01-04 | 1973-01-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1003562A true CA1003562A (en) | 1977-01-11 |
Family
ID=23249154
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA184,705A Expired CA1003562A (en) | 1973-01-04 | 1973-10-31 | Deskewing buffer arrangement which includes means for detecting and correcting channel errors |
Country Status (8)
Country | Link |
---|---|
US (1) | US3792436A (de) |
JP (1) | JPS5847768B2 (de) |
CA (1) | CA1003562A (de) |
DE (1) | DE2400249C2 (de) |
FR (1) | FR2213716A5 (de) |
GB (1) | GB1423675A (de) |
IT (1) | IT1002570B (de) |
NL (1) | NL184648C (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3803552A (en) * | 1973-05-09 | 1974-04-09 | Honeywell Inf Systems | Error detection and correction apparatus for use in a magnetic tape system |
US3938182A (en) * | 1975-01-06 | 1976-02-10 | The United States Of America As Represented By The United States National Aeronautics And Space Administration Office Of General Counsel-Code Gp | Automatic character skew and spacing checking network |
US4006455A (en) * | 1975-10-10 | 1977-02-01 | Texas Instruments Incorporated | Error correction system in a programmable calculator |
US4044329A (en) * | 1976-07-02 | 1977-08-23 | Honeywell Information Systems, Inc. | Variable cyclic redundancy character detector |
US4115759A (en) * | 1977-08-08 | 1978-09-19 | Honeywell Information Systems Inc. | Multiple bit deskew buffer |
US4298956A (en) * | 1979-05-14 | 1981-11-03 | Honeywell Information Systems Inc. | Digital read recovery with variable frequency compensation using read only memories |
US4803566A (en) * | 1983-08-01 | 1989-02-07 | Eastman Kodak Company | Digital time base correction using a reference bit |
US4839907A (en) * | 1988-02-26 | 1989-06-13 | American Telephone And Telegraph Company, At&T Bell Laboratories | Clock skew correction arrangement |
US5157530A (en) * | 1990-01-18 | 1992-10-20 | International Business Machines Corporation | Optical fiber system |
KR100945488B1 (ko) * | 2003-09-20 | 2010-03-09 | 삼성전자주식회사 | 비터비 검출 장치 및 방법 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
USRE25572E (en) * | 1958-06-30 | 1964-05-12 | Fired silica refractories | |
US3193812A (en) * | 1961-05-16 | 1965-07-06 | Gen Electric | Missing bit detector on recorded storage media |
US3451049A (en) * | 1966-01-19 | 1969-06-17 | Control Data Corp | Skew correction arrangement for parallel track readout devices |
FR2048174A5 (de) * | 1969-06-03 | 1971-03-19 | Cii |
-
1973
- 1973-01-04 US US00321094A patent/US3792436A/en not_active Expired - Lifetime
- 1973-10-31 CA CA184,705A patent/CA1003562A/en not_active Expired
- 1973-11-26 NL NLAANVRAGE7316134,A patent/NL184648C/xx not_active IP Right Cessation
- 1973-12-03 GB GB5584773A patent/GB1423675A/en not_active Expired
- 1973-12-21 JP JP48142546A patent/JPS5847768B2/ja not_active Expired
- 1973-12-28 FR FR7346952A patent/FR2213716A5/fr not_active Expired
- 1973-12-28 IT IT54664/73A patent/IT1002570B/it active
-
1974
- 1974-01-04 DE DE2400249A patent/DE2400249C2/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2213716A5 (de) | 1974-08-02 |
JPS5847768B2 (ja) | 1983-10-25 |
NL184648C (nl) | 1989-09-18 |
GB1423675A (en) | 1976-02-04 |
DE2400249C2 (de) | 1986-11-20 |
NL184648B (nl) | 1989-04-17 |
JPS49103540A (de) | 1974-10-01 |
DE2400249A1 (de) | 1974-08-08 |
IT1002570B (it) | 1976-05-20 |
NL7316134A (de) | 1974-07-08 |
US3792436A (en) | 1974-02-12 |
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