CA1002664A - Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system - Google Patents

Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system

Info

Publication number
CA1002664A
CA1002664A CA185,550A CA185550A CA1002664A CA 1002664 A CA1002664 A CA 1002664A CA 185550 A CA185550 A CA 185550A CA 1002664 A CA1002664 A CA 1002664A
Authority
CA
Canada
Prior art keywords
memory
reconfiguration
automatically
technique
failures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA185,550A
Other languages
English (en)
Other versions
CA185550S (en
Inventor
David D. Devoy
George J. Barlow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1002664A publication Critical patent/CA1002664A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0669—Configuration or reconfiguration with decentralised address assignment
    • G06F12/0676—Configuration or reconfiguration with decentralised address assignment the address being position dependent

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
CA185,550A 1973-01-03 1973-11-09 Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system Expired CA1002664A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00320790A US3803560A (en) 1973-01-03 1973-01-03 Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system

Publications (1)

Publication Number Publication Date
CA1002664A true CA1002664A (en) 1976-12-28

Family

ID=23247879

Family Applications (1)

Application Number Title Priority Date Filing Date
CA185,550A Expired CA1002664A (en) 1973-01-03 1973-11-09 Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system

Country Status (9)

Country Link
US (1) US3803560A (it)
JP (1) JPS594798B2 (it)
AU (1) AU476537B2 (it)
CA (1) CA1002664A (it)
DE (1) DE2400161A1 (it)
FR (1) FR2226081A5 (it)
GB (1) GB1451386A (it)
IT (1) IT1000794B (it)
NL (1) NL186783C (it)

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US6425046B1 (en) 1991-11-05 2002-07-23 Monolithic System Technology, Inc. Method for using a latched sense amplifier in a memory module as a high-speed cache memory

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US4740916A (en) * 1985-12-19 1988-04-26 International Business Machines Corporation Reconfigurable contiguous address space memory system including serially connected variable capacity memory modules and a split address bus
DE3782893T2 (de) * 1986-09-10 1993-04-08 Nippon Electric Co Informationsverarbeitungssystem, faehig zur verminderung ungueltiger speicheroperationen durch erkennung von hauptspeicherfehlern.
US4922451A (en) * 1987-03-23 1990-05-01 International Business Machines Corporation Memory re-mapping in a microcomputer system
US4908789A (en) * 1987-04-01 1990-03-13 International Business Machines Corporation Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
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US5287470A (en) * 1989-12-28 1994-02-15 Texas Instruments Incorporated Apparatus and method for coupling a multi-lead output bus to interleaved memories, which are addressable in normal and block-write modes
US5105425A (en) * 1989-12-29 1992-04-14 Westinghouse Electric Corp. Adaptive or fault tolerant full wafer nonvolatile memory
US5315708A (en) * 1990-02-28 1994-05-24 Micro Technology, Inc. Method and apparatus for transferring data through a staging memory
US5134619A (en) * 1990-04-06 1992-07-28 Sf2 Corporation Failure-tolerant mass storage system
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US5388243A (en) * 1990-03-09 1995-02-07 Mti Technology Corporation Multi-sort mass storage device announcing its active paths without deactivating its ports in a network architecture
US5325497A (en) * 1990-03-29 1994-06-28 Micro Technology, Inc. Method and apparatus for assigning signatures to identify members of a set of mass of storage devices
US5202856A (en) * 1990-04-05 1993-04-13 Micro Technology, Inc. Method and apparatus for simultaneous, interleaved access of multiple memories by multiple ports
US5233692A (en) * 1990-04-06 1993-08-03 Micro Technology, Inc. Enhanced interface permitting multiple-byte parallel transfers of control information and data on a small computer system interface (SCSI) communication bus and a mass storage system incorporating the enhanced interface
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US5956524A (en) * 1990-04-06 1999-09-21 Micro Technology Inc. System and method for dynamic alignment of associated portions of a code word from a plurality of asynchronous sources
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US5745672A (en) * 1995-11-29 1998-04-28 Texas Micro, Inc. Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer
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US5751939A (en) * 1995-11-29 1998-05-12 Texas Micro, Inc. Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory
US5737514A (en) * 1995-11-29 1998-04-07 Texas Micro, Inc. Remote checkpoint memory system and protocol for fault-tolerant computer system
US6105156A (en) * 1996-01-23 2000-08-15 Nec Corporation LSI tester for use in LSI fault analysis
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TW405092B (en) * 1998-12-10 2000-09-11 Mitac Int Corp Automatic switching control device for DRAM
US7111190B2 (en) 2001-02-23 2006-09-19 Intel Corporation Method and apparatus for reconfigurable memory
US6567290B2 (en) * 2000-07-05 2003-05-20 Mosaic Systems, Inc. High-speed low-power semiconductor memory architecture
US20030226090A1 (en) * 2002-05-28 2003-12-04 Thayer Larry Jay System and method for preventing memory access errors
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US8195981B2 (en) * 2008-06-03 2012-06-05 International Business Machines Corporation Memory metadata used to handle memory errors without process termination

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US3444526A (en) * 1966-06-08 1969-05-13 Ibm Storage system using a storage device having defective storage locations
US3432812A (en) * 1966-07-15 1969-03-11 Ibm Memory system
NL149927B (nl) * 1968-02-19 1976-06-15 Philips Nv Woordgeorganiseerd geheugen.
JPS5230100B2 (it) * 1972-04-03 1977-08-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6425046B1 (en) 1991-11-05 2002-07-23 Monolithic System Technology, Inc. Method for using a latched sense amplifier in a memory module as a high-speed cache memory
US6483755B2 (en) 1991-11-05 2002-11-19 Monolithic System Technology, Inc. Memory modules with high speed latched sense amplifiers
US6717864B2 (en) 1991-11-05 2004-04-06 Monlithic System Technology, Inc. Latched sense amplifiers as high speed memory in a memory system

Also Published As

Publication number Publication date
IT1000794B (it) 1976-04-10
NL7316782A (it) 1974-07-05
JPS49103539A (it) 1974-10-01
DE2400161A1 (de) 1974-07-18
JPS594798B2 (ja) 1984-01-31
AU6358773A (en) 1975-06-19
AU476537B2 (en) 1976-09-23
US3803560A (en) 1974-04-09
FR2226081A5 (it) 1974-11-08
DE2400161C2 (it) 1988-03-10
GB1451386A (en) 1976-09-29
NL186783C (nl) 1991-02-18
NL186783B (nl) 1990-09-17

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