BRPI1105202A2 - Method of Manufacturing a Semiconductor Array Package and Semiconductor Device Package - Google Patents

Abstract

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE AND A SEMICONDUCTOR DEVICE PACKAGE. It is a method of manufacturing a semiconductor device package. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having an outer dielectric film surface and a first outer metal layer surface; forming a plurality of pathways extending through the laminate according to a predetermined pattern; connecting one or more semiconductor devices contact one or more pathways after wiring; arranging an electrically conductive layer on the first outer metal layer surface and on an inner surface of the plurality of pathways to form an interconnecting layer comprising the first metal layer and the electrically conductive layer; and standardizing the interconnect according to a predetermined circuit configuration to form a standard interconnect layer, wherein a portion of the standard interconnect layer extends through one or more pathways to form electrical contact with the semiconductor device. A semiconductor device package is also provided.

Description

"METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE AND SEMICONDUCTOR DEVICE PACKAGE" BACKGROUND OF THE INVENTION

The present invention generally relates to electronic packaging technology and, more particularly, to electronic packaging technology applicable to power semiconductor devices.

Advanced semiconductor device technologies such as Integrated Gate Bipolar Transistor (IGBT) 1 MOS Controlled Metal Oxide Field Effect Transistor (MOSFET), MOS Thyristor (MCT) offer improved thermal and electrical performance for a wide range of applications in the wide range of energy levels. However, to fully utilize the capabilities of such devices there is a need to provide improved packaging designs.

Typical semiconductor module designs employ wire connections to connect semiconductor devices to power buses and control terminals. Semiconductor devices are commonly soldered to a metalized insulating ceramic substrate and subsequently attached to a heat disperser. Typically, an injection molded polymer housing covers the module, which exposes only the input / output and control terminals and the heat exchanger. The heat spreader is attached to a heat sink and the thermal contact between the heat spreader and the heat sink is achieved through the thermal paste or thermally conductive polymer. Disadvantages of wire-based semiconductor module designs include relatively high parasitic impedance, high volume and weight, high heat resistance, and limited reliability primarily due to wire connections.

Power Overlay (POL) technology eliminates the use of wire bonding and offers significant advantages over power module-based wire bonding, for example, higher packaging density, lower pack parasites, high reliability. , underweight, smaller size, and higher effectiveness. A typical energy overlay fabrication process involves the use of a dielectric film stretched over a frame. An adhesive layer is applied to the dielectric film, where pathways are formed by laser ablation, followed by attachment of the semiconductor devices to the dielectric film. This is followed by metallization and circuit formation on the film by electroplating a thick copper layer on the dielectric film and into the pathways. The resulting package is then fixed to a substrate. In some cases, "feedthrough" or "shim" structures that are used to electrically connect the metallized layer to the substrate may be attached separately to the dielectric film. Therefore, in POL technology, the power and control circuits for the devices are reached through the metallised pathways, thus obviating the need for connecting wires.

However, the current POL manufacturing process can still present economic and technical challenges because of the number of steps and the time involved for each step. For example, the metallization step typically involves electroplating for hours to achieve the desired copper thickness for current handling, which significantly increases the cost of the POL process. In addition, the use of a frame reduces the area available for packaging and also adds processing steps to the POL manufacturing process. The use of separate copper shims may further increase the cost of the manufacturing step and may pose technical challenges such as lower adhesion.

Thus, there is a need to simplify POL manufacturing processes in order to provide low cost semiconductor device packaging manufacturing processes that overcomes one or more disadvantages associated with current POL processes.

Brief Description Of The Invention Embodiments of the present invention are provided to meet these and other needs. One embodiment is a method of manufacturing a semiconductor device package. The method includes providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having an outer dielectric film surface and a first outer metal layer surface; forming a plurality of pathways extending through the laminate according to a predetermined pattern; securing one or more semiconductor devices to the outer surface of dielectric film such that the semiconductor device contacts one or more pathways after fixation; arranging an electrically conductive layer on the first outer surface of the metal layer and on the inner surface of the plurality of pathways to form an interconnecting layer comprising the first metal layer and the electrically conductive layer; and standardizing the interconnect layer according to the predetermined circuit configuration to form the standard interconnect layer, with a portion of the standard interconnect layer extending through one or more pathways to form electrical contact with the semiconductor device. .

Another embodiment is a method of manufacturing a semiconductor device package. The method includes providing a laminate comprising a dielectric film disposed between a first metal layer and the second metal layer, said laminate having a first metal layer outer surface and a second metal layer outer surface; patterning the second metal layer to a predetermined pattern to form the second patterned metal layer; forming a plurality of pathways extending through the laminate according to a predetermined pattern; attaching one or more semiconductor devices to the outer surface of the second metal layer of a portion of the second standardized metal layer;

arranging an electrically conductive layer on the first outer surface of the metal layer and on an inner surface of one or more pathways to form an interconnecting layer comprising the first metal layer and the electrically conductive layer; and standardizing the interconnect layer according to a predetermined circuit configuration to form a standard interconnect layer, with a portion of the standard interconnect layer extending through one or more pathways to form electrical contact with the semiconductor device. .

Yet another embodiment is a semiconductor device package. The semiconductor device package includes a laminate comprising a first metal layer disposed on a dielectric film; a plurality of pathways extending through the laminate according to a predetermined pattern; one or more semiconductor devices attached to the dielectric film such that the semiconductor device contacts one or more pathways; a standard interconnect layer disposed on the dielectric film, said standard interconnect layer comprising one or more standard regions of the first metal layer and an electrically conductive layer, with a portion of the standard interconnect layer extending through one or more more ways to form an electrical contact with the semiconductor device. The standard interconnect layer comprises the top interconnect region and the road interconnect region, with the packet interconnect region having a thickness greater than the thickness of the road interconnect region. Drawings These and other attributes, aspects, and advantages of the present invention will be better understood when the following detailed description is read with reference to the accompanying drawings, where:

Figure 1 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 2 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 3 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 4 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 5 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 6 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 7 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 8 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 9 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 10 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 11 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Figure 12 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention. Figure 13 is a sectional side view of a step of the manufacturing process according to an embodiment of the invention.

Detailed Description As discussed in detail below, some of the embodiments of the invention provide a method for fabricating a semiconductor device package using a pre-metallized dielectric film.

Approaching language as used herein throughout the specification and claims may apply to modify any quantitative representation that could permissively vary without resulting in a change in the basic function to which it refers. Therefore, a value modified by a term or terms, such as "about", is not limited to the specified precise value. In some cases, the approximation of language may correspond to the accuracy of an instrument to measure the value.

In the following specification and claims, the forms

singular "one", "one" and "the" include plurals unless the context clearly indicates otherwise.

As used herein, the terms "may" and "may be" indicate a possibility of an occurrence within a set of circumstances; possession of a specific property, characteristic or function; and / or qualify another verb by expressing one or more of a skill, ability, or possibility associated with the qualified verb. Therefore, the use of "may" and "may be" indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or use, while taking into account that in some Under these circumstances the modified term may sometimes not be appropriate, capable, or appropriate. For example, in some circumstances an event or ability may be expected, while in other circumstances the event or ability cannot occur - this distinction is covered by the terms "may" and "may" be.

An exemplary semiconductor device package is described in terms of the following process steps, with reference to the drawings figures. Any dimensional and component values given herein are exemplary for illustration purposes only and are not intended to limit the scope of the invention described herein. Figures 1 to 13 are sectional side views of the manufacturing process steps according to some embodiments of the invention. As used herein, the terms "disposed in" or "fixed to" refer to layers or devices arranged or fixed directly in contact with each other or indirectly by having intermediate layers therebetween.

As illustrated in Figure 1, the method includes providing a laminate 100 comprising a dielectric film 120 disposed on a first metal layer 130. As shown in Figure 1, laminate 100 further includes an outer dielectric film surface 122 and a first metal layer outer surface 132. Dielectric film 120 further includes an inner surface 121 and the first metal layer includes an inner surface 131, so that the first inner surface metal layer 131 is disposed adjacent the inner layer surface While laminate 100 is illustrated as having a rectangular shape, laminate 100 may have any desired shape or size that is suitable for forming the structures of the present application.

In one embodiment, dielectric film 120 includes an organic dielectric material chosen to have particular thermal, structural and electrical properties suitable for use in semiconductor packaging structures. In some embodiments, dielectric film 120 has the lower modulus (high compliance), thermal expansion coefficient (CTE) of lower x, y and eixos geometry axes, and a high glass transition temperature (Tg) or melting temperature (Tm) 1. thereby improving the thermal and structural reliability of the resulting semiconductor device package. In one embodiment, dielectric film 120 includes a stable electrically insulating polymer for continuous use at temperatures above 150 ° C. Nonlimiting examples of suitable materials include polyimides, such as KAPTON (a trademark of El DuPont de Nemours and Co. ); polyethermides such as ULTEM (a trademark of General Electric Company); polyquinolines; polyquinoxalines; polyetherketones; and bismaleimide triazine resins. In a particular embodiment, the dielectric film 120 includes a polyimide, such as KAPTON.

In one embodiment, the first metal layer 130 includes copper and laminate 100 is provided by disposing a first metal layer 130 on top of the dielectric layer 120. In some embodiments, the first metal layer 130 may be directly attached to the dielectric film. 120, that is, no adhesive layer may be present between the dielectric film 120 and the first metal layer 130. In some other embodiments, an adhesive layer (not shown) is placed between the dielectric film 120 and the first metal layer. 130. In some embodiments, the first metal layer may be laminated onto the dielectric film using a roll making method.

In one embodiment, the dielectric film 120 has a thickness in a range of from about 1 micron to about 1,000 microns. In another embodiment, dielectric film 120 has a thickness in a range of from about 5 microns to about 200 microns. In one embodiment, the first metal layer has a thickness in a range of from about 10 microns to about 200 microns. In another embodiment, the first metal layer has a thickness in a range of from about 25 microns to about 150 microns. In a particular embodiment, the first metal layer has a thickness in a range of from about 50 microns to about 125 microns. As described in detail below, by providing a laminate 100 comprising a first metal layer 130 having a desired thickness, the time taken for subsequent deposition of the electrically conductive layer and metallization of the pathways can therefore be reduced.

As noted earlier, laminate 100 does not include the frame and therefore the method does not involve the dielectric film frame step 120. In some embodiments, the first metal layer 130 provides the structural support for the dielectric film 120 and stability. to the semiconductor device package manufactured from it. In addition, the first metal layer 130 may provide for ease of handling and ease of transport in the absence of a transport frame that is typically used for the energy overlay fabrication process. A frameless dielectric film advantageously provides improved usable area for securing semiconductor devices and, therefore, a large number of semiconductor devices can be fixed using the methods of the present invention.

As illustrated in Figure 2, the method further includes forming a plurality of pathways 150 extending through the laminate 100 according to a predetermined pattern. Multiple pathways, such as representative pathways 150, may be formed through laminate 100 by a standard mechanical punching process, water-adjusted punching process, chemical etching, plasma etching, reactive ion etching, or laser processing, for example. In one embodiment, the pathways 150 are formed through the laser ablation laminate. The track pattern is determined by one or more of the number of devices to be attached, the number of device contact pads, the size of device contact pads, and the desired circuit configuration. As shown in Figure 2, the plurality of tracks 150 further includes an inside track surface 152.

In one embodiment, the tracks 150 have a circular shape with vertical sidewalls as shown in Figure 2. The shape of the tracks 150 is not limited, however, and the tracks may include any suitable shape. For example, the lanes 150 may have an oval shape or a square shape with rounded corners, or another more complex shape. In another embodiment, the lanes 150 have tapered sidewalls. The size and number of the pathways may depend in part on the size of the contact pads 210 and 220 and the electrical current requirements of the device 200. For example, as shown in Figure 4, the conductive layer 180 contacts the contact pad 210. via two-way and contact pad 220 via one-way to meet the desired electrical current requirements for device 200 in one exemplary embodiment. In another embodiment, three or more pathways 150 may contact the contact pad 210. In an alternative embodiment, fewer pathways having larger openings may be employed to meet the same desired current requirements. For example, a single major pathway could replace the plurality of pathways in contact with the contact pad 210 in the embodiment of Figure 4. In one embodiment, the plurality of pathways 150 have a diameter in a range of from about 25 microns to about 10,000 microns. In another embodiment, the plurality of lanes 150 have a diameter in a range greater than about 10,000 microns. In yet another embodiment, the plurality of pathways 150 have a diameter in a range of from about 2,000 microns to about 40,000 microns. In one embodiment, the first metal layer 130 may enhance the dimensional stability of laminate 100, which allows for fairer track spacing 150. Increased track density 150 may advantageously reduce resistive losses and crowding of current. Multiple connections formed through the pathways to a single contact pad provide an electrical connection, which may be greater than a single wire connection.

The method further includes positioning an adhesive layer 160 between the dielectric layer 120 and the device 200. In one embodiment, the method includes arranging an adhesive layer 160 on the dielectric outer surface 122 as shown in Figure 3. The adhesive layer 160 may be applied before or after the formation of the route. In some embodiments, the protective release layer (not shown) may be applied over the adhesive layer 160 to keep the adhesive layer 160 clean during the pathway process. The adhesion layer 160 may be applied to the dielectric outer surface 122 by any suitable method. For example, the adhesion layer 160 may be applied by spin coating, meniscus coating, spray coating, vacuum deposition, or lamination techniques. In the embodiment illustrated in Figure 3, the adhesion layer 160 is applied to the outer surface of dielectric film 122 after the pathways 150 are formed. In an alternative embodiment, the adhesion layer 160 is applied to the outer surface of dielectric film 122 before the pathways 150 are formed. The lanes 150 are then formed through dielectric film 120 and adhesion layer 160 using any suitable technique such as mechanical drilling, laser processing, plasma etching, reactive ion etching, or chemical etching techniques mentioned above. .

In another embodiment, the method includes arranging an adhesive layer 160 over the active layer 202 of the device 200. The adhesive layer 160 may be applied before or after the formation of the pathway. In some embodiments, the protective release layer (not shown) may be applied over the adhesive layer 160 to keep the adhesive layer 160 clean during the pathway process. The adhesion layer 160 may be applied to the active layer 202 by any suitable method. For example, the adhesion layer 160 may be applied by spin coating, meniscus coating, spray coating, vacuum deposition, or lamination techniques.

Adhesive layer 160 may include one or more of a thermostable polymer or thermoplastic polymer. Suitable non-limiting examples for adhesive layer 160 include acrylic, an epoxy, and a polyethermide. In one embodiment, the low temperature cure thermostable can be used as an adhesive to minimize high temperature processing. In one embodiment, the adhesive layer has a thickness in a range of from about 1 micron to about 100 microns. In one embodiment, a suitable material for the adhesive layer 160 includes a polyetherimide having a thickness in a range of from about 10 microns to about 25 microns.

As shown in Figure 3, the method further includes securing one or more semiconductor devices 200 to the dielectric film outer surface 122, so that the semiconductor device contacts one or more lanes 150 upon attachment. In a particular embodiment, semiconductor device 200 is representative of a power device. In one embodiment, semiconductor device 200 is representative of power semiconductor devices of various types, such as, but not limited to power MOSFETs (semiconductor oxide metal field effect transistors) and IGBTs (isolated gate bipolar transistor), which are employed in power switching applications. In another embodiment, semiconductor device 200 is a diode. A single semiconductor device 200 is provided by way of example only. However, in the current energy overlay fabrication process a plurality of semiconductor devices may be attached to the outer surface of dielectric film 122. In an exemplary embodiment, prior to any packaging or interconnection, such devices 200 are generally in the form of a chip. semiconductor having an active layer 202 and an opposite surface 204. The active layer 202 is standardized and has metallized I / O pads 210 and 220 including, in the case of a semiconductor power device 220, at least two terminals namely, a device main terminal as a source terminal represented by the contact pad 210, and a control terminal as a gate terminal, represented by the contact pad 220. In some embodiments, in order to provide low impedance connections , there is also the big main terminal 210 over the active layer 202, or there are multiple main terminals 210 (not shown), all to be connected in parallel, and additionally one or more control terminals 220 (not shown), also to be connected in parallel. The opposite uniform surface 204 includes another device main terminal 230, such as the drain terminal.

In one embodiment, after the adhesion layer 160 is disposed on the dielectric outer surface 122 or the active layer 202 of the device 200, the active layer 202 of the device 200 is contacted with the adhesion layer 160 so that a plurality of 150 is arranged. aligned with the contact pads 210 and 220 as shown in Figure 3. In an exemplary embodiment, the device 200 is positioned on the adhesion layer 160 using the pick-up machine. The device 200 is then bonded to the dielectric film 120. In one embodiment, the adhesion layer 160 is a thermoplastic, and bonding is performed by increasing the temperature until sufficient flux has occurred in the thermoplastic to allow bonding to occur. In another embodiment, the adhesion layer 160 is a thermostable and bonding is performed by increasing the temperature of the adhesion layer until crosslinking has occurred. In one embodiment, device 200 is bonded to dielectric film 160 using a thermal cure cycle and, if necessary, a vacuum to facilitate trapped air removal and degassing of adhesive 160. Alternative cure options include a cure microwaves and a cure for ultraviolet light, for example.

In one embodiment, the method further includes arranging a layer

electrically conductive layer 180 on the first outer surface of the metal layer 132 as shown in figure 4. The method further includes arranging the electrically conductive layer 180 on an inner surface 152 of a plurality of pathways 150. As illustrated in figure 4, electrically conductive layer 180 and first metal layer 130 of interconnect layer 190 on the outer surface of dielectric film 122. Interconnect layer 190 still extends through the pathways and comprises electrically conductive layer 180 on pathways 150 as shown in figure 4.

The electrically conductive layer 180 may include any

conductive material suitable for use in semiconductor device interconnections. In one embodiment, the electrically conductive layer 180 includes refractory metals, noble metals, or combinations thereof. Non-limiting examples of suitable metals and alloys include tungsten, molybdenum, titanium / tungsten, gold, platinum, palladium, gold / indium, and gold / germanium. In another embodiment, copper, aluminum, or copper or aluminum alloys may be employed as the electrically conductive layer 180. The material employed for the electrically conductive layer 180 may be chosen to withstand temperatures at which semiconductor device 200 is expected to operate. . In one embodiment, the electrically conductive layer 180 includes the same material as the first metal layer 130. In a particular embodiment, the electrically conductive layer 180 includes copper. In one embodiment, the electrically conductive layer 180 may be disposed on the first outer surface of the metal layer 122 and an inner surface of the pathways 152 by crackling, chemical vapor deposition, electroplating, electrolytic galvanizing, or any other suitable methods. In a particular embodiment, the electrically conductive layer 180 is electroplated. In some embodiments, the method may further include disposing one or more additional layers prior to arranging the electrically conductive layer, such as a seed layer (not shown). In one embodiment, the seed layer includes barrier metal such as Ti, Cr or Ni, or in alternative embodiments, the seed layer includes a non-barrier metal such as Cu. Typically, it is desirable for a seed layer to achieve good adhesion between the electrically conductive layer 180 and the dielectric film 120. In some embodiments, the methods of the present invention obviate the need for deposition of a separate seed layer, such as the first layer. Metal 130 provides the surface characteristics required for deposition of the electrically conductive layer 180 and also provides improved adhesion between the electrically conductive layer 180 and the dielectric film 120.

The thickness of the electrically conductive layer 180 can

depend in part on the amount of current that will pass through the interconnect layer, the width of the patterned regions in the patterned interconnect layer 192, and the thickness of the first metal layer 130 already present in the dielectric film. In one embodiment, the electrically conductive layer 180 has a thickness in a range of from about 10 microns to about 100 microns. In one particular embodiment, the electrically conductive layer has a thickness in a range of from about 25 microns to about 50 microns. As noted earlier, the lower thickness of the electrically conductive layer 180 means less time required for deposition, for example, electroplating of the electrically conductive layer 180 and thus reduced cost. In one embodiment, the electrically conductive layer 180 is deposited to a thickness such that the thickness of the resulting interconnect layer 190 is capable of carrying the relatively high currents typical for relatively low resistive loss semiconductor device operation. As noted above, the methods of the present invention advantageously allow the formation of a thick interconnect layer in the dielectric film and at the same time reduce manufacturing time and associated cost. For example, a typical electroplating process for depositing a 125 micron thick interconnect layer may require 5 to 6 hours of electroplating time. In an exemplary embodiment of the present invention, a 25 micron thick electrically conductive layer may be deposited on a first metal layer having a thickness of 100 microns, which may advantageously reduce the fabrication time by one fifth.

The method further includes standardizing interconnect layer 190 according to a predetermined circuit configuration to form a standardized interconnect layer 192, wherein a portion of the standardized interconnect layer 192 extends through one or more pathways 150 to form an interconnect. electrical contact with semiconductor device 200 as illustrated in FIGURE 5. FIGURE 5 illustrates a cross-sectional view of device 200 attached to dielectric film 120 after interconnect layer 190 is patterned. Interconnect layer 190 is patterned by selectively removing the portions of interconnect layer 190 to form the standard interconnect layer 192 composed of packaging structure interconnects. As shown in FIGURE 5, the standard interconnect layer 192 includes a top interconnect region 194 and a track interconnect region 194. Top interconnect region 194 includes standard portions of the first electrically conductive layer 180 and the first interconnect layer. 130 and is formed adjacent the outer surface of dielectric film 122. The standard interconnect layer 192 additionally includes a track interconnect region 196 formed on the plurality of track 150. A first portion of the track interconnect region 196 is disposed adjacent the track side walls 150 and a second portion is arranged adjacent one or more contact pads 210/220 of semiconductor device 200. Track interconnect region 196 comprises electrically conductive layer 180.

As illustrated in FIGURE 5, the top interconnect region 194 has a thickness greater than a thickness of the track interconnect region 196. In one embodiment, the track interconnect region 196 has a thickness in the range of about 10 microns. at about 75 microns. In one embodiment, the track interconnect region 196 has a thickness in a range of from about 25 microns to about 50 microns. In one embodiment, the top interconnect region 194 has a thickness in a range of from about 50 microns to about 200 microns. In another embodiment, the top interconnect region 194 has a thickness in a range of from about 75 microns to about 150 microns.

Top interconnect region 194 and track interconnect region 196 can provide low resistance and low induction interconnects. In one embodiment, the interconnect region comprising top interconnect region 192 and track interconnect region 194 in electrical contact with contact pad 210 may serve as a packet main terminal contact and may have current carrying capacity. Similarly, the interconnect region comprising the top interconnect region 192 and the track interconnect region 194 in electrical contact with the contact pad 220 may serve as the packet gate terminal contact.

In one embodiment, interconnect layer 190 is standardized by the subtractive etching method, semi-additive processing technique or lithography, such as, for example, adaptive lithography. For example, In one embodiment a photomask material may be applied to the surface of interconnect layer 190, followed by photo developing the photomask material in the desired interconnect pattern and then engraving the exposed portions of the layer. 190 with use of a standard wet etching bath. In an alternative embodiment, a metal seed layer may be formed on the metal layer 130. A photo mask material is applied to the surface of the thin metal seed layer, followed by photo development of the photo mask material. so that the thin metal seed layer is exposed where the desired interconnect pattern should be formed. An electroplating process is then employed to selectively deposit additional metal into the exposed seed layer to form a thicker layer, followed by removal of the remaining photo masking material and etching of the exposed thin metal seed layer. In one embodiment, a semiconductor device package 300 is

The semiconductor device package 300 includes a laminate 100 comprising a first metal layer 130 disposed on a dielectric film 120. The semiconductor device package 300 includes a plurality of pathways 150 extending through the laminate 100 according to a predetermined standard. One or more semiconductor devices 200 are connected to dielectric film 120 such that semiconductor device 200 contacts one or more pathways 150. A standard interconnect layer 192 is disposed on dielectric film 120, said interconnect layer being said. Pattern 192 comprises one or more pattern regions of the first metal layer 130 and an electrically conductive layer 180, wherein a portion of the pattern interconnect layer 192 extends through one or more pathways 150 to form an electrical contact with the semiconductor device. 200. The standard interconnect layer 192 additionally includes a top interconnect region 194 and a track interconnect region 196, wherein packet interconnect region 194 has a thickness greater than a thickness of the track interconnect region 196. In the embodiments described above in the present invention, the

Laminate includes a layer of metal arranged only on one side of the dielectric film. In another embodiment, the method includes providing a laminate 100 comprising a dielectric film 110 interposed between a first metal layer 130 and a second metal layer 110, as shown in FIGURE 6. The laminate 100 further includes a first outer layer surface. 132 and a second metal layer outer surface 112. The first metal layer further includes a first metal layer inner surface 131 disposed adjacent the inner surface of the dielectric film 121. The second metal layer 110 additionally includes a surface second layer metal inner layer 111 disposed adjacent the dielectric film outer surface 122. In one embodiment, the second metal layer 110 includes copper.

As noted earlier, the laminate does not include a frame and therefore the method does not involve the step of placing the frame on the dielectric film. In some embodiments, the first metal layer 130 and the second metal layer 110 together provide structural support for dielectric film 120 and dimensional stability for the semiconductor device package manufactured therefrom. In addition, the first metal layer 130 and the second metal layer 110 may provide ease of handling and ease of transport in the absence of a carrier frame that is typically used for energy overlay fabrication process.

In one embodiment, the method further includes standardizing the

second metal layer 110 according to a predetermined pattern to form a second standardized metal layer 140 as shown in FIGURE 7. In some embodiments, the second metal layer 110 is patterned by the subtractive etching or lithography method such as, for example. , adaptive lithography. In one embodiment, the second metal layer 110 is patterned to form a plurality of patterned second metal layer regions, such as, for example, the patterned second metal layer regions 141, 143, and 145 in dielectric film 120. In one embodiment, the second metal layer 110 is patterned to form one or more feedthrough structures 145. In some embodiments, one or more feedthrough structures 145 may permit electrical contact with the drain terminal contact 230 arranged on the opposite surface 204 of device 200, thereby bringing all electrical connections to the top of the semiconductor device package. In a typical power overlay fabrication process, the feedthrough structures are manufactured separately and subsequently bonded to dielectric 120, which can increase the number of fabrication steps and also the associated cost. In addition, separately bonded feedthrough structures may have lower adhesion and increased possibility of defects at the interface between the feedthrough structure and the dielectric film. In some embodiments, the methods of the present invention advantageously provide an integrated process for manufacturing feedthrough structures using the second metal layer 110, which may result in a reduction in the number of fabrication steps and may be economically advantageous.

The size and thickness of the patterned regions 141, 143, and 145 may depend in part on the thickness of the device, the thickness of the desired feedthrough structure and the track pattern. In one embodiment, the second metal layer 110 is further patterned to form one or more patterned regions 141 and 143 having a thickness determined by the thickness of the device to be attached to the dielectric film 120. In such instances, the thickness of the second region The patterned metal layer 141 and 143, for example, may be selectively adjusted such that the attached device 200 is substantially flat with the feedthrough structure 145 which may facilitate subsequent bonding of a flat substrate.

The method further includes forming a plurality of pathways 150 extending through the laminate according to a predetermined pattern. As shown in FIGURE 8, the plurality of lanes 150 thus formed extends through the first metal layer 130, dielectric film 120, and a portion of the second standardized metal layer 140. As illustrated in FIGURE 8, the plurality of lanes 151, 153, and 155 extends through the second metal layer patterned regions 141 and 143, and not through the feedthrough structure 145. The plurality of pathways 150 may be formed by any suitable methods as described above. In some embodiments, the plurality of pathways may be selectively formed through the laminate such that only a portion of the second patterned metal layer 140 is removed to form the pathways. For example, as shown in FIGURE 8, illustrative path 155 is formed through laminate 100 such that path 155 is aligned with one or more feed-through frame 145 and does not extend through feed-through frame 145. In some embodiments, the plurality of pathways are formed after patterning of the second metal layer 110. In an alternative embodiment, the plurality of pathways is formed before patterning of the second metal layer 110.

In some other embodiments, the second metal layer 110 is selectively patterned prior to the formation of the pathways 150 to selectively remove portions of the standardized second metal layer regions, for example, the patterned regions 141 and 143, based on the predetermined pattern of the layers. lanes 151 and 153, for example. As illustrated in FIGURE 9, the second metal layer 110 is patterned to form the second patterned metal layer 140, wherein the patterned metal layer 140 additionally includes patterned regions 141 and 143, such that a portion of the patterned regions is. removed based on the road pattern. In some embodiments, the first metal layer 130 is further selectively patterned prior to forming the pathways 150 to selectively remove portions of the first metal layer 130 based on the predetermined pattern of the pathways 151 and 153, for example as shown in FIGURE 9. In such embodiments, forming the pathways 150 only includes removing selected portions of the dielectric film 120 to form the pathways 150 extending through the laminate as shown in FIGURE 8.

In one embodiment, one or more of the standard second metal layer regions 145 do not contact a path 150 and interconnect layer 192. In such embodiments, the path 155, for example, may not being present and the patterned second layer metal region 145 may provide mechanical support for the dielectric film and may function as a frame in the absence of the carrier frame.

The method further includes connecting one or more semiconductor devices 200 to the second metal layer outer surface 142 of a portion of the second standardized metal layer 140. As shown in FIGURE 10, device 200 is connected to the second metal layer outer surface 142 of the standardized second metal layer regions 141 and 143. In some embodiments, the method may further include interposing an adhesive layer 160 between the device 200 and the second outer metal layer surface 142 prior to attachment of the device. The adhesive layer 160 may be arranged by a method as described above. In one embodiment, after arranging the adhesion layer 160, the largest active surface 202 of the device 200 is brought into contact with the adhesion layer 160 so that the lanes 151 and 153 are aligned with the contact pads 210 and 220, As noted above, the patterned second metal layer regions 141 and 143 permit alignment of the device such that the opposite surface 204 of the device 200 is aligned with the outer surface of the feedthrough 145. to form a substantially flat surface.

In one embodiment, the method further includes arranging an electrically conductive layer 180 on the first outer surface of metal layer 132 as shown in FIGURE 11. The method further includes arranging the electrically conductive layer 180 on an inner surface 152 of the plurality of pathways 150. As illustrated in FIGURE 11, electrically conductive layer 180 and first metal layer 130 form interconnect layer 190 in dielectric film 120. Interconnect layer 190 extends further through the pathways as shown in FIGURE 11, wherein the interconnect layer 190 comprises the electrically conductive layer 180 in pathways 150.

The method further includes standardizing interconnect layer 190 according to a predetermined circuit configuration to form a standardized interconnect layer 192, wherein a portion of the standardized interconnect layer 192 extends through one or more pathways 150 to form an interconnect. electrical contact with semiconductor device 200 as illustrated in FIGURE 12. FIGURE 12 illustrates a cross-sectional view of device 200 attached to dielectric film 120 after interconnect layer 190 is patterned. Interconnect layer 190 is patterned by selectively removing the portions of interconnect layer 190 to form the standard interconnect layer 192 composed of the packaging structure interconnects. As shown in FIGURE 12, the standard interconnect layer 192 includes a top interconnect region 194 and a track interconnect region 196. Top interconnect region 194 includes the standard portions of the first electrically conductive layer 180 and the first layer of metal 130 and is formed adjacent to the dielectric film. The standard interconnect layer 192 further includes a track interconnect region 196 formed in the plurality of track 150. A first part of the track interconnect region 196 is disposed adjacent the side walls of the track 150 and a second part is disposed adjacent a or more contact pads 210/220 of the semiconductor device 200. The track interconnect region 196 comprises the electrically conductive layer 180. In addition, in one embodiment, a portion of the patterned interconnect layer 192 extends across one or more pathways. 150 to form an electrical contact with one or more feedthrough structures 145 as illustrated in FIGURE 12.

In one embodiment, the method further includes patterning the second metal layer 110 prior to bonding one or more devices to form a plurality of patterned regions, wherein at least two patterned regions have a different thickness from one another. In such embodiments, the patterned regions of different thickness may advantageously accommodate semiconductor devices having different thicknesses, such that the opposite surfaces of the semiconductor devices are all aligned and provide a substantially flat surface of a substrate. In one embodiment, the method further includes attaching a plurality of semiconductor devices to the second standardized metal layer, wherein at least two semiconductor devices have a different thickness from one another. As shown in FIGURE 13, semiconductor devices 200 and 400 having different thicknesses are advantageously bonded to the dielectric film such that opposite surfaces of semiconductor devices are aligned with each other and with the outer surface of the feedthrough structure. In FIGURE 13, only one contact pad is shown aligned with pathways 150, however, semiconductor devices 200 and 400 may include a plurality of contact pads aligned with pathways 150 as described above.

In one embodiment, a semiconductor device package 300 is provided as shown in FIGURE 12. Semiconductor device package 300 includes a laminate 100 comprising a first metal layer 130 disposed on a dielectric film 120. Semiconductor device package 300 further includes a second patterned metal layer 140 disposed on the dielectric film 120 and, a side opposite to the first metal layer 130. The second patterned metal layer 140 includes the regions of the second patterned metal layer, such as, for example, 141 and 143 and one or more feed-through structures 145. Semiconductor device package 300 includes a plurality of pathways 150 extending through laminate 100 according to a predetermined pattern. One or more semiconductor devices 200 are connected to the second outer metal layer surface 142 of a portion of the second standardized metal layer 140 such that the semiconductor device 200 contacts one or more pathways 150. An interconnect layer 192 is arranged in the dielectric film 120, said patterned interconnect layer 192 comprising first metal layer 130 and an electrically conductive layer 180, wherein a portion of the patterned interconnect layer 192 extends through one or more pathways. 150 to form an electrical contact with the semiconductor device 200. The standard interconnect layer 192 includes a top interconnect region 194 and a track interconnect region 196, wherein packet interconnect region 194 is thicker than one. thickness of the road interconnect region 196. In addition, a portion of the standard interconnect layer 192 extends across an u more ways 150 to form an electrical contact with one or more feedthrough structures 145.

In one embodiment, semiconductor device package 300 may be additionally attached to a semiconductor device substrate (not shown). The semiconductor device substrate may include an isolation substrate having one or more electrically conductive substrate contacts to which the semiconductor device 200 may be electrically coupled. For example, semiconductor device 200 may be soldered to substrate contact. The semiconductor device substrate may also include a backing conductive layer, which may facilitate connection of the semiconductor device 200 to a heat sink, for example.

In some embodiments, the resulting semiconductor device package 300 provides high current carrier capability and a low impedance thermal path for conducting heat away from the active surface 202 of the semiconductor device. In some embodiments, the heatsink structures, electrical interconnect structures, or both may be mounted on the top or bottom of the package or both.

The appended claims are intended to claim the invention as broadly as conceived and the examples in the present invention are illustrative of selected embodiments of a multiplicity of all possible embodiments. Accordingly, it is the intention of the applicants that the appended claims are not limited by the choice of examples used to illustrate the features of the present invention. As used in the claims, the word "comprises" and its grammatical variants logically also include and include sentences of different lengths and variants such as, for example, but not limited to these, "consisting essentially of" and "consisting of". When necessary, tracks were provided; These tracks are inclusive of all sub-tracks in between. It should be expected that variations in these ranges will be suggested to a person skilled in the art and when not yet dedicated to the public, such variations should, where possible, be construed to be encompassed by the appended claims. It is also anticipated that advances in science and technology will make equivalents and substitutions possible which are not contemplated because of language inaccuracy and these variations should also be interpreted, where possible, to be covered by the appended claims.

Claims (11)

A method of manufacturing a semiconductor device package, comprising: providing a laminate comprising a dielectric film disposed on a first metal layer, said laminate having an outer dielectric film surface and a first outer layer surface. of metal; forming a plurality of pathways extending through the laminate according to a predetermined pattern; connecting one or more semiconductor devices to the outer surface of dielectric film such that the semiconductor device contacts one or more pathways after bonding; arranging an electrically conductive layer on the first outer metal layer surface and on an inner surface of the plurality of pathways to form an interconnecting layer comprising the first metal layer and the electrically conductive layer; and standardizing the interconnect layer according to a predetermined circuit configuration to form a standard interconnect layer, wherein a portion of the standard interconnect layer extends through one or more pathways to form electrical contact with the semiconductor device. A method according to claim 1, wherein the standard interconnect layer comprises a top interconnect region and a track interconnect region, and wherein the top interconnect region has a thickness greater than one thickness. track interconnection region. A method according to claim 2, wherein the track interconnect region has a thickness in a range of from about 5 microns to about 125 microns. A method according to claim 2, wherein the top interconnecting region has a thickness in a range of from about microns to about 200 microns. A method according to claim 1, wherein the laminate is unstrapped. A method of manufacturing a semiconductor device package which comprises: providing a laminate comprising a dielectric film interposed between a first metal layer and a second metal layer, said laminate having a first outer layer of metal and a second outer surface of the metal layer; patterning the second metal layer to a predetermined pattern to form a second patterned metal layer; forming a plurality of pathways extending through the laminate according to a predetermined pattern; connecting one or more semiconductor devices to the second outer metal layer surface of a portion of the second standardized metal layer; arranging an electrically conductive layer on the first outer metal layer surface and on an inner surface of one or more pathways to form an interconnecting layer comprising the first metal layer and the electrically conductive layer; and standardizing the interconnect layer according to a predetermined circuit configuration to form a standard interconnect layer, wherein a portion of the standard interconnect layer extends through one or more pathways to form electrical contact with the semiconductor device. The method of claim 6, wherein the second patterned metal layer further comprises one or more feed-through structures aligned with one or more pathways, and a portion of the patterned interconnect layer extends through a or more pathways to form electrical contact with one or more feedthrough structures. A method according to claim 6, further comprising standardizing the first metal layer according to the predetermined track pattern before forming the plurality of tracks. A method according to claim 6, wherein the second patterned metal layer further comprises a plurality of patterned regions, wherein at least two patterned regions have a different thickness from one another. A method according to claim 6, further comprising connecting a plurality of semiconductor devices to the second standardized metal layer, wherein at least two semiconductor devices have a different thickness from one another. A semiconductor device package comprising: a laminate comprising a first layer of metal arranged in a dielectric film; a plurality of pathways extending through the laminate according to a predetermined pattern; one or more semiconductor devices bonded to the dielectric film such that the semiconductor device contacts one or more pathways; and a patterned interconnect layer disposed in the dielectric film, said patterned interconnect layer comprising one or more patterned regions of the first metal layer and an electrically conductive layer, wherein a portion of the patterned interconnect layer extends through one or more pathways to form an electrical contact with the semiconductor device, and the standard interconnect layer comprises a top interconnect region and a track interconnect region, wherein the top interconnect region has a thickness greater than one thickness. of the road interconnection region.