TWI648834B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor packaging structure includes a substrate, at least one electronic component, a packaging gel, and a redistribution circuit layer. The substrate includes a thermally conductive insulating layer, a patterned circuit layer, and a metal layer. The thermally conductive insulating layer has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the thermally conductive insulating layer and exposes a portion of the first surface of the thermally conductive insulating layer. The metal layer is disposed on the thermally conductive insulating layer and completely covers the second surface of the thermally conductive insulating layer. The electronic component is disposed on the substrate and is electrically connected to the patterned circuit layer. The encapsulating gel covers at least the electronic component. The redistribution circuit layer is disposed on the packaging gel and is electrically connected to the electronic component. The edge of the packaging gel is approximately aligned with the edge of the substrate.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a semiconductor package structure and a manufacturing method thereof, and in particular to a semiconductor package structure and a manufacturing method thereof having better heat dissipation effects.

In the conventional Quad Flat No-Lead (QFN) package structure, the chip is usually arranged on a leadframe. The lead frame has a chip holder and a plurality of pins, and the chip is electrically connected to the pins of the lead frame via bonding wires. These pins, bonding wires, and chips are encapsulated and protected by the packaging gel, and the bottom of these pins is exposed to the packaging material for electrically connecting to an external device such as a printed circuit board.

However, in the above-mentioned square flat leadless package structure, since the chip needs to be arranged on the lead frame, it is difficult to further reduce the overall thickness of the package structure. Furthermore, because the quad flat flat leadless package structure uses a lead frame as the main structure, solder is not required, so it is difficult to embed passive components such as resistors, capacitors, or inductors that need to be connected through the solder in the package structure. In addition, when the electronic components in the package structure operate, a large amount of thermal energy is generated. If the thermal energy cannot be dissipated and is continuously accumulated, the package structure may suffer from performance degradation or shortened service life due to overheating. In severe cases, it may even be permanent. Damage. Therefore, how to further reduce the overall thickness of the packaging structure, and integrate different types of electronic components into the packaging structure, and improve the heat dissipation efficiency of the packaging structure, has become an urgent issue.

The invention provides a semiconductor package structure and a manufacturing method thereof, which can reduce the overall thickness of the package structure and has better heat dissipation effect.

The invention provides a semiconductor packaging structure, which includes a substrate, at least one electronic component, a packaging gel, and a redistribution circuit layer. The substrate includes a thermally conductive insulating layer, a patterned circuit layer, and a metal layer. The thermally conductive insulating layer has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the thermally conductive insulating layer and exposes a portion of the first surface of the thermally conductive insulating layer. The metal layer is disposed on the thermally conductive insulating layer and completely covers the second surface of the thermally conductive insulating layer. The electronic component is disposed on the substrate and is electrically connected to the patterned circuit layer. The encapsulating gel covers at least the electronic component. The redistribution circuit layer is disposed on the packaging gel and is electrically connected to the electronic component. The edge of the packaging gel is approximately aligned with the edge of the substrate.

According to an embodiment of the present invention, the semiconductor package structure further includes at least one conductive via. The conductive vias penetrate the packaging gel, and the redistribution circuit layer is electrically connected to the patterned circuit layer of the substrate through the conductive vias.

In an embodiment of the present invention, the above-mentioned semiconductor package structure further includes an adhesive layer. The adhesive layer is disposed on the substrate, and the electronic component is fixed on the substrate by the adhesive layer.

In an embodiment of the present invention, the semiconductor package structure further includes a first solder resist layer and a second solder resist layer. The first solder mask layer is disposed on the metal layer of the base, wherein the first solder mask layer has at least one first opening, and the first opening exposes a part of the metal layer and defines at least one first pad. The second solder mask is disposed on the packaging gel and covers the redistribution circuit layer. The second solder mask has at least one second opening, and the second opening exposes part of the redistribution circuit layer, and defines at least one second pad. .

In an embodiment of the present invention, the semiconductor package structure further includes a third solder resist layer. The third solder resist is disposed on the thermally conductive insulating layer of the substrate, and the third solder resist is located between the packaging gel and the thermally conductive insulating layer. The third solder mask layer covers the patterned circuit layer, wherein the third solder mask layer has at least one third opening, and the third opening exposes a portion of the patterned circuit layer, and defines at least one third pad, and the electronic component is located at the first Three pads.

In an embodiment of the present invention, the semiconductor package structure further includes at least one heat dissipation element. The heat dissipation element is disposed on the first pad.

In an embodiment of the present invention, the at least one electronic component includes a plurality of electronic components. These electronic components are connected in series, parallel, electrically independent or a combination of the above.

In an embodiment of the present invention, the at least one electronic component includes an active component and a passive component.

In an embodiment of the present invention, the redistribution circuit layer includes a redistribution circuit and a plurality of conductive blind holes. The redistribution circuit is arranged on the packaging gel. The conductive blind hole is located in the packaging gel and connects the electronic component and the redistribution circuit.

In an embodiment of the present invention, the thermal conductivity of the thermally conductive insulating layer is between 1 W / (mK) and 100 W / (mK).

The method for manufacturing a semiconductor package structure of the present invention includes the following steps. A substrate is provided. The substrate includes a thermally conductive insulating layer, a patterned circuit layer, and a metal layer. The thermally conductive insulating layer has a first surface and a second surface opposite to each other. The patterned circuit layer is disposed on the thermally conductive insulating layer and exposes a portion of the first surface of the thermally conductive insulating layer. The metal layer is disposed on the thermally conductive insulating layer and completely covers the second surface of the thermally conductive insulating layer. At least one electronic component is disposed on the substrate, wherein the electronic component is electrically connected to the patterned circuit layer. An encapsulant is formed to at least cover the electronic components. A redistribution circuit layer is formed on the packaging gel, wherein the redistribution circuit layer is electrically connected to the electronic component, and the edge of the packaging gel is approximately aligned with the edge of the substrate.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure further includes forming at least a through-package gel after forming a package gel to cover at least the electronic components and before forming a redistribution circuit layer on the package gel. A conductive via, wherein the redistribution circuit layer is electrically connected to the patterned circuit layer of the substrate through the conductive via.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure further includes forming an adhesive layer on the substrate after providing the substrate and before disposing the electronic components on the substrate, so that the The electronic component is fixed on the substrate by an adhesive layer.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure further includes forming a first solder resist layer on the metal layer of the substrate, wherein the first solder resist layer has at least one first opening, and the first opening is exposed. Part of the metal layer is defined, and at least one first pad is defined; and a second solder mask layer is formed on the encapsulation gel and covers the redistribution circuit layer, wherein the second solder mask layer has at least a second opening and a second opening A portion of the redistribution circuit layer is exposed, and at least one second pad is defined.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure further includes forming a third solder mask layer on the thermally conductive insulating layer of the substrate and covering the patterned circuit layer, wherein the third solder mask layer has at least Three openings. The third opening exposes a portion of the patterned circuit layer, and defines at least one third pad, and the electronic component is located on the third pad.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure further includes disposing at least one heat dissipation element on the first pad.

In an embodiment of the present invention, the at least one electronic component includes a plurality of electronic components. These electronic components are connected in series, parallel, electrically independent or a combination of the above.

In an embodiment of the present invention, the at least one electronic component includes an active component and a passive component.

In an embodiment of the present invention, the redistribution circuit layer includes a redistribution circuit and a plurality of conductive blind holes. The redistribution circuit is arranged on the packaging gel. The conductive blind hole is located in the packaging gel and connects the electronic component and the redistribution circuit.

In an embodiment of the present invention, the thermal conductivity of the thermally conductive insulating layer is between 1 W / (mK) and 100 W / (mK).

Based on the above, in the design of the semiconductor package structure of the present invention, the electronic component is disposed on the substrate and is electrically connected to the patterned circuit layer, so the heat generated by the electronic component can sequentially pass through the patterned circuit layer of the substrate, and conduct heat. The insulating layer and the metal layer are transmitted to the outside, which can have better heat dissipation effect. Furthermore, the electronic component of the present invention is not disposed on a conventional lead frame, but is disposed on a substrate. Therefore, the semiconductor package structure of the present invention can integrate different types of electronic components on the substrate, in addition to being thinner. In addition to the thickness of the package, it can also have a wide range of applications. In addition, the edge of the packaging gel of the present invention is approximately aligned with the edge of the substrate. Therefore, the semiconductor packaging structure of the present invention can be applied to a flip-chip technology packaging structure and a square flat leadless packaging structure.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of each embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as: "up", "down", "front", "rear", "left", "right", etc., are only directions referring to the attached drawings. Therefore, the directional terms used are used for illustration, but not for limiting the present invention. And, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

1A to 1J are schematic cross-sectional views of a method for fabricating a semiconductor package structure according to a first embodiment of the present invention.

The manufacturing method of the semiconductor package structure 100 in this embodiment includes the following steps. First, referring to FIG. 1A, a substrate 110 a is provided. The substrate 110a includes a thermally conductive insulating layer 111, a first metal layer 112a, and a second metal layer 113. The thermally conductive insulating layer 111 has a first surface 111 a and a second surface 111 b that are opposed to each other. The first metal layer 112 a is disposed on the thermally conductive insulating layer 111 and completely covers the first surface 111 a of the thermally conductive insulating layer 111. The second metal layer 113 is disposed on the thermally conductive insulating layer 111 and completely covers the second surface 111 b of the thermally conductive insulating layer 111.

In this embodiment, the first metal layer 112a and / or the second metal layer 113 is, for example, a copper foil. In other words, the substrate 110a in this embodiment may be, for example, a specially designed heat-dissipating copper foil substrate (Copper Clad). Laminate; CCL), but the invention is not limited to this. In addition, the thickness of the thermally conductive insulating layer 111, the first metal layer 112a, and / or the second metal layer 113 may be adjusted according to design requirements, and is not limited in the present invention.

Next, referring to FIG. 1A and FIG. 1B, a patterning process is performed on the first metal layer 112 a (shown in FIG. 1A) to form a patterned circuit layer 112. In this embodiment, the patterning process may, for example, first form a patterned photoresist layer (not shown) on the first surface 111a of the thermally conductive insulating layer 111, and then remove the exposed photoresist layer through the patterning process through the etching process. A portion of the first metal layer 112a forms a patterned circuit layer 112 as shown in FIG. 1B. As such, the patterned circuit layer 112 may expose a portion of the first surface 111 a of the thermally conductive insulating layer 111.

In the present embodiment, the thermal conductivity of the thermally conductive insulating layer may be between 111 ^Kelvin 1 Wm ^{-1 -1 (watts per meter-kelvin;} W / (mK)) to 100 W / (mK). In one embodiment, the thermal conductivity of the thermally conductive insulating layer 111 may be between 2 W / (mK) and 3 W / (mK), but is not limited thereto. For example, the material of the thermally conductive insulating layer 111 may include a diamond-like carbon (DLC) film doped with a mixture of fluorine, silicon, nitrogen, and boron, a thermally conductive ceramic material film, or a thermally conductive filler. ) Glass fiber composite materials. Compared with an insulating layer generally composed of a glass substrate, a polyimide (PI) glass fiber composite substrate, or other similar insulating materials, the thermally conductive insulating layer 111 of this embodiment has a higher thermal conductivity. Of course, this embodiment is only used for illustration, and the present invention is not limited to the type, material, or formation method of the thermally conductive insulating layer 111. In addition, the substrate 110 formed by the thermally conductive insulating layer 111, the patterned circuit layer 112, and the metal layer described above may also have a good thermal conductivity. In this embodiment, the equivalent thermal conductivity of the substrate 110 may be 6 W / (mK) or more. In this way, the heat dissipation efficiency of the semiconductor package structure 100 formed by the substrate 110 described above can be effectively improved.

Next, referring to FIG. 1C, a solder resist layer 121 is formed on the patterned circuit layer 112 of the substrate 110. The solder mask layer 121 on the patterned circuit layer 112 has at least one opening 121a, and the opening 121a exposes a part of the patterned circuit layer 112, and defines at least one first pad 112b. A solder resist layer 122 is formed on the second metal layer 113 of the base 110. The solder resist layer 122 on the second metal layer 113 has at least one opening 122a, and the opening 122a exposes a part of the second metal layer 113, and defines at least one second pad 113b. It is worth noting that the order of forming the solder resist layer 121 on the patterned circuit layer 112 and the solder resist layer 122 on the second metal layer 113 is not limited in the present invention. In addition, in FIG. 1C, the number and size of the openings 121a where the patterned circuit layer 112 is exposed and the number and size of the openings 122a where the second metal layer 113 is exposed are only exemplary illustrations, and are used in the present invention. It is not restricted. In addition, in some embodiments, the first pad 112b and / or the second pad 113b may also be plated with a metal layer or an alloy layer such as nickel, palladium, or gold to enhance the first pad 112b and / or the second pad. The bonding force between the pad 113b and another film layer or element.

Next, referring to FIG. 1D, a conductive adhesive layer 131 is formed on a portion of the first pads 112 b. For example, the material of the conductive adhesive layer 131 is, for example, solder flux including tin powder and / or solder, silver paste, or aluminum paste. The type or material of the conductive adhesive layer 131 is not limited in the present invention. As long as the subsequently-formed electronic component 140 (as shown in FIG. 1E) can be fixed by the conductive adhesive layer 131 and electrically connected to the patterned circuit layer 112. It is worth noting that, because the first pad 112b is defined by the opening 121a of the first solder mask layer 121, the conductive adhesive layer 131 can be limited to the range of the opening 121a of the first solder mask layer 121, and will not Covers the upper surface 121b of the first solder resist layer 121.

Next, referring to FIG. 1E, an electronic component 140 is disposed on the patterned circuit layer 112 of the substrate 110. The electronic component 140 may include an active component 141 and / or a passive component 142. For example, the active device 141 may be a transistor including a source S, a drain D, and a gate G. The passive element 142 has, for example, a resistance or a capacitance of the first electrode 142a and the second electrode 142b. Taking resistance as an example, the passive element material 142c between the first electrode 142a and the second electrode 142b may be a resistance material. Alternatively, taking a capacitor as an example, the passive element material 142c between the first electrode 142a and the second electrode 142b may be a dielectric material. Since the passive element 142 is disposed on the patterned circuit layer 112 of the substrate 110 in the same way as the active element 141, the passive element 142 can also be the same as the active element 141 by the patterned circuit layer 112, the thermally conductive insulating layer 111, and the first The two metal layers 113 conduct the thermal energy transferred by the circuit to the outside, which can prevent the passive element 142 from aging due to long-term heating and reduce the service life.

Next, referring to FIG. 1F, a wafer 144 is disposed on the substrate 110. The wafer 144 has an active surface 144 a and a back 144 b opposite to the active surface 144 a. The wafer 144 is bonded to one of the first pads 112 b ′ on the substrate 110 by an insulating adhesive layer 132. In this embodiment, the chip 144 is, for example, a microcontroller (MCU) or a gate driver, but the present invention is not limited thereto. In addition, in this embodiment, the insulating adhesive layer 132 is, for example, a die attach film (DAF) with good thermal conductivity, so that the thermal energy generated during the operation of the wafer 144 can be transferred from the crystal back of the wafer 144. 144b is conducted to the substrate 110 having good thermal conductivity through the insulating adhesive layer 132.

Next, referring to FIG. 1G, an encapsulant 150 is formed on the substrate 110 to cover part of the first pad 112b ", part of the solder mask layer 121, the active element 141, the passive element 142, and the chip 144. The encapsulant 150 can be borrowed It is formed by a general molding process, so it will not be repeated here.

Next, referring to FIG. 1H, a plurality of through holes 151, 152 can be formed in the encapsulant 150 by etching, mechanical drill, laser drill, or other similar removal methods. . Part of the through hole 151 penetrates the encapsulant 150 to expose the first pad 112b "covered by the encapsulant 150. The other part of the via 152 may be located on the active element 141, the passive element 142, and / or the chip 144 to expose The gate G and the drain D of the active element 141, the first electrodes 142a and the second electrodes 142b of the passive element 142, and the active surface 144a of the chip 144 are output.

Next, referring to FIG. 1I, a redistribution circuit layer 160 is formed on the encapsulant 150. Specifically, the method for manufacturing the redistribution circuit layer 160 may include the following steps, for example. The conductive substance may be formed on the surface 150b of the encapsulant 150 by other suitable processes such as a deposition process and / or an electroplating process. In addition, a conductive substance may be further filled into the through-holes 151 and 152 (shown in FIG. 1H) of the hole-filling colloid 150 to form conductive blind holes 162 and / or conductive vias 163 having conductive properties. The conductive via 163 penetrates the packaging gel 150 to be connected to the first pad 112b "exposed by the packaging gel 150. The gate G and the drain D of the active element 141, and the first electrode 142a and the second of the passive element 142 The electrodes 142b and the active surface 144a of the wafer 144 may be connected to the corresponding conductive blind holes 162. Subsequently, the conductive material covering the surface 150b of the encapsulant 150 may be patterned by, for example, lithography and etching processes to The redistribution circuit 161 is formed. Generally, based on the consideration of conductivity, the redistribution circuit layer 160 is generally made of a metal material, but the present invention is not limited thereto.

In the embodiment shown in FIG. 1I, the source S of the two active elements 141 ′ and 141 ″ are in contact with the conductive adhesive layer 131, and the drain D of one active element 141 ′ is in contact with the other through the conductive via 163. The source S of the active element 141 "is electrically connected. That is, the two active elements 141 ′ and 141 ″ may be configured in the same direction, and the two active elements 141 ′ and 141 ″ may be connected in series with each other through the conductive via 163. In other feasible embodiments, multiple electronic components may also be connected in series, parallel, electrically independent, or a combination of the foregoing according to design requirements.

In this embodiment, other conductive materials may be further filled in the conductive via 163 to improve the conductivity of the conductive via 163, but the present invention is not limited thereto. In other embodiments, the conductive via 163 may also be a via with a hollow structure, and the inner hollow portion is filled with a hole filling material.

Next, referring to FIG. 1J, a solder resist layer 123 is disposed on the encapsulant 150, and a portion of the redistribution circuit 161 is covered by the solder resist layer 123. The solder mask layer 123 has at least one opening 123a, and the opening 123a exposes part of the redistribution circuit 161, and defines at least one third pad 161a. In addition, in FIG. 1J, the number and size of the openings 123 a in which the redistribution circuit 161 is exposed are merely exemplary illustrations, and are not limited in the present invention. In addition, in some embodiments, the third pad 161a may also be plated with a metal layer or an alloy layer such as nickel, palladium, or gold to improve the bonding force between the third pad 161a and other film layers or components. Finally, the edge forming process or the cutting forming process can be performed according to the needs. Mechanical routing, laser routing, and etching processes can be used, but it is not limited to this. Or strip-shaped packaging structure.

After the above process, the fabrication of the semiconductor package structure 100 of this embodiment can be substantially completed. Structurally, the semiconductor package structure 100 of this embodiment includes a substrate 110, an electronic component 140, a packaging gel 150, and a redistribution circuit layer 160. The substrate 110 includes a thermally conductive insulating layer 111, a patterned circuit layer 112, and a metal layer. The thermally conductive insulating layer 111 has a first surface 111 a and a second surface 111 b that are opposed to each other. The patterned circuit layer 112 is disposed on the thermally conductive insulating layer 111 and exposes a portion of the first surface 111 a of the thermally conductive insulating layer 111. The metal layer is disposed on the thermally conductive insulating layer 111 and completely covers the second surface 111 b of the thermally conductive insulating layer 111. The electronic component 140 is disposed on the substrate 110 and is electrically connected to the patterned circuit layer 112. The encapsulant 150 covers at least the electronic component 140. The redistribution circuit layer 160 is disposed on the encapsulant 150 and is electrically connected to the electronic component 140. In one embodiment, the edge 150 a of the encapsulant 150 is approximately aligned with the edge 110 b of the substrate 110. In another embodiment, the edge 160 a of the redistribution circuit layer 160 is approximately aligned with the edge 150 a of the encapsulant 150 and the edge 110 b of the substrate 110, and the edge 160 a of the redistribution circuit layer 160 may not be covered by the solder mask 123. . The encapsulation structure of the above part may be approximately aligned on the particle-shaped multilateral sides, or may be approximately aligned on the outer side of the strip-shaped approximately. Because the packaging structure is finally manufactured by a molding process, the edge 150a of the packaging gel 150 is approximately aligned with the edge 110b of the substrate 110, which can reduce unnecessary design of the packaging structure edges, further reduce the size of the packaging structure, and achieve light, thin and short effects. , To increase the scope of application of this packaging structure.

In this embodiment, the electronic component 140 is configured at least corresponding to a portion of the first pad 112b, and the adhesive layers 131, 132 (for example, active components) between the electronic component 140 and the first pad 112b, 112b ', 112b " The conductive adhesive layer 131 between the element 141 / passive element 142 and the first pads 112b, 112b "and the insulating adhesive layer 132 between the chip 144 and the first pad 112b 'have good thermal conductivity. In this way, with the above-mentioned arrangement and the substrate 110 having good thermal conductivity, and the heat generated by the electronic component 140 can be sequentially transmitted through the patterned circuit layer 112, the thermally conductive insulating layer 111, and the metal layer 113 of the substrate 110, It can be transmitted to the outside, so that the semiconductor package structure 100 can have better heat dissipation effect. Furthermore, the electronic component 140 of the present invention is not disposed on a conventional lead frame, but is disposed on a substrate 110. Therefore, the semiconductor package structure 100 of the present invention can incorporate different types of electronic components (for example, active components 141, The passive component 142 and / or the chip 144) are integrated on the substrate 110, and in addition to having a thinner package thickness, they can also have wider applicability. In addition, the edge of the packaging gel 150 of the present invention is approximately aligned with the edge 110b of the substrate 110. Therefore, the semiconductor packaging structure 100 of the present invention can be applied to various different packaging structures, such as a Flip Chip Package packaging structure. In another embodiment, the edge 160a of the redistribution circuit layer 160 is approximately aligned with the edge 150a of the packaging gel 150 and the edge 110b of the substrate 110. Therefore, the semiconductor packaging structure 100 of the present invention can be applied to a square flat leadless packaging structure. .

In some embodiments, a heat dissipation element (for example, the heat dissipation element 470 in FIG. 4 or FIG. 5 may be configured on the second pad 113b, which may be a heat dissipation plate, a heat dissipation fin, etc., but the present invention is not limited thereto), and The heat generated by the electronic component 140 can be transmitted to the outside through the patterned circuit layer 112, the thermally conductive insulating layer 111, the metal layer 113, and the heat dissipation element 470 of the substrate 110, so that the semiconductor package structure 100 can have a better heat dissipation effect. However, the present invention is not limited to this.

FIG. 2 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention. It is worth noting that, in this embodiment, the semiconductor package structure 200 is similar to the semiconductor package structure 100 shown in FIG. 1J, and similar components are denoted by the same reference numerals, and have similar functions or formation methods, and description is omitted. . Specifically, the difference between the semiconductor package structure 200 of this embodiment and the semiconductor package structure 100 shown in FIG. 1J is that the source S of the first active element 141 ″ is in contact with the conductive adhesive layer 131, and the second active element 241 The drain electrode D and the gate electrode G are respectively in contact with the corresponding conductive adhesive layers 131. That is, the two active elements 141 "and 241 'may be arranged in different directions. In this way, the two active elements 141 "and 241 'can be connected in series with each other through the corresponding conductive adhesive layer 131 and the patterned circuit layer 112, and the second electrode 142b of the passive element 142 can also have the corresponding pattern The circuit layers 112 are electrically connected to each other.

In this embodiment, the second active device 241 'may have a plurality of conductive terminals 241a. The conductive terminals 241a may be embedded in the opening 121a of the solder mask layer 121 during the manufacturing process of the semiconductor package structure 200 (shown in FIG. 1C). In order to reduce the possibility of unnecessary movement during the configuration of the second active element 241 '. In this embodiment, the conductive terminal 241a may be, for example, a solder ball, but the present invention is not limited thereto.

3 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention. It is worth noting that, in this embodiment, the semiconductor package structure 300 is similar to the semiconductor package structure 200 shown in FIG. 2, and similar components are denoted by the same reference numerals, and have similar functions or formation methods, and description is omitted. . Specifically, the difference between the semiconductor package structure 300 in this embodiment and the semiconductor package structure 200 shown in FIG. 2 is that the patterned circuit layer 112 of the substrate 310 may not have a solder resist layer (such as in FIG. 1J or FIG. 2). The illustrated solder resist layer 121), and the active elements 141 "and 241 'can directly contact the patterned circuit layer 112, and the encapsulant 150 can cover a part of the thermally conductive insulating layer 311.

In this embodiment, the thermally conductive insulating layer 311 may have a plurality of openings 311c, and the second metal layer 313 may be filled in the openings 311c of the thermally conductive insulating layer 311, so that the insulating adhesive layer 132 on the thermally conductive insulating layer 311 can communicate with The second metal layer 313 contacts to improve the heat dissipation efficiency of the semiconductor package structure 300, but the present invention is not limited thereto. In other embodiments, the insulating adhesive layer 132 may also be filled in the opening 311c of the thermal conductive insulating layer 311, so that the insulating adhesive layer 132 on the thermal conductive insulating layer 311 and the second metal layer 313 may be in contact with each other to improve the semiconductor package. Structure 300 heat dissipation efficiency.

4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the present invention. It is worth noting that, in this embodiment, the semiconductor package structure is similar to the semiconductor package structure shown in FIG. 3, and similar components are denoted by the same reference numerals, and have similar functions or formation methods, and description is omitted. Specifically, the difference between the semiconductor package structure 400 in this embodiment and the semiconductor package structure 300 shown in FIG. 3 is that a heat dissipation element 470 may be disposed on the second pad 113 b of the second metal layer 113 to improve the semiconductor package structure 400. Thermal efficiency. In a variant embodiment, the design of the heat dissipation element 470 may also be larger than the second pad 113b, and the heat dissipation element 470 may be connected to the second pad 113b through a thermally conductive glue, a thermally conductive paste, or other thermally conductive material.

In this embodiment, the substrate 110 and the electronic component 140 of the semiconductor package structure 400 may be located on the surface 401 a of the circuit board 401. That is, the semiconductor package structure 400 may be a package having a plate-like structure.

FIG. 5 is a schematic cross-sectional view of a semiconductor package structure according to a fifth embodiment of the present invention. It is worth noting that, in this embodiment, the semiconductor package structure 500 is similar to the circuit board structure 400 shown in FIG. 4, and similar components are denoted by the same reference numerals, and have similar functions or formation methods, and description is omitted. . Specifically, the semiconductor package structure 500 of this embodiment is different from the semiconductor package structure 400 shown in FIG. 4 in that the substrate 110 and the electronic component 140 of the semiconductor package structure 500 can be embedded in the circuit board 501.

In summary, in the design of the semiconductor package structure of the present invention, the electronic component is disposed on the substrate and is electrically connected to the patterned circuit layer, so the heat generated by the electronic component can sequentially pass through the patterned circuit layer of the substrate, The heat-conducting insulating layer and the metal layer are transmitted to the outside, which can have better heat dissipation effect. Furthermore, the electronic component of the present invention is not disposed on a conventional lead frame, but is disposed on a substrate. Therefore, the semiconductor package structure of the present invention can integrate different types of electronic components on the substrate, in addition to being thinner. In addition to the thickness of the package, it can also have a wide range of applications. In addition, the edge of the packaging gel of the present invention is approximately aligned with the edge of the substrate, so the semiconductor packaging structure of the present invention can be applied to a flip-chip packaging structure or a square flat no-lead packaging structure.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200, 300, 400, 500‧‧‧ semiconductor package structure

110, 110a, 310‧‧‧ substrate

110b, 150a, 160a‧‧‧Edge

111, 311‧‧‧ thermal conductive insulation

111a‧‧‧first surface

111b‧‧‧Second surface

311c, 121a, 122a, 123a

112a‧‧‧first metal layer

112‧‧‧patterned circuit layer

112b, 112b ', 112b "‧‧‧The first pad

113, 313‧‧‧Second metal layer

113b‧‧‧Second pad

121, 122, 123‧‧‧ solder mask

121b‧‧‧ Top surface

131‧‧‧ conductive adhesive layer

132‧‧‧Insulation adhesive layer

140‧‧‧Electronic components

141, 141 ', 141 ", 241'‧‧‧ active components

S‧‧‧Source

D‧‧‧ Drain

G‧‧‧Gate

241a‧‧‧Conductive terminal

142‧‧‧Passive components

142a‧‧‧First electrode

142b‧‧‧Second electrode

142c‧‧‧Passive component material

144‧‧‧Chip

144a‧‧‧active side

144b‧‧‧ Crystal back

150‧‧‧ encapsulated colloid

150b‧‧‧ surface

151, 152‧‧‧through holes

160‧‧‧ redistribution circuit layer

161‧‧‧ heavy route

161a‧‧‧Third pad

162‧‧‧Conductive blind hole

163‧‧‧ conductive via

470‧‧‧ heat dissipation element

401, 501‧‧‧ circuit board

401a‧‧‧ surface

1A to 1J are schematic cross-sectional views of a method for fabricating a semiconductor package structure according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention. 3 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention. 4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a semiconductor package structure according to a fifth embodiment of the present invention.

Claims (18)

A semiconductor package structure includes: a substrate including: a thermally conductive insulating layer having a first surface and a second surface opposite to each other; a patterned circuit layer disposed on the thermally conductive insulating layer and exposing the thermally conductive insulation Part of the first surface of the layer; and a metal layer disposed on the thermally conductive insulating layer and completely covering the second surface of the thermally conductive insulating layer; at least one electronic component disposed on the substrate and connected to the patterned circuit layer An electrical connection; a packaging gel that covers at least the at least one electronic component; a redistribution circuit layer disposed on the packaging gel and electrically connected to the at least one electronic component, wherein an edge of the packaging gel is approximately aligned with the An edge of the substrate; a first solder mask layer disposed on the metal layer of the substrate, wherein the first solder mask layer has at least one first opening, and the at least one first opening exposes part of the metal layer, and is defined At least one first pad; and a second solder mask layer disposed on the packaging gel and covering the redistribution circuit layer, wherein the second solder mask layer has at least one second opening At least one second opening exposing a portion of the redistribution layer, and define at least one second pad. The semiconductor package structure according to item 1 of the scope of patent application, further comprising: at least one conductive via penetrating through the packaging gel, wherein the redistribution circuit layer is patterned with the substrate through the at least one conductive via. The line layer is electrically connected. The semiconductor package structure according to item 1 of the patent application scope further includes: an adhesive layer disposed on the substrate, wherein the at least one electronic component is fixed on the substrate by the adhesive layer. The semiconductor package structure according to item 1 of the scope of patent application, further comprising: a third solder resist layer disposed on the thermally conductive insulating layer of the substrate and located between the packaging colloid and the thermally conductive insulating layer. Three solder mask layers cover the patterned circuit layer, wherein the third solder mask layer has at least one third opening, and the at least one third opening exposes part of the patterned circuit layer, and defines at least one third pad, The at least one electronic component is located on the at least one third pad. The semiconductor package structure according to item 1 of the scope of patent application, further comprising: at least one heat dissipation element disposed on the first pad. The semiconductor package structure according to item 1 of the scope of patent application, wherein the at least one electronic component includes a plurality of electronic components, and the electronic components are connected in series, parallel, electrically independent, or a combination thereof. The semiconductor package structure according to item 1 of the scope of patent application, wherein the at least one electronic component includes an active component and a passive component. The semiconductor package structure according to item 1 of the scope of patent application, wherein the redistribution circuit layer includes: a redistribution circuit disposed on the packaging colloid; and a plurality of conductive blind holes located in the packaging colloid and connected to the at least one Electronic components and the redistribution circuit. The semiconductor package structure according to item 1 of the scope of the patent application, wherein the thermal conductivity of the thermally conductive insulating layer is between 1 W / (mK) and 100 W / (mK). A method for manufacturing a semiconductor package structure includes: providing a substrate, the substrate including: a thermally conductive insulating layer having a first surface and a second surface opposite to each other; a patterned circuit layer disposed on the thermally conductive insulating layer And a portion of the first surface of the thermally conductive insulating layer is exposed; a metal layer is disposed on the thermally conductive insulating layer and completely covers the second surface of the thermally conductive insulating layer; and at least one electronic component is disposed on the substrate, wherein the At least one electronic component is electrically connected to the patterned circuit layer; forming a packaging gel to cover at least the at least one electronic component; forming a redistribution circuit layer on the packaging gel, wherein the redistribution circuit layer and the at least one electronic The components are electrically connected, and the edge of the encapsulant is approximately aligned with the edge of the substrate; forming a first solder mask layer on the metal layer of the substrate, wherein the first solder mask layer has at least a first opening, The at least one first opening exposes part of the metal layer, and defines at least one first pad; and a second solder resist layer is formed on the packaging gel and covers the Cloth wiring layers, wherein the at least one second solder resist layer having a second opening, the second opening exposing at least a portion of the redistribution layer, and define at least one second pad. The method for manufacturing a semiconductor package structure according to item 10 of the scope of patent application, further comprising: after forming the encapsulant to cover at least the at least one electronic component, and before forming the redistribution circuit layer on the encapsulant. Forming at least one conductive via hole penetrating the encapsulant, wherein the redistribution circuit layer is electrically connected to the patterned circuit layer of the substrate through the at least one conductive via hole. The manufacturing method of the semiconductor package structure according to item 10 of the patent application scope, further comprising: after the substrate is provided, and before the at least one electronic component is disposed on the substrate, forming an adhesive layer on the substrate, wherein The at least one electronic component is fixed on the substrate by the adhesive layer. The method for manufacturing a semiconductor package structure according to item 10 of the patent application scope, further comprising: forming a third solder mask layer on the thermally conductive insulating layer of the substrate and covering the patterned circuit layer, wherein the third solder mask layer The layer has at least one third opening. The at least one third opening exposes part of the patterned circuit layer, and defines at least one third pad. The at least one electronic component is located on the at least one third pad. The manufacturing method of the semiconductor package structure according to item 10 of the scope of patent application, further comprising: arranging at least one heat dissipation element on the first pad. The method for manufacturing a semiconductor package structure according to item 10 of the scope of the patent application, wherein the at least one electronic component includes a plurality of electronic components, and the electronic components are connected in series, parallel, electrically independent, or a combination thereof. The semiconductor package structure as described in claim 10, wherein the at least one electronic component includes an active component and a passive component. The method for manufacturing a semiconductor package structure according to item 10 of the patent application scope, wherein the redistribution circuit layer includes: a redistribution circuit disposed on the packaging colloid; and a plurality of conductive blind holes located in the packaging colloid and connected The at least one electronic component and the redistribution circuit. The method for manufacturing a semiconductor package structure according to item 10 of the scope of the patent application, wherein the thermal conductivity of the thermally conductive insulating layer is between 1 W / (mK) and 100 W / (mK).