BR9815119A - Processador digital, e, processo de traduzir códigos de operação de instruções de programa para microinstruções em um processador digital - Google Patents

Processador digital, e, processo de traduzir códigos de operação de instruções de programa para microinstruções em um processador digital

Info

Publication number
BR9815119A
BR9815119A BR9815119-3A BR9815119A BR9815119A BR 9815119 A BR9815119 A BR 9815119A BR 9815119 A BR9815119 A BR 9815119A BR 9815119 A BR9815119 A BR 9815119A
Authority
BR
Brazil
Prior art keywords
digital processor
instruction
program instruction
microinstructions
status signals
Prior art date
Application number
BR9815119-3A
Other languages
English (en)
Inventor
Tobias Roos
Dan Halvarsson
Tomas Jonsson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9815119A publication Critical patent/BR9815119A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/261—Microinstruction address formation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

"PROCESSADOR DIGITAL, E, PROCESSO DE TRADUZIR CóDIGOS DE OPERAçãO DE INSTRUçõES DE PROGRAMA PARA MICROINSTRUçõES EM UM PROCESSADOR DIGITAL" Em um sistema de computador, a unidade de decodificação de instrução para traduzir instruções de programa para instruções de microcódigo operar dinamicamente. Então, a unidade recebe sinais de estado indicando o estado do computador, tal como um sinal de habilitação de rastreamento (63), influenciando o processo de tradução na unidade de decodificação de instrução. Estes sinais de estado (63) são adicionados ao código de operação (65) da instrução de programa a ser decodificada, o código de operação da instrução de programa sendo então estendido e usado como entrada para uma tabela de tradução (55), o código de operação estendido da instrução de programa sendo considerado como um endereço de um campo na tabela. Os endereços e então os conteúdos dos campos destinados ao mesmo código de operação de uma instrução de programa, podem então sem diferentes para valores diferentes dos sinais de estado. Então, geralmente, os sinais de estado fazem com que o decodificador de instrução mude seu algoritmo de tradução, de modo que o decodificador pode decodificar um código de operação diferentemente, dependendo do estado que os sinais adotem. A decodificação dinâmica pode, para um sinal de habilitação de rastreamento, ser usado para comutar uma função traçadora. No caso normal, o rastreamento não é desejado, não há microinstruções suportando a função traçadora tendo que ser executadas, e deste modo o desempenho e, em particular, a velocidade do sistema de computador será aumentada.
BR9815119-3A 1997-12-02 1998-12-02 Processador digital, e, processo de traduzir códigos de operação de instruções de programa para microinstruções em um processador digital BR9815119A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9704475A SE520511C2 (sv) 1997-12-02 1997-12-02 Processor och förfarande för instruktionsavkodning
PCT/SE1998/002205 WO1999028817A2 (en) 1997-12-02 1998-12-02 An instruction decoder

Publications (1)

Publication Number Publication Date
BR9815119A true BR9815119A (pt) 2000-10-10

Family

ID=20409221

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9815119-3A BR9815119A (pt) 1997-12-02 1998-12-02 Processador digital, e, processo de traduzir códigos de operação de instruções de programa para microinstruções em um processador digital

Country Status (8)

Country Link
US (1) US6611909B1 (pt)
EP (1) EP1034472A2 (pt)
JP (1) JP2001525568A (pt)
AU (1) AU1581099A (pt)
BR (1) BR9815119A (pt)
CA (1) CA2313013C (pt)
SE (1) SE520511C2 (pt)
WO (1) WO1999028817A2 (pt)

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US9141389B2 (en) 2011-04-07 2015-09-22 Via Technologies, Inc. Heterogeneous ISA microprocessor with shared hardware ISA registers
US9176733B2 (en) 2011-04-07 2015-11-03 Via Technologies, Inc. Load multiple and store multiple instructions in a microprocessor that emulates banked registers
US9317288B2 (en) 2011-04-07 2016-04-19 Via Technologies, Inc. Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9043580B2 (en) 2011-04-07 2015-05-26 Via Technologies, Inc. Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
US9032189B2 (en) 2011-04-07 2015-05-12 Via Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9128701B2 (en) 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US9336180B2 (en) 2011-04-07 2016-05-10 Via Technologies, Inc. Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode
US9378019B2 (en) 2011-04-07 2016-06-28 Via Technologies, Inc. Conditional load instructions in an out-of-order execution microprocessor
US8880851B2 (en) * 2011-04-07 2014-11-04 Via Technologies, Inc. Microprocessor that performs X86 ISA and arm ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
US9645822B2 (en) 2011-04-07 2017-05-09 Via Technologies, Inc Conditional store instructions in an out-of-order execution microprocessor
US9274795B2 (en) 2011-04-07 2016-03-01 Via Technologies, Inc. Conditional non-branch instruction prediction
US9292470B2 (en) 2011-04-07 2016-03-22 Via Technologies, Inc. Microprocessor that enables ARM ISA program to access 64-bit general purpose registers written by x86 ISA program
EP2624126B1 (en) * 2011-04-07 2016-11-02 VIA Technologies, Inc. Efficient conditional ALU instruction in read-port limited register file microprocessor
US9244686B2 (en) 2011-04-07 2016-01-26 Via Technologies, Inc. Microprocessor that translates conditional load/store instructions into variable number of microinstructions
US9146742B2 (en) 2011-04-07 2015-09-29 Via Technologies, Inc. Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
US8880857B2 (en) 2011-04-07 2014-11-04 Via Technologies, Inc. Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
US8924695B2 (en) * 2011-04-07 2014-12-30 Via Technologies, Inc. Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
US9898291B2 (en) 2011-04-07 2018-02-20 Via Technologies, Inc. Microprocessor with arm and X86 instruction length decoders
US8892958B2 (en) 2012-06-15 2014-11-18 International Business Machines Corporation Dynamic hardware trace supporting multiphase operations
US9262163B2 (en) * 2012-12-29 2016-02-16 Intel Corporation Real time instruction trace processors, methods, and systems
US9697074B2 (en) 2014-12-11 2017-07-04 Internatioanl Business Machines Corporation Non-local error detection in processor systems
US10157057B2 (en) * 2016-08-01 2018-12-18 Syntel, Inc. Method and apparatus of segment flow trace analysis
JP2019095952A (ja) * 2017-11-21 2019-06-20 ソニーセミコンダクタソリューションズ株式会社 プロセッサ、情報処理装置および処理方法

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Also Published As

Publication number Publication date
SE520511C2 (sv) 2003-07-22
CA2313013A1 (en) 1999-06-10
AU1581099A (en) 1999-06-16
EP1034472A2 (en) 2000-09-13
CA2313013C (en) 2005-03-29
JP2001525568A (ja) 2001-12-11
US6611909B1 (en) 2003-08-26
SE9704475L (sv) 1999-06-23
SE9704475D0 (sv) 1997-12-02
WO1999028817A3 (en) 1999-07-22
WO1999028817A2 (en) 1999-06-10

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B09B Patent application refused [chapter 9.2 patent gazette]

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B09B Patent application refused [chapter 9.2 patent gazette]

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