BR9713649A - Dispositivo de amplificação de potência linear combinado e processo de controlar o mesmo. - Google Patents

Dispositivo de amplificação de potência linear combinado e processo de controlar o mesmo.

Info

Publication number
BR9713649A
BR9713649A BR9713649-2A BR9713649A BR9713649A BR 9713649 A BR9713649 A BR 9713649A BR 9713649 A BR9713649 A BR 9713649A BR 9713649 A BR9713649 A BR 9713649A
Authority
BR
Brazil
Prior art keywords
power
module
linear
signal
connected respectively
Prior art date
Application number
BR9713649-2A
Other languages
English (en)
Inventor
Jong-Tae Park
Young Kon Lee
Hong-Kee Kim
Young Kim
Seung-Won Chung
Seong-Hoon Lee
Soon Chul Jeong
Chul-Dong Kim
Ik-Soo Chang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019970070435A external-priority patent/KR100326313B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of BR9713649A publication Critical patent/BR9713649A/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
    • H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction
    • H03F1/3235—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction using a pilot signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/52—Circuit arrangements for protecting such amplifiers
    • H03F1/526—Circuit arrangements for protecting such amplifiers protecting by using redundant amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
    • H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
    • H03F2201/3212—Using a control circuit to adjust amplitude and phase of a signal in a signal path

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

"DISPOSITIVO DE AMPLIFICAçãO DE POTêNCIA LINEAR COMBINADO E PROCESSO DE CONTROLAR O MESMO". Um dispositivo e um processo para combinação de saídas de uma pluralidade de amplificadores de potência linear enquanto prevenindo perda de sinais. O dispositivo de amplificação de potência linear combinado, incluindo: um módulo divisor de potência (150) que tem trajetos conectados respectivamente entre um terminal de entrada e uma pluralidade de terminais de saída e chaves conectadas respectivamente a cada um dos terminais de saída para divisão de potência de uma entrada de sinal de RF ao módulo divisor de potência e respectivamente dando saída a potência dividida aos terminais de saída; um módulo combinador de potência (300) que tem trajetos conectados respectivamente entre uma pluralidade de terminais de entrada e um terminal de saída e as chaves conectadas respectivamente a cada um dos terminais de entrada, para combinação de potência de uma entrada de sinal de RF ao módulo combinador de potência e dando saída a potência combinado; e amplificadores de potência linear (200) que são conectados entre os terminais de saída do módulo divisor de potência e os terminais de entrada do módulo combinador de potência, para linear amplificação do sinal de RF dividido em potência no módulo divisor de potência por esse meio dando saída ao sinal linear amplificado ao módulo combinador de potência, e na geração de um estado falho dos amplificadores de potência linear, o amplificador falho abrindo o trajeto do sinal de RF afetado pelo desligamento das correspondentes chaves no dito módulo divisor de potência e dito módulo combinador de potência.
BR9713649-2A 1996-12-30 1997-12-29 Dispositivo de amplificação de potência linear combinado e processo de controlar o mesmo. BR9713649A (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR19960076706 1996-12-30
KR1019970070435A KR100326313B1 (ko) 1996-12-30 1997-12-19 합성선형증폭장치및방법
PCT/KR1997/000281 WO1998029941A1 (en) 1996-12-30 1997-12-29 Combined linear power amplifying device and method

Publications (1)

Publication Number Publication Date
BR9713649A true BR9713649A (pt) 2000-04-11

Family

ID=26632415

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9713649-2A BR9713649A (pt) 1996-12-30 1997-12-29 Dispositivo de amplificação de potência linear combinado e processo de controlar o mesmo.

Country Status (10)

Country Link
US (1) US5986500A (pt)
EP (1) EP0948838B1 (pt)
JP (1) JP3434519B2 (pt)
CN (1) CN1134886C (pt)
AU (1) AU733748B2 (pt)
BR (1) BR9713649A (pt)
CA (1) CA2276311C (pt)
DE (1) DE69724146T2 (pt)
ES (1) ES2205269T3 (pt)
WO (1) WO1998029941A1 (pt)

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Also Published As

Publication number Publication date
AU5344698A (en) 1998-07-31
EP0948838B1 (en) 2003-08-13
CA2276311C (en) 2001-12-18
CN1249080A (zh) 2000-03-29
AU733748B2 (en) 2001-05-24
DE69724146D1 (de) 2003-09-18
DE69724146T2 (de) 2004-02-26
EP0948838A1 (en) 1999-10-13
JP2000508149A (ja) 2000-06-27
JP3434519B2 (ja) 2003-08-11
WO1998029941A1 (en) 1998-07-09
ES2205269T3 (es) 2004-05-01
US5986500A (en) 1999-11-16
CA2276311A1 (en) 1998-07-09
CN1134886C (zh) 2004-01-14

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Legal Events

Date Code Title Description
B15K Others concerning applications: alteration of classification

Free format text: ALTERADA A CLASSIFICACAO PARA INT.CL. 2008.01 H03F 3/24; H03F 3/20; H03F 1/32

Ipc: H03F 3/24 (2008.04), H03F 3/20 (2008.04), H03F 1/3

B07A Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: INDEFERIDO COM BASE NO ARTIGO 8O COMBINADO COM O ART.13 DA LPI

B09B Patent application refused [chapter 9.2 patent gazette]

Free format text: MANTIDO O INDEFERIMENTO UMA VEZ QUE NAO FOI APRESENTADO RECURSO DENTRO DO PRAZO LEGAL.