BR9711505A - Sistema para permitir que o processador i/o opere sob diferentes algoritmos de transferência. - Google Patents

Sistema para permitir que o processador i/o opere sob diferentes algoritmos de transferência.

Info

Publication number
BR9711505A
BR9711505A BR9711505-3A BR9711505A BR9711505A BR 9711505 A BR9711505 A BR 9711505A BR 9711505 A BR9711505 A BR 9711505A BR 9711505 A BR9711505 A BR 9711505A
Authority
BR
Brazil
Prior art keywords
processor
allow
under different
operate under
different transfer
Prior art date
Application number
BR9711505-3A
Other languages
English (en)
Inventor
Marc Blumer
Wayne Ando
Original Assignee
Eletronics For Imaging Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eletronics For Imaging Inc filed Critical Eletronics For Imaging Inc
Publication of BR9711505A publication Critical patent/BR9711505A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Record Information Processing For Printing (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

Patente de Invenção: <B>"SISTEMA PARA PERMITIR QUE O PROCESSADOR I/O OPERE SOB DIFERENTES ALGORITMOS DE TRANSFERêNCIA".<D> Um controlador programável DMA
BR9711505-3A 1996-09-18 1997-07-24 Sistema para permitir que o processador i/o opere sob diferentes algoritmos de transferência. BR9711505A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/716,555 US5835788A (en) 1996-09-18 1996-09-18 System for transferring input/output data independently through an input/output bus interface in response to programmable instructions stored in a program memory
PCT/US1997/013142 WO1998012630A1 (en) 1996-09-18 1997-07-24 System for allowing i/o processor to operate under different transfer algorithms

Publications (1)

Publication Number Publication Date
BR9711505A true BR9711505A (pt) 2000-01-18

Family

ID=24878476

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9711505-3A BR9711505A (pt) 1996-09-18 1997-07-24 Sistema para permitir que o processador i/o opere sob diferentes algoritmos de transferência.

Country Status (9)

Country Link
US (1) US5835788A (pt)
EP (1) EP1012706A1 (pt)
JP (1) JP2001502082A (pt)
AU (1) AU714338B2 (pt)
BR (1) BR9711505A (pt)
CA (1) CA2265694C (pt)
IL (1) IL129013A0 (pt)
NZ (1) NZ334674A (pt)
WO (1) WO1998012630A1 (pt)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10124268A (ja) * 1996-08-30 1998-05-15 Canon Inc 印字制御装置
EP0935195A2 (en) 1998-02-06 1999-08-11 Analog Devices, Inc. "An integrated circuit with a high resolution analog-to-digital converter, a microcontroller and high density memory and an emulator for an integrated circuit
US6701395B1 (en) * 1998-02-06 2004-03-02 Analog Devices, Inc. Analog-to-digital converter that preseeds memory with channel identifier data and makes conversions at fixed rate with direct memory access
US6092124A (en) 1998-04-17 2000-07-18 Nvidia Corporation Method and apparatus for accelerating the rendering of images
US6223339B1 (en) * 1998-09-08 2001-04-24 Hewlett-Packard Company System, method, and product for memory management in a dynamic translator
US6624761B2 (en) 1998-12-11 2003-09-23 Realtime Data, Llc Content independent data compression method and system
IL128007A (en) * 1999-01-11 2003-02-12 Milsys Ltd Enhancements on compact logic devices and also for accelerating and securing computations in modular arithmetic especially for use in public key cryptographic co-processors designed for elliptic curve and rsa type computations
US6324598B1 (en) * 1999-01-11 2001-11-27 Oak Technology Software enlarged tag register and method thereof for noting the completion of a DMA transfer within a chain of DMA transfers
US6330631B1 (en) * 1999-02-03 2001-12-11 Sun Microsystems, Inc. Data alignment between buses
US6604158B1 (en) 1999-03-11 2003-08-05 Realtime Data, Llc System and methods for accelerated data storage and retrieval
US6601104B1 (en) 1999-03-11 2003-07-29 Realtime Data Llc System and methods for accelerated data storage and retrieval
JP2001022689A (ja) * 1999-07-06 2001-01-26 Mitsubishi Electric Corp 出力ｆｉｆｏデータ転送制御装置
US6449665B1 (en) 1999-10-14 2002-09-10 Lexmark International, Inc. Means for reducing direct memory access
US6728853B1 (en) * 1999-12-14 2004-04-27 Genesis Microchip Inc. Method of processing data utilizing queue entry
US20010047473A1 (en) 2000-02-03 2001-11-29 Realtime Data, Llc Systems and methods for computer initialization
US6816924B2 (en) * 2000-08-10 2004-11-09 Infineon Technologies North America Corp. System and method for tracing ATM cells and deriving trigger signals
US8692695B2 (en) 2000-10-03 2014-04-08 Realtime Data, Llc Methods for encoding and decoding data
US7417568B2 (en) 2000-10-03 2008-08-26 Realtime Data Llc System and method for data feed acceleration and encryption
US9143546B2 (en) 2000-10-03 2015-09-22 Realtime Data Llc System and method for data feed acceleration and encryption
GB0028354D0 (en) * 2000-11-21 2001-01-03 Aspex Technology Ltd Improvements relating to memory addressing
US7386046B2 (en) 2001-02-13 2008-06-10 Realtime Data Llc Bandwidth sensitive data compression and decompression
WO2002084498A1 (en) * 2001-04-11 2002-10-24 Chelsio Communications, Inc. Reduced-overhead dma
US7324220B1 (en) 2001-07-09 2008-01-29 Lexmark International, Inc. Print performance under the windows® operating system
ITTO20010838A1 (it) * 2001-08-30 2003-03-02 Telecom Italia Lab Spa Metodo per trasferire dati in un circuito elettronico, circuito elettronico e dispositivo relativo.
US7249248B2 (en) * 2002-11-25 2007-07-24 Intel Corporation Method, apparatus, and system for variable increment multi-index looping operations
DE10256586A1 (de) * 2002-12-04 2004-06-17 Philips Intellectual Property & Standards Gmbh Datenverarbeitungseinrichtung mit Mikroprozessor und mit zusätzlicher Recheneinheit sowie zugeordnetes Verfahren
US20050138233A1 (en) * 2003-12-23 2005-06-23 Intel Corporation Direct memory access control
US8427490B1 (en) 2004-05-14 2013-04-23 Nvidia Corporation Validating a graphics pipeline using pre-determined schedules
US7334056B2 (en) * 2004-08-09 2008-02-19 Lsi Logic Corporation Scalable architecture for context execution
US8624906B2 (en) 2004-09-29 2014-01-07 Nvidia Corporation Method and system for non stalling pipeline instruction fetching from memory
US8736623B1 (en) 2004-11-15 2014-05-27 Nvidia Corporation Programmable DMA engine for implementing memory transfers and video processing for a video processor
JP4560398B2 (ja) * 2004-12-15 2010-10-13 シャープ株式会社 データ処理回路
US9092170B1 (en) 2005-10-18 2015-07-28 Nvidia Corporation Method and system for implementing fragment operation processing across a graphics bus interconnect
JPWO2008068937A1 (ja) * 2006-12-01 2010-03-18 三菱電機株式会社 データ転送制御装置およびコンピュータシステム
US8683126B2 (en) * 2007-07-30 2014-03-25 Nvidia Corporation Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory
US9024957B1 (en) 2007-08-15 2015-05-05 Nvidia Corporation Address independent shader program loading
US8698819B1 (en) 2007-08-15 2014-04-15 Nvidia Corporation Software assisted shader merging
US8411096B1 (en) 2007-08-15 2013-04-02 Nvidia Corporation Shader program instruction fetch
US8659601B1 (en) 2007-08-15 2014-02-25 Nvidia Corporation Program sequencer for generating indeterminant length shader programs for a graphics processor
US8780123B2 (en) * 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8681861B2 (en) * 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) * 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8489851B2 (en) * 2008-12-11 2013-07-16 Nvidia Corporation Processing of read requests in a memory controller using pre-fetch mechanism
US7870309B2 (en) * 2008-12-23 2011-01-11 International Business Machines Corporation Multithreaded programmable direct memory access engine
CN102197647A (zh) * 2009-08-24 2011-09-21 松下电器产业株式会社 电视会议系统、电视会议装置、电视会议控制方法以及程序
JP5268841B2 (ja) * 2009-09-11 2013-08-21 三菱電機株式会社 情報処理装置
US20150186311A1 (en) * 2013-12-28 2015-07-02 Ming Kiat Yap Smart direct memory access
US10069766B2 (en) 2015-07-07 2018-09-04 TransferSoft, Inc. Accelerated data transfer using thread pool for parallel operations
KR102395541B1 (ko) * 2015-07-09 2022-05-11 에스케이하이닉스 주식회사 메모리 컨트롤 유닛 및 그것을 포함하는 데이터 저장 장치
CN107357745A (zh) * 2016-05-09 2017-11-17 飞思卡尔半导体公司 具有算术单元的dma控制器
FR3070514B1 (fr) * 2017-08-30 2019-09-13 Commissariat A L'energie Atomique Et Aux Energies Alternatives Controleur d'acces direct en memoire, dispositif et procede de reception, stockage et traitement de donnees correspondants
CN108388527B (zh) * 2018-02-02 2021-01-26 上海兆芯集成电路有限公司 直接存储器存取引擎及其方法
WO2020232705A1 (zh) * 2019-05-23 2020-11-26 深圳市大疆创新科技有限公司 数据搬运方法、计算处理装置、设备及存储介质
CN115754971B (zh) * 2023-01-10 2023-09-15 湖南傲英创视信息科技有限公司 一种基于离散dma技术的雷达数据采集存储方法和系统

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4042914A (en) * 1976-05-17 1977-08-16 Honeywell Information Systems Inc. Microprogrammed control of foreign processor control functions
US4821180A (en) * 1985-02-25 1989-04-11 Itt Corporation Device interface controller for intercepting communication between a microcomputer and peripheral devices to control data transfers
US4809216A (en) * 1986-08-25 1989-02-28 Digital Equipment Corporation Print engine data interface
JPS63146566A (ja) * 1986-12-09 1988-06-18 Ricoh Co Ltd デジタル複写機
US4992958A (en) * 1988-06-27 1991-02-12 Hitachi, Ltd. Method and apparatus for controlling printer
US5057997A (en) * 1989-02-13 1991-10-15 International Business Machines Corp. Interruption systems for externally changing a context of program execution of a programmed processor
US4984182A (en) * 1989-07-12 1991-01-08 Ricoh Company, Ltd. Laser printer controller flexible frame buffer achitecture which allows software to initiate the loading of a frame buffer start address
US5276781A (en) * 1989-07-12 1994-01-04 Ricoh Company, Ltd. Laser printer controller flexible frame buffer architecture which allows hardware assisted memory erase
US5023813A (en) * 1989-08-03 1991-06-11 International Business Machines Corporation Non-volatile memory usage
JP2527821B2 (ja) * 1989-09-14 1996-08-28 株式会社日立製作所 デ―タ処理方法及び入出力装置
US5163123A (en) * 1990-04-25 1992-11-10 Minolta Camera Kabushiki Kaisha Synchronously transferring image data to a printer
US5345567A (en) * 1991-06-10 1994-09-06 International Business Machines Corporation System and method for modifying program status word system mask, system access key, and address space code with overlap enabled
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5307458A (en) * 1991-12-23 1994-04-26 Xerox Corporation Input/output coprocessor for printing machine
US5315691A (en) * 1992-01-22 1994-05-24 Brother Kogyo Kabushiki Kaisha Print control apparatus
JP3515142B2 (ja) * 1992-06-11 2004-04-05 セイコーエプソン株式会社 データ転送制御装置
AU5169093A (en) * 1992-10-02 1994-04-26 Compaq Computer Corporation Method for improving scsi operations by actively patching scsi processor instructions
WO1994027215A1 (en) * 1993-05-07 1994-11-24 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US5588120A (en) * 1994-10-03 1996-12-24 Sanyo Electric Co., Ltd. Communication control system for transmitting, from one data processing device to another, data of different formats along with an identification of the format and its corresponding DMA controller

Also Published As

Publication number Publication date
CA2265694C (en) 2001-09-25
AU714338B2 (en) 1999-12-23
CA2265694A1 (en) 1998-03-26
IL129013A0 (en) 2000-02-17
WO1998012630A1 (en) 1998-03-26
AU3814697A (en) 1998-04-14
US5835788A (en) 1998-11-10
EP1012706A1 (en) 2000-06-28
NZ334674A (en) 2000-09-29
JP2001502082A (ja) 2001-02-13

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Legal Events

Date Code Title Description
FB34 Technical and formal requirements: requirement - article 34 of industrial property law
FA14 Dismissal: dismissal - article 34 of industrial property law
B15K Others concerning applications: alteration of classification

Ipc: G06F 9/38 (2006.01), G06F 13/28 (2006.0

B11T Dismissal of application maintained [chapter 11.20 patent gazette]