WO2020232705A1 - 数据搬运方法、计算处理装置、设备及存储介质 - Google Patents

数据搬运方法、计算处理装置、设备及存储介质 Download PDF

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Publication number
WO2020232705A1
WO2020232705A1 PCT/CN2019/088163 CN2019088163W WO2020232705A1 WO 2020232705 A1 WO2020232705 A1 WO 2020232705A1 CN 2019088163 W CN2019088163 W CN 2019088163W WO 2020232705 A1 WO2020232705 A1 WO 2020232705A1
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Prior art keywords
data
dma controller
transfers
completed
processor
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PCT/CN2019/088163
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English (en)
French (fr)
Inventor
陈晓光
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深圳市大疆创新科技有限公司
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Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to PCT/CN2019/088163 priority Critical patent/WO2020232705A1/zh
Priority to CN201980008842.2A priority patent/CN111615692A/zh
Publication of WO2020232705A1 publication Critical patent/WO2020232705A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/282—Cycle stealing DMA
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer

Definitions

  • This application relates to the field of data processing technology, in particular to a data transfer method, a computing processing device, a computing processing device, and a computer-readable storage medium.
  • Embedded technology is developing rapidly, but computing resources in embedded systems are relatively scarce.
  • the embedded system not only uses more and more CPU (Central Processing Unit, central processing unit) resources, but also requires more and more real-time data.
  • CPU Central Processing Unit, central processing unit
  • mass data transfer generally no longer uses CPU for operation, but uses DMA (Direct Memory Access) controller for data transfer.
  • DMA Direct Memory Access
  • the CPU configures a section of DMA data and starts the DMA transfer. After the DMA transfer is successful, an interrupt is usually generated to the CPU, and the CPU configures the DMA data again for the next data transfer.
  • the CPU overhead caused by this method is relatively large, and when the interrupts are frequent, the CPU response may not be timely, which may lead to data loss.
  • this application is proposed to provide a data transfer method, computing processing device, computing processing equipment, and computer-readable storage medium that overcome or at least partially solve the above problems.
  • a data transfer method is provided, which is applied to an external device, including:
  • the processor According to the number of completed transfers reaching the target number of transfers, the processor is notified that the data transfer is completed.
  • a computing processing device for implementing data transfer, the computing processing device including an external device, a DMA controller, and a processor;
  • the external device is used to: obtain transport configuration information, where the transport configuration information includes the target number of transports; trigger the DMA controller to perform multiple data transports; determine the number of completed transports of the DMA controller; When the number of completed transfers reaches the target number of transfers, the processor is notified that the data transfer is completed.
  • a computer program including computer-readable code, which, when the computer-readable code runs on a computing processing device, causes the computing processing device to execute the aforementioned data transfer method.
  • Figure 1 shows a flow chart of the steps of a data transfer method according to the first embodiment of the present invention
  • Figure 2 shows a schematic diagram of a handshake between an external device and a DMA controller
  • FIG. 3 shows a flowchart of the steps of a data transfer method according to the second embodiment of the present invention
  • Figure 4 shows a schematic diagram of the data transfer process
  • Fig. 5 schematically shows a block diagram of a computing processing device for executing the method according to the present invention.
  • Fig. 6 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present invention.
  • the DMA controller is an external device that transfers data within the system.
  • the function of the DMA controller is to perform the transfer under the programming control of the processor. It can be regarded as a type that can connect internal and external memory with a set of dedicated buses. A controller connected to each external device with DMA capability.
  • the external device can generate or obtain data.
  • the external device When the external device generates or obtains the data, in order to move the data, it usually generates an interrupt signal to the processor, and the processor directly transports the data or the processor is equipped with a DMA controller to transport the data go. If the external device generates or obtains data frequently or the amount of data is relatively large, it may happen that the processor is not handled in time or the processor is not configured with the DMA controller in time, which may cause data loss.
  • the data input provided by the external device is periodic, frequent, or continuous data, in order to avoid the problem of data loss caused by untimely processor response.
  • the present invention provides a data transfer mechanism, which is applied to external equipment. By acquiring transfer configuration information, triggering the DMA controller to perform multiple data transfers, determining the number of completed transfers of the DMA controller, and reaching the target transfer according to the number of completed transfers The number of times, the processor is notified of the completion of the data transfer, so that the data transfer no longer depends on the way the processor responds to the interrupt.
  • the external device can directly trigger the DMA controller to perform multiple data transfers, avoiding the problem of waiting for the processor to respond each data transfer. The purpose of continuous and uninterrupted data transfer is realized, and the problem of data loss caused by untimely processor response is solved.
  • the present invention is applicable but not limited to the above application scenarios.
  • Step 101 Acquire transportation configuration information, where the transportation configuration information includes the target number of transportations.
  • the external device in order to avoid the need to wait for the processor response for each data transfer during the data transfer process, can be configured in advance to obtain the transfer configuration information, which includes the number of configured data transfers, which is recorded as the target Number of transfers.
  • the transportation configuration information can be configured according to the characteristics and actual needs of the external device, which is not limited in the embodiment of the present invention.
  • the software configures the bandwidth acquisition device in advance, obtains the transportation configuration information, and sends the transportation configuration information to the bandwidth acquisition device.
  • the target number of transports is configured to be 1024.
  • the bandwidth acquisition device can set a special register to store the target number of transfers.
  • Step 102 Trigger the DMA controller to perform multiple data transfers.
  • the DMA controller no longer generates an interrupt To the processor, but let the DMA controller wait for the external device to trigger the next data transfer, that is, the external device triggers the DMA controller to perform multiple data transfers.
  • the processor will not be notified, nor Will wait for the response of the processor to configure the next data transfer.
  • an implementation manner for triggering the DMA controller to perform multiple data transfers may include: sending a request signal for each data transfer to the DMA controller; receiving a feedback signal for completing each transfer by the DMA controller.
  • the schematic diagram of the handshake between the external device and the DMA controller, the external device and the DMA controller are synchronized by the handshake signal realized by hardware, when the external device has data to be transferred, the dma_req signal is used (That is, the request signal) is sent directly to the DMA controller, and the DMA controller performs data transfer according to the transfer configuration information. After the transfer is completed, it sends the dma_ack signal (ie feedback signal) to the external device.
  • the external device will generate the next time after receiving the dma_ack signal
  • the dma_req signal is no longer interspersed with software processing during the data transfer process of the target transfer times, and the processor will be notified only after the data transfer of the target transfer times is completed.
  • Step 103 Determine the number of completed transfers of the DMA controller.
  • the external device may determine the number of completed transactions each time after completing the data transfer, and record it as the number of completed transfers.
  • an implementation manner of determining the number of completed transports of the DMA controller may include: determining the number of completed transports according to a feedback signal. Each time the external device receives a feedback signal, which means that a data transfer is completed, the number of completed transfers can be increased by one, that is, the number of completed transfers can be counted according to the feedback signal to obtain the current number of completed transfers.
  • the external device can set a special register to store the number of completed transfers. By default, the value in this register is set to 0. After each feedback signal is received, the value in this register is increased by 1 to confirm that the transfer has been completed. frequency.
  • Step 104 According to the number of completed transfers reaching the target number of transfers, the processor is notified that the data transfer is completed.
  • the processor when the number of completed transfers does not reach the target number of transfers, the processor does not need to be notified, and the external device continues to trigger the DMA controller for data transfer; when the number of completed transfers reaches the target number of transfers, the processor is notified After the data transfer is completed, the processor performs subsequent data processing.
  • the handling configuration information is obtained through an external device, and the handling configuration information includes the target handling times, triggers the DMA controller to perform multiple data handling, determines the completed handling times of the DMA controller, and reaches the target according to the completed handling times
  • the number of transfers informs the processor that the data transfer is completed, so that the data transfer no longer depends on the way the processor responds to interrupts.
  • the external device can directly trigger the DMA controller to perform multiple data transfers, avoiding the problem of waiting for the processor to respond each data transfer , To achieve the purpose of continuous and uninterrupted data transfer, and solve the problem of data loss caused by the processor's untimely response.
  • FIG. 3 there is shown a flow chart of the steps of a data transfer method according to the second embodiment of the present invention, which is applied to an external device and may specifically include the following steps:
  • Step 201 Obtain transportation configuration information, where the transportation configuration information includes the target number of transportations.
  • Step 202 Send a request signal for each data transfer to the DMA controller.
  • Step 203 transfer data to at least two cache units via the DMA controller, where the first cache unit of the at least two cache units is full of data and then switches to the second cache unit to continue writing. After the cache unit is full of data, the processor is notified to perform processing so as to clear the first cache unit full of data.
  • the purpose of continuous data transfer is achieved, but when the system cache is relatively small, the size of the cache determines the upper limit of the target transfer times. After the cache is full, the data will be lost if the transfer is continued, which will result in no longer Time to obtain data from external devices.
  • At least two cache units may be used as a cache for data transfer.
  • the data of the external device can be transferred to at least two buffer units through the DMA controller.
  • the first cache unit of the at least two cache units is switched to the second cache unit to continue writing after being full of data, and the processor is notified to perform processing after the first cache unit is full of data, so as to clear the first cache full of data unit.
  • the processor may also be a third cache unit, a fourth cache unit, etc., which are not limited in the embodiment of the present invention.
  • the processing of the data in the first cache unit by the processor includes, but is not limited to: transporting the data in the first cache unit to other storage spaces by the processor, or extracting the data in the first cache unit by the processor, and
  • the operation of setting data is not limited in the embodiment of the present invention.
  • the switching of the cache unit can be implemented by software or hardware.
  • the way of software implementation is that when a cache unit is full of data, the DMA controller generates an interrupt signal to the processor, and the processor triggers the data transfer of the next cache unit, and at the same time transfers the data in the cache unit that has been filled with data. Perform processing so that the cache unit can be used next time, and at least two cache units are recycled, so that there will always be enough cache usage.
  • the transport configuration information further includes the amount of data to be transported each time and the addresses and lengths of the at least two buffer units, and the data is transported to at least two through the DMA controller.
  • An implementation manner of a cache unit may include: determining a cache unit for writing data for data transfer according to the number of completed transfers, the amount of data transferred each time, and the addresses and lengths of the at least two cache units .
  • the transportation configuration information acquired by the external device includes not only the target number of transportations, but also the amount of data to be moved each time and the addresses and lengths of at least two cache units.
  • the external device can determine the spatial location of the cache unit in the memory according to the address of the cache unit, so as to configure the destination address of the DMA controller for data transfer. According to the length of the buffer unit, the number of completed transfers, and the amount of data transferred each time, the external device can determine whether the buffer unit is full of data and decide whether to switch the buffer unit.
  • the external device can directly determine the cache unit used to write data for data transfer, without waiting for the processor to respond to the interrupt to configure the DMA controller, that is, the hardware realizes the automatic switching of the cache unit to achieve continuous uninterrupted data Transport to ensure that periodic, frequent, or continuous data will not be lost.
  • an implementation manner for determining a cache unit for writing data to perform data transfer may include : According to the length of the first buffer unit, the number of completed transfers and the amount of data transferred each time, it is determined that the first buffer unit is not full of data, and the data is transferred to the first buffer unit via the DMA controller.
  • the software can actively stop the data transfer.
  • One implementation manner may include: after determining that the first buffer unit is not full of data according to the length of the first buffer unit, the number of completed transfers, and the amount of data transferred per transfer, receiving a data transfer end request; control The DMA controller stops transferring data to the first buffer unit. If the end request of the data transfer is not received, the data transfer will continue.
  • the software needs to transfer the data in the first cache unit for processing, so that the entire data transfer process can be ended.
  • an implementation manner for determining a cache unit for writing data to perform data transfer may include : According to the length of the first buffer unit, the number of completed transfers and the amount of data transferred each time, it is determined that the first buffer unit is full of data, and the data is transferred to the second buffer unit via the DMA controller according to the address of the second buffer unit. Cache unit. At the same time, the processor is notified to transport the data in the first cache unit for processing.
  • another implementation manner of deciding whether to stop the data transfer may include: software checking whether the number of completed transfers has reached the configured target transfer If the number of times is reached, the data transfer process ends, otherwise the data transfer continues to the second buffer unit.
  • the address, length and target transfer times of the dual buffer are configured by software.
  • the external device triggers the start of the data transfer through the hardware handshake signal with the DMA controller.
  • Judge whether the current Buffer is full If it is full, the hardware generates an interrupt signal to the processor and automatically switches to another Buffer.
  • the software moves the data in the current Buffer away. Then it is judged whether the number of completed transfers has reached the target transfer number, if the target transfer number is reached, the data transfer process is ended, and if the target transfer number is not reached, the data transfer is continued.
  • the current buffer is not full, it will determine whether the software has triggered the end request of the data transfer. If the end request of the data transfer has not been triggered, the data transfer will continue. If the end request of the data transfer has been triggered, the software will change the The data is moved away, and the entire data movement process is ended.
  • Step 204 Receive a feedback signal that the DMA controller completes each transfer.
  • Step 205 Determine the number of completed transports based on the feedback signal.
  • Step 206 Control the DMA controller to generate an interrupt signal and send it to the processor according to the number of completed transfers reaching the target number of transfers.
  • a request signal for each data transport is sent to the DMA controller, the data is transported to at least two buffer units via the DMA controller, and the data is received.
  • the DMA controller completes a feedback signal for each transfer, determines the number of completed transfers according to the feedback signal, and controls the DMA controller to generate an interrupt signal according to the number of completed transfers reaching the target number of transfers Send to the processor so that the data transfer no longer depends on the way the processor responds to the interrupt.
  • the external device can directly trigger the DMA controller to perform multiple data transfers, avoiding the problem of waiting for the processor to respond each time the data is transferred.
  • the purpose of continuous uninterrupted data transfer solves the problem of data loss caused by the processor's untimely response.
  • the hardware realizes the automatic switching of the cache unit, realizes continuous and uninterrupted data transfer, and ensures that the periodic, frequent, or continuous data will not be lost.
  • the third embodiment of the present invention provides a computing and processing device for data transfer.
  • the computing and processing device includes an external device, a DMA controller, and a processor.
  • the external device is used to: obtain transfer configuration information.
  • the configuration information includes the target number of transfers, triggers the DMA controller to perform multiple data transfers, determines the number of completed transfers of the DMA controller, and informs the processor of the data based on the number of completed transfers reaching the target number of transfers The handling is complete.
  • the external device When the external device triggers the DMA controller to perform multiple data transfers, it is specifically used to: send a request signal for each data transfer to the DMA controller; receive a feedback signal that the DMA controller completes each transfer.
  • the external device When determining the number of completed transports of the DMA controller, the external device is specifically configured to: determine the number of completed transports according to the feedback signal.
  • the external device When the external device triggers the DMA controller to perform multiple data transfers, it is specifically used to: transfer data to at least two cache units via the DMA controller, wherein the first cache unit of the at least two cache units After the data is full, it switches to the second cache unit to continue writing. After the first cache unit is full of data, the processor is notified to perform processing to clear the first cache unit full of data.
  • the transport configuration information further includes the amount of data to be transported each time and the addresses and lengths of the at least two cache units, and the external device is specifically used to: when transporting data to the at least two cache units via the DMA controller: According to the number of completed transfers, the amount of data transferred each time, and the addresses and lengths of the at least two cache units, a cache unit for writing data is determined for data transfer.
  • the external device determines the buffer unit for writing data to perform data transfer according to the number of completed transfers, the amount of data transferred each time, and the addresses and lengths of the at least two buffer units
  • the external device is specifically used to: The length of the first buffer unit, the number of completed transfers, and the amount of data transferred per time determine that the first buffer unit is not full of data; the data is transferred to the first buffer unit via the DMA controller .
  • the external device is further configured to: after determining that the first buffer unit is not full of data based on the length of the first buffer unit, the number of completed transfers, and the amount of data transferred each time, receive data transfer End request; controlling the DMA controller to stop transferring data to the first buffer unit.
  • the external device determines the buffer unit for writing data to perform data transfer according to the number of completed transfers, the amount of data transferred each time, and the addresses and lengths of the at least two buffer units
  • the external device is specifically used to: The length of the first buffer unit, the number of completed transfers, and the amount of data transferred each time determine that the first buffer unit is full of data; according to the address of the second buffer unit, the DMA controls The device carries the data to the second buffer unit.
  • the external device When the external device notifies the processor that the data transfer is completed, it is specifically used to: control the DMA controller to generate an interrupt signal and send it to the processor.
  • the handling configuration information is obtained through an external device, and the handling configuration information includes the target handling times, triggers the DMA controller to perform multiple data handling, determines the completed handling times of the DMA controller, and reaches the target according to the completed handling times
  • the number of transfers informs the processor that the data transfer is completed, so that the data transfer no longer depends on the way the processor responds to interrupts.
  • the external device can directly trigger the DMA controller to perform multiple data transfers, avoiding the problem of waiting for the processor to respond each data transfer , To achieve the purpose of continuous and uninterrupted data transfer, and solve the problem of data loss caused by the processor's untimely response.
  • the device embodiments described above are merely illustrative.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement it without creative work.
  • the various component embodiments of the present invention may be implemented by hardware, or by software modules running on one or more processors, or by a combination of them.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present invention.
  • DSP digital signal processor
  • the present invention can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein.
  • Such a program for realizing the present invention may be stored on a computer-readable medium, or may have the form of one or more signals. Such signals can be downloaded from Internet websites, or provided on carrier signals, or provided in any other form.
  • FIG. 5 shows a computing processing device that can implement the method according to the present invention.
  • the computing processing device traditionally includes a processor 1010 and a computer program product in the form of a memory 1020 or a computer readable medium.
  • the memory 1020 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 1020 has a storage space 1030 for executing the program code 1031 of any method step in the above method.
  • the storage space 1030 for program codes may include various program codes 1031 for implementing various steps in the above method. These program codes can be read out from or written into one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards or floppy disks.
  • Such a computer program product is usually a portable or fixed storage unit as described with reference to FIG. 6.
  • the storage unit may have storage segments, storage spaces, etc. arranged similarly to the memory 1020 in the computing processing device of FIG. 5.
  • the program code can be compressed in an appropriate form, for example.
  • the storage unit includes computer-readable codes 1031', that is, codes that can be read by, for example, a processor such as 1010. These codes, when run by a computing processing device, cause the computing processing device to execute the method described above. The various steps.
  • any reference signs placed between parentheses should not be constructed as a limitation to the claims.
  • the word “comprising” does not exclude the presence of elements or steps not listed in the claims.
  • the word “a” or “an” preceding an element does not exclude the presence of multiple such elements.
  • the invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several devices, several of these devices may be embodied by the same hardware item.
  • the use of the words first, second, and third, etc. do not indicate any order. These words can be interpreted as names.

Abstract

本申请公开了一种数据搬运方法、计算处理装置、设备和存储介质。所述方法包括：获取搬运配置信息，搬运配置信息包括目标搬运次数(101)，触发DMA控制器进行多次数据搬运(102)，确定DMA控制器的已完成搬运次数(103)，根据已完成搬运次数达到了目标搬运次数，通知处理器数据搬运完成(104)，使得数据搬运不再依赖处理器响应中断的方式，外部设备可以直接触发DMA控制器进行多次数据搬运，避免每次数据搬运都需等待处理器响应的问题，实现了持续不间断的数据搬运的目的，解决了处理器响应不及时导致数据丢失的问题。

Description

数据搬运方法、计算处理装置、设备及存储介质 技术领域
本申请涉及数据处理技术领域，具体涉及一种数据搬运方法、一种计算处理装置、一种计算处理设备、一种计算机可读存储介质。
背景技术
嵌入式技术发展迅速，但是嵌入式系统中的运算资源却比较稀缺。嵌入式系统中不仅对于CPU(Central Processing Unit，中央处理器)资源的利用越来越多，而且对于数据实时性的需求也越来越高。
在嵌入式系统针对数据搬运的处理方案中，大批量数据搬运一般不再使用CPU进行操作，而是使用DMA(Direct Memory Access，直接存储器存取)控制器进行数据搬运。
在嵌入式系统的数据搬运过程中，CPU配置好一段DMA数据后启动DMA搬运，DMA搬运成功后通常会产生中断给CPU，由CPU再次配置DMA数据进行下一次数据搬运。这样的方式带来的CPU开销较大，而且当中断比较频繁时CPU响应也很可能不及时，继而导致数据可能丢失。
发明内容
鉴于上述问题，提出了本申请以便提供一种克服上述问题或者至少部分地解决上述问题的数据搬运方法、计算处理装置、计算处理设备、计算机可读存储介质。
依据本申请的一个方面，提供了一种数据搬运方法，应用于外部设备，包括：
获取搬运配置信息，所述搬运配置信息包括目标搬运次数；
触发所述DMA控制器进行多次数据搬运；
确定所述DMA控制器的已完成搬运次数；
根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
依据本申请的另一个方面，提供了一种计算处理装置，用于实现数据搬运，所述计算处理装置包括外部设备、DMA控制器、处理器；
所述外部设备用于：获取搬运配置信息，所述搬运配置信息包括目标搬运次数；触发所述DMA控制器进行多次数据搬运；确定所述DMA控制器的已完成搬运次数；根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
依据本申请的另一个方面，提供了一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行上述的数据搬运方法。
依据本申请的另一个方面，提供了一种计算机可读介质，其中存储了如上所述的计算机程序。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本发明实施例一的一种数据搬运方法的步骤流程图；
图2示出了外部设备与DMA控制器之间握手的示意图；
图3示出了本发明实施例二的一种数据搬运方法的步骤流程图；
图4示出了数据搬运过程的示意图；
图5示意性地示出了用于执行根据本发明的方法的计算处理设备的框图；以及
图6示意性地示出了用于保持或者携带实现根据本发明的方法的程序代码的存储单元。
具体实施例
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施 例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
为使本领域技术人员更好地理解本发明，以下对本发明涉及的概念进行说明：
DMA控制器是一种在系统内部转移数据的外部设备，DMA控制器的作用是在处理器的编程控制下来执行传输，可以将其视为一种能够通过一组专用总线将内部和外部存储器与每个具有DMA能力的外部设备连接起来的控制器。
外部设备可以产生或获取数据，当外部设备产生或获取数据后，为了将数据搬移，通常会产生中断信号给处理器，由处理器将数据直接搬运走或者处理器配置DMA控制器来将数据搬运走。如果外部设备产生或获取数据比较频繁或者数据量比较大，可能出现处理器搬运不及时或者处理器配置DMA控制器不及时导致数据丢失的情况。
根据本发明的一种实施例，在数据搬运过程中，针对外部设备提供的数据输入是周期性的、或频繁的、或持续的数据，为了避免处理器响应不及时导致数据丢失的问题。本发明提供了一种数据搬运机制，应用于外部设备，通过获取搬运配置信息，触发DMA控制器进行多次数据搬运，确定DMA控制器的已完成搬运次数，根据已完成搬运次数达到了目标搬运次数，通知处理器数据搬运完成，使得数据搬运不再依赖处理器响应中断的方式，外部设备可以直接触发DMA控制器进行多次数据搬运，避免每次数据搬运都需等待处理器响应的问题，实现了持续不间断的数据搬运的目的，解决了处理器响应不及时导致数据丢失的问题。本发明适用但不局限于上述应用场景。
实施例1
参照图1，示出了本发明实施例一的一种数据搬运方法的步骤流程图，应用于外部设备，具体可以包括如下步骤：
步骤101，获取搬运配置信息，所述搬运配置信息包括目标搬运次数。
在本发明实施例中，在数据搬运过程中，为了避免每次数据搬运都需等待处理器响应，可以预先针对外部设备进行配置，得到搬运配置信息，其中包括配置数据搬运的次数，记为目标搬运次数。搬运配置信息可以根据外部 设备的特性以及实际需要进行配置，本发明实施例对此不做限制。
例如，软件预先针对带宽采集设备进行配置，得到搬运配置信息，将搬运配置信息发送给带宽采集设备。其中，根据带宽采集设备的特性，配置目标搬运次数为1024次。带宽采集设备可以设置专门的寄存器存储目标搬运次数。
步骤102，触发所述DMA控制器进行多次数据搬运。
在本发明实施例中，外部设备产生或获取数据后，不再产生中断给处理器，而是直接触发DMA控制器进行数据搬运，并且在完成每一次数据搬运后，DMA控制器不再产生中断给处理器，而是让DMA控制器等待外部设备触发下一次数据搬运，也就是说，由外部设备触发DMA控制器进行多次数据搬运，期间完成每次数据搬运不会通知处理器，也不会等待处理器的响应来配置下一次数据搬运。
可选地，触发所述DMA控制器进行多次数据搬运的一种实现方式可以包括：向DMA控制器发送每次数据搬运的请求信号；接收DMA控制器完成每次搬运的反馈信号。
例如，如图2所示的外部设备与DMA控制器之间握手的示意图，外部设备与DMA控制器之间通过硬件方式实现的握手信号进行同步，当外部设备有数据要搬运时，通过dma_req信号(即请求信号)直接发送给DMA控制器，DMA控制器根据搬运配置信息进行数据搬运，搬运完成后发送dma_ack信号(即反馈信号)给外部设备，外部设备接收到dma_ack信号之后才会产生下一次的dma_req信号，在完成目标搬运次数的数据搬运过程中，不再穿插软件处理，只有在目标搬运次数的数据搬运都完成之后，才会通知处理器。
步骤103，确定所述DMA控制器的已完成搬运次数。
在本发明实施例中，外部设备可以在每次完成数据搬运后，确定当前已经完成的搬运次数，记为已完成搬运次数。
可选地，确定所述DMA控制器的已完成搬运次数的一种实现方式可以包括：根据反馈信号，确定已完成搬运次数。外部设备每收到一次反馈信号，意味着完成了一次数据搬运，就可以将已完成搬运次数增加一次，即根据反馈信号进行计数，得到当前的已完成搬运次数。
例如，外部设备可以设置专门的寄存器存储已完成搬运次数，默认将该寄存器中的值置为0，每次收到反馈信号后，将此寄存器中的值进行加1，即可确定已完成搬运次数。
步骤104，根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
在本发明实施例中，当已完成搬运次数未达到目标搬运次数时，不必通知处理器，继续由外部设备触发DMA控制器进行数据搬运；当已完成搬运次数达到目标搬运次数时，通知处理器数据搬运完成，由处理器进行后续数据的处理。
依据本发明实施例，通过外部设备获取搬运配置信息，搬运配置信息包括目标搬运次数，触发DMA控制器进行多次数据搬运，确定DMA控制器的已完成搬运次数，根据已完成搬运次数达到了目标搬运次数，通知处理器数据搬运完成，使得数据搬运不再依赖处理器响应中断的方式，外部设备可以直接触发DMA控制器进行多次数据搬运，避免每次数据搬运都需等待处理器响应的问题，实现了持续不间断的数据搬运的目的，解决了处理器响应不及时导致数据丢失的问题。
实施例2
参照图3，示出了本发明实施例二的一种数据搬运方法的步骤流程图，应用于外部设备，具体可以包括如下步骤：
步骤201，获取搬运配置信息，所述搬运配置信息包括目标搬运次数。
步骤202，向DMA控制器发送每次数据搬运的请求信号。
步骤203，经所述DMA控制器搬运数据到至少两个缓存单元，其中，所述至少两个缓存单元中第一缓存单元写满数据后切换到第二缓存单元继续写入，所述第一缓存单元写满数据后通知处理器进行处理，以清空写满数据的第一缓存单元。
上述实施例中实现了持续不间断的进行数据搬运的目的，但当系统缓存比较少时，缓存的大小决定了目标搬运次数的上限，缓存被写满后，继续搬运会丢失数据，继而导致无法长时间获取外部设备的数据。
在本发明实施例中，为了长时间的获取外部设备的数据，可以采用至少 两个缓存单元作为数据搬运的缓存。外部设备的数据经过DMA控制器可以搬运到至少两个缓存单元。
其中，至少两个缓存单元中第一缓存单元写满数据后切换到第二缓存单元继续写入，并且第一缓存单元写满数据后通知处理器进行处理，以清空写满数据的第一缓存单元。依此规律，还可以有第三缓存单元、第四缓存单元等等，本发明实施例对此不做限制。处理器对第一缓存单元中数据的处理包括但不限于：通过处理器将第一缓存单元中的数据搬运至其他存储空间，或者由处理器将第一缓存单元中的数据提取走，并对数据进行设定的运算，本发明实施例对此不做限制。
缓存单元的切换可以由软件实现，也可以由硬件实现。其中软件实现的方式是，当一个缓存单元写满数据后，DMA控制器产生中断信号给处理器，由处理器触发下一个缓存单元的数据搬运，同时把已经写满数据的缓存单元中的数据进行处理，以便下一次继续可以使用该缓存单元，循环使用至少两个缓存单元，就可以一直有足够的缓存使用。
为了进一步降低数据丢失的风险，除了软件实现缓存单元切换的方式之外，还可以采用硬件切换的方式。
在一可选实施例中，采用硬件切换的方式下，搬运配置信息还包括每次搬运的数据量以及所述至少两个缓存单元的地址和长度，经所述DMA控制器搬运数据到至少两个缓存单元的一种实现方式可以包括：根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运。
外部设备获取的搬运配置信息不仅包括目标搬运次数，还可以包括每次搬运的数据量以及至少两个缓存单元的地址和长度。外部设备根据缓存单元的地址，就可以确定缓存单元在存储器中的空间位置，从而可以配置DMA控制器进行数据搬运的目的地址。外部设备根据缓存单元的长度、已完成搬运次数和每次搬运的数据量，就可以确定缓存单元是否写满数据，决定是否需要切换缓存单元。因此，外部设备就可以直接确定用于写入数据的缓存单元进行数据搬运，无需等待处理器响应中断配置DMA控制器，也就是说，由硬件实现缓存单元的自动切换，实现持续不间断的数据搬运，保证周期性的、或频繁的、或持续的数据不会丢失。
可选地，根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运的一种实现方式可以包括：根据第一缓存单元的长度、已完成搬运次数和每次搬运的数据量，确定第一缓存单元未写满数据，经DMA控制器搬运数据到第一缓存单元。
可选地，在数据搬运的过程中，软件可以主动停止数据搬运。其中一种实现方式可以包括：在根据第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定第一缓存单元未写满数据之后，接收数据搬运的结束请求；控制DMA控制器停止搬运数据到第一缓存单元。如果没有接收到数据搬运的结束请求，则继续进行数据搬运。
另外，对于已经搬运到第一缓存单元的数据，软件需要将第一缓存单元中的数据搬运走进行处理，这样才可以结束整个数据搬运过程。
可选地，根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运的一种实现方式可以包括：根据第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定第一缓存单元已写满数据，根据第二缓存单元的地址，经DMA控制器搬运数据到第二缓存单元。同时，通知处理器将第一缓存单元中的数据搬运走进行处理。
可选地，在通知处理器将第一缓存单元中的数据搬运走进行处理之后，决定是否停止数据搬运的另一种实现方式可以包括：由软件检查已完成搬运次数是否已经达到配置的目标搬运次数，若达到，则数据搬运过程结束，否则继续数据搬运到第二缓存单元。
例如，如图4所示的数据搬运过程的示意图，由软件配置双Buffer(即两个缓存单元)的地址、长度以及目标搬运次数。软件触发数据搬运过程后，外部设备通过与DMA控制器之间的硬件握手信号触发开始数据搬运。判断当前Buffer是否已经写满，若已经写满，则硬件产生中断信号给处理器，并自动切换到另外一个Buffer，软件收到中断后把当前Buffer中的数据搬运走。然后判断已完成搬运次数是否达到目标搬运次数，若达到目标搬运次数，则结束数据搬运过程，若未达到目标搬运次数，则继续进行数据搬运。若当前Buffer未写满，则判断软件是否触发了数据搬运的结束请求，若没有触发数 据搬运的结束请求，则继续进行数据搬运，若已经触发数据搬运的结束请求，则软件将当前Buffer中的数据搬运走，并结束整个数据搬运过程。
步骤204，接收所述DMA控制器完成每次搬运的反馈信号。
步骤205，根据所述反馈信号，确定所述已完成搬运次数。
步骤206，根据所述已完成搬运次数达到了所述目标搬运次数，控制所述DMA控制器产生中断信号发送给所述处理器。
依据本发明实施例，通过获取搬运配置信息，搬运配置信息包括目标搬运次数，向DMA控制器发送每次数据搬运的请求信号，经所述DMA控制器搬运数据到至少两个缓存单元，接收所述DMA控制器完成每次搬运的反馈信号，根据所述反馈信号，确定所述已完成搬运次数，根据所述已完成搬运次数达到了所述目标搬运次数，控制所述DMA控制器产生中断信号发送给所述处理器，使得数据搬运不再依赖处理器响应中断的方式，外部设备可以直接触发DMA控制器进行多次数据搬运，避免每次数据搬运都需等待处理器响应的问题，实现了持续不间断的数据搬运的目的，解决了处理器响应不及时导致数据丢失的问题。
进一步，通过至少两个缓存单元中第一缓存单元写满数据后切换到第二缓存单元继续写入，第一缓存单元写满数据后通知处理器进行处理，以清空写满数据的第一缓存单元，由硬件实现缓存单元的自动切换，实现持续不间断的数据搬运，保证周期性的、或频繁的、或持续的数据不会丢失。
实施例3
本发明实施例三提供了一种计算处理装置，用于实现数据搬运，所述计算处理装置包括外部设备、DMA控制器、处理器；所述外部设备用于：获取搬运配置信息，所述搬运配置信息包括目标搬运次数，触发所述DMA控制器进行多次数据搬运，确定所述DMA控制器的已完成搬运次数，根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
所述外部设备在触发所述DMA控制器进行多次数据搬运时具体用于：向DMA控制器发送每次数据搬运的请求信号；接收所述DMA控制器完成每次搬运的反馈信号。
所述外部设备在确定所述DMA控制器的已完成搬运次数时具体用于： 根据所述反馈信号，确定所述已完成搬运次数。
所述外部设备在触发所述DMA控制器进行多次数据搬运时具体用于：经所述DMA控制器搬运数据到至少两个缓存单元，其中，所述至少两个缓存单元中第一缓存单元写满数据后切换到第二缓存单元继续写入，所述第一缓存单元写满数据后通知处理器进行处理，以清空写满数据的第一缓存单元。
所述搬运配置信息还包括每次搬运的数据量以及所述至少两个缓存单元的地址和长度，所述外部设备在经所述DMA控制器搬运数据到至少两个缓存单元时具体用于：根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运。
所述外部设备在根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运时具体用于：根据所述第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元未写满数据；经所述DMA控制器搬运数据到所述第一缓存单元。
所述外部设备还用于：在根据所述第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元未写满数据之后，接收数据搬运的结束请求；控制所述DMA控制器停止搬运数据到所述第一缓存单元。
所述外部设备在根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运时具体用于：根据所述第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元已写满数据；根据所述第二缓存单元的地址，经所述DMA控制器搬运数据到所述第二缓存单元。
所述外部设备在通知处理器数据搬运完成时具体用于：控制所述DMA控制器产生中断信号发送给所述处理器。
依据本发明实施例，通过外部设备获取搬运配置信息，搬运配置信息包括目标搬运次数，触发DMA控制器进行多次数据搬运，确定DMA控制器的已完成搬运次数，根据已完成搬运次数达到了目标搬运次数，通知处理器 数据搬运完成，使得数据搬运不再依赖处理器响应中断的方式，外部设备可以直接触发DMA控制器进行多次数据搬运，避免每次数据搬运都需等待处理器响应的问题，实现了持续不间断的数据搬运的目的，解决了处理器响应不及时导致数据丢失的问题。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本发明的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本发明实施例的计算处理设备中的一些或者全部部件的一些或者全部功能。本发明还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本发明的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图5示出了可以实现根据本发明的方法的计算处理设备。该计算处理设备传统上包括处理器1010和以存储器1020形式的计算机程序产品或者计算机可读介质。存储器1020可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器1020具有用于执行上述方法中的任何方法步骤的程序代码1031的存储空间1030。例如，用于程序代码的存储空间1030可以包括分别用于实现上面的方法中的各种步骤的各个程序代码1031。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图6所述的便携式或者固定存储单元。该存储单元可以具有与图5的计算处理设备中的存储器1020 类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码1031’，即可以由例如诸如1010之类的处理器读取的代码，这些代码当由计算处理设备运行时，导致该计算处理设备执行上面所描述的方法中的各个步骤。
本文中所称的“一个实施例”、“实施例”或者“一个或者多个实施例”意味着，结合实施例描述的特定特征、结构或者特性包括在本发明的至少一个实施例中。此外，请注意，这里“在一个实施例中”的词语例子不一定全指同一个实施例。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (12)

  1. 一种数据搬运方法，其特征在于，应用于外部设备，包括：
    获取搬运配置信息，所述搬运配置信息包括目标搬运次数；
    触发所述DMA控制器进行多次数据搬运；
    确定所述DMA控制器的已完成搬运次数；
    根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
  2. 根据权利要求1所述的方法，其特征在于，所述触发所述DMA控制器进行多次数据搬运包括：
    向所述DMA控制器发送每次数据搬运的请求信号；
    接收所述DMA控制器完成每次搬运的反馈信号。
  3. 根据权利要求2所述的方法，其特征在于，所述确定所述DMA控制器的已完成搬运次数包括：
    根据所述反馈信号，确定所述已完成搬运次数。
  4. 根据权利要求1所述的方法，其特征在于，所述触发所述DMA控制器进行多次数据搬运包括：
    经所述DMA控制器搬运数据到至少两个缓存单元，其中，所述至少两个缓存单元中第一缓存单元写满数据后切换到第二缓存单元继续写入，所述第一缓存单元写满数据后通知处理器进行处理，以清空写满数据的第一缓存单元。
  5. 根据权利要求4所述的方法，其特征在于，所述搬运配置信息还包括每次搬运的数据量以及所述至少两个缓存单元的地址和长度，所述经所述DMA控制器搬运数据到至少两个缓存单元包括：
    根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运。
  6. 根据权利要求5所述的方法，其特征在于，所述根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运包括：
    根据所述第一缓存单元的长度、已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元未写满数据；
    经所述DMA控制器搬运数据到所述第一缓存单元。
  7. 根据权利要求6所述的方法，其特征在于，在所述根据所述第一缓存单元的长度、已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元未写满数据之后，所述方法还包括：
    接收数据搬运的结束请求；
    控制所述DMA控制器停止搬运数据到所述第一缓存单元。
  8. 根据权利要求5所述的方法，其特征在于，所述根据所述已完成搬运次数、每次搬运的数据量以及所述至少两个缓存单元的地址和长度，确定用于写入数据的缓存单元进行数据搬运包括：
    根据所述第一缓存单元的长度、所述已完成搬运次数和每次搬运的数据量，确定所述第一缓存单元已写满数据；
    根据所述第二缓存单元的地址，经所述DMA控制器搬运数据到所述第二缓存单元。
  9. 根据权利要求1所述的方法，其特征在于，所述通知处理器数据搬运完成包括：
    控制所述DMA控制器产生中断信号发送给所述处理器。
  10. 一种计算处理装置，用于实现数据搬运，其特征在于，所述计算处理装置包括外部设备、DMA控制器、处理器；
    所述外部设备用于：获取搬运配置信息，所述搬运配置信息包括目标搬运次数；触发所述DMA控制器进行多次数据搬运；确定所述DMA控制器的已完成搬运次数；根据所述已完成搬运次数达到了所述目标搬运次数，通知处理器数据搬运完成。
  11. 一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据权利要求1-9中的任一个所述的数据搬运方法。
  12. 一种计算机可读介质，其中存储了如权利要求11所述的计算机程序。
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