BR9508906A - Processo e aparelho para executar transações diferidas - Google Patents

Processo e aparelho para executar transações diferidas

Info

Publication number
BR9508906A
BR9508906A BR9508906A BR9508906A BR9508906A BR 9508906 A BR9508906 A BR 9508906A BR 9508906 A BR9508906 A BR 9508906A BR 9508906 A BR9508906 A BR 9508906A BR 9508906 A BR9508906 A BR 9508906A
Authority
BR
Brazil
Prior art keywords
deferred transactions
executing deferred
executing
transactions
deferred
Prior art date
Application number
BR9508906A
Other languages
English (en)
Other versions
BR9508906C1 (pt
Inventor
Nitin V Sarangdhar
Konrad K Lai
Gurbir Singh
Peter D Macwilliams
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=23168453&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=BR9508906(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR9508906A publication Critical patent/BR9508906A/pt
Publication of BR9508906C1 publication Critical patent/BR9508906C1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
BR9508906-3A 1994-09-08 1995-09-08 Sistema de computador, processo para executar transações e operações de barramento, agente de barramento e aparelho BR9508906C1 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/302,600 US5615343A (en) 1993-06-30 1994-09-08 Method and apparatus for performing deferred transactions
PCT/US1995/011315 WO1996007970A1 (en) 1994-09-08 1995-09-08 Method and apparatus for performing deferred transactions

Publications (2)

Publication Number Publication Date
BR9508906A true BR9508906A (pt) 1997-10-28
BR9508906C1 BR9508906C1 (pt) 2004-10-19

Family

ID=23168453

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9508906-3A BR9508906C1 (pt) 1994-09-08 1995-09-08 Sistema de computador, processo para executar transações e operações de barramento, agente de barramento e aparelho

Country Status (7)

Country Link
US (4) US5615343A (pt)
JP (2) JP3771260B2 (pt)
KR (1) KR100253753B1 (pt)
AU (1) AU3506295A (pt)
BR (1) BR9508906C1 (pt)
DE (1) DE19580990C2 (pt)
WO (1) WO1996007970A1 (pt)

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5615343A (en) * 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
USRE38428E1 (en) 1995-05-02 2004-02-10 Apple Computer, Inc. Bus transaction reordering in a computer system having unordered slaves
US6108735A (en) * 1995-09-29 2000-08-22 Intel Corporation Method and apparatus for responding to unclaimed bus transactions
US5802055A (en) * 1996-04-22 1998-09-01 Apple Computer, Inc. Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads
KR100280285B1 (ko) 1996-08-19 2001-02-01 윤종용 멀티미디어 신호에 적합한 멀티미디어 프로세서
US5923857A (en) * 1996-09-06 1999-07-13 Intel Corporation Method and apparatus for ordering writeback data transfers on a bus
US5878235A (en) * 1996-10-03 1999-03-02 Micron Electronics, Inc. Method and system for concurrent computer transaction processing
US6173349B1 (en) * 1996-10-18 2001-01-09 Samsung Electronics Co., Ltd. Shared bus system with transaction and destination ID
US6012118A (en) * 1996-12-30 2000-01-04 Intel Corporation Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
US5930485A (en) * 1997-01-07 1999-07-27 Apple Computer, Inc. Deadlock avoidance in a computer system having unordered slaves
DE19712799A1 (de) 1997-03-26 1998-10-01 Siemens Nixdorf Inf Syst Abhängigkeitssteuerung für überlappende Speicherzugriffe
US6128677A (en) * 1997-10-15 2000-10-03 Intel Corporation System and method for improved transfer of data between multiple processors and I/O bridges
US6260091B1 (en) * 1997-10-20 2001-07-10 Intel Corporation Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply
US6145038A (en) * 1997-10-31 2000-11-07 International Business Machines Corporation Method and system for early slave forwarding of strictly ordered bus operations
US6112270A (en) * 1997-10-31 2000-08-29 International Business Machines Corporation Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6032178A (en) * 1998-01-12 2000-02-29 Siemens Aktiengesellschaft Method and arrangement for data transmission between units on a bus system selectively transmitting data in one of a first and a second data transmission configurations
US6195722B1 (en) * 1998-01-26 2001-02-27 Intel Corporation Method and apparatus for deferring transactions on a host bus having a third party agent
US6223238B1 (en) 1998-03-31 2001-04-24 Micron Electronics, Inc. Method of peer-to-peer mastering over a computer bus
US6073198A (en) * 1998-03-31 2000-06-06 Micron Electronics, Inc. System for peer-to-peer mastering over a computer bus
US6202101B1 (en) * 1998-09-30 2001-03-13 Compaq Computer Corporation System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom
TW523672B (en) * 1999-04-23 2003-03-11 Via Tech Inc Bus system delayed transaction method and device applying the method
US6609171B1 (en) 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
US6813767B1 (en) * 2000-06-30 2004-11-02 Intel Corporation Prioritizing transaction requests with a delayed transaction reservation buffer
US6450882B1 (en) * 2000-08-30 2002-09-17 Liberty Diversified Industries, Inc. Precipitation resistant ridge vent
US6993663B1 (en) * 2000-08-31 2006-01-31 Microsoft Corporation Input buffer overrun checking and prevention
US20020087766A1 (en) * 2000-12-29 2002-07-04 Akhilesh Kumar Method and apparatus to implement a locked-bus transaction
US6742160B2 (en) 2001-02-14 2004-05-25 Intel Corporation Checkerboard parity techniques for a multi-pumped bus
US6968409B1 (en) * 2001-08-29 2005-11-22 Lsi Logic Corporation Method and apparatus of establishing a dynamically adjustable loop of delayed read commands for completion in a queue buffer
US6961800B2 (en) * 2001-09-28 2005-11-01 Hewlett-Packard Development Company, L.P. Method for improving processor performance
US6807593B1 (en) * 2001-11-01 2004-10-19 Lsi Logic Corporation Enhanced bus architecture for posted read operation between masters and slaves
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US7085889B2 (en) * 2002-03-22 2006-08-01 Intel Corporation Use of a context identifier in a cache memory
TWI282513B (en) * 2002-06-12 2007-06-11 Mediatek Inc A pre-fetch device of instruction for an embedded system
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7254658B2 (en) * 2004-06-08 2007-08-07 Arm Limited Write transaction interleaving
US7779188B2 (en) * 2005-03-22 2010-08-17 Intel Corporation System and method to reduce memory latency in microprocessor systems connected with a bus
US7373462B2 (en) 2005-03-29 2008-05-13 International Business Machines Corporation Snoop filter for filtering snoop requests
US7386683B2 (en) * 2005-03-29 2008-06-10 International Business Machines Corporation Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture
US20070067567A1 (en) * 2005-09-19 2007-03-22 Via Technologies, Inc. Merging entries in processor caches
US20080282034A1 (en) * 2005-09-19 2008-11-13 Via Technologies, Inc. Memory Subsystem having a Multipurpose Cache for a Stream Graphics Multiprocessor
JP4297969B2 (ja) * 2006-02-24 2009-07-15 富士通株式会社 記録制御装置および記録制御方法
WO2007097029A1 (ja) * 2006-02-27 2007-08-30 Fujitsu Limited プロセッサ装置および命令処理方法
US8386822B2 (en) * 2008-02-01 2013-02-26 International Business Machines Corporation Wake-and-go mechanism with data monitoring
US8725992B2 (en) 2008-02-01 2014-05-13 International Business Machines Corporation Programming language exposing idiom calls to a programming idiom accelerator
US8312458B2 (en) 2008-02-01 2012-11-13 International Business Machines Corporation Central repository for wake-and-go mechanism
US8250396B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Hardware wake-and-go mechanism for a data processing system
US8225120B2 (en) 2008-02-01 2012-07-17 International Business Machines Corporation Wake-and-go mechanism with data exclusivity
US8788795B2 (en) * 2008-02-01 2014-07-22 International Business Machines Corporation Programming idiom accelerator to examine pre-fetched instruction streams for multiple processors
US8145849B2 (en) * 2008-02-01 2012-03-27 International Business Machines Corporation Wake-and-go mechanism with system bus response
US8015379B2 (en) * 2008-02-01 2011-09-06 International Business Machines Corporation Wake-and-go mechanism with exclusive system bus response
US8171476B2 (en) 2008-02-01 2012-05-01 International Business Machines Corporation Wake-and-go mechanism with prioritization of threads
US8732683B2 (en) 2008-02-01 2014-05-20 International Business Machines Corporation Compiler providing idiom to idiom accelerator
US8612977B2 (en) * 2008-02-01 2013-12-17 International Business Machines Corporation Wake-and-go mechanism with software save of thread state
US8880853B2 (en) 2008-02-01 2014-11-04 International Business Machines Corporation CAM-based wake-and-go snooping engine for waking a thread put to sleep for spinning on a target address lock
US8316218B2 (en) * 2008-02-01 2012-11-20 International Business Machines Corporation Look-ahead wake-and-go engine with speculative execution
US8516484B2 (en) 2008-02-01 2013-08-20 International Business Machines Corporation Wake-and-go mechanism for a data processing system
US8341635B2 (en) 2008-02-01 2012-12-25 International Business Machines Corporation Hardware wake-and-go mechanism with look-ahead polling
US8127080B2 (en) 2008-02-01 2012-02-28 International Business Machines Corporation Wake-and-go mechanism with system address bus transaction master
US8452947B2 (en) * 2008-02-01 2013-05-28 International Business Machines Corporation Hardware wake-and-go mechanism and content addressable memory with instruction pre-fetch look-ahead to detect programming idioms
US8640141B2 (en) * 2008-02-01 2014-01-28 International Business Machines Corporation Wake-and-go mechanism with hardware private array
US20090235083A1 (en) * 2008-02-20 2009-09-17 Micheal Bleahen System and method for preventing unauthorized access to information
US9443068B2 (en) 2008-02-20 2016-09-13 Micheal Bleahen System and method for preventing unauthorized access to information
US8145805B2 (en) * 2008-06-09 2012-03-27 Emulex Design & Manufacturing Corporation Method for re-sequencing commands and data between a master and target devices utilizing parallel processing
US8230201B2 (en) * 2009-04-16 2012-07-24 International Business Machines Corporation Migrating sleeping and waking threads between wake-and-go mechanisms in a multiple processor data processing system
US8145723B2 (en) * 2009-04-16 2012-03-27 International Business Machines Corporation Complex remote update programming idiom accelerator
US8082315B2 (en) * 2009-04-16 2011-12-20 International Business Machines Corporation Programming idiom accelerator for remote update
US8886919B2 (en) 2009-04-16 2014-11-11 International Business Machines Corporation Remote update programming idiom accelerator with allocated processor resources
US9104581B2 (en) * 2010-06-24 2015-08-11 International Business Machines Corporation eDRAM refresh in a high performance cache architecture
WO2013070217A1 (en) * 2011-11-09 2013-05-16 Intel Corporation Method and apparatus for an agent interfacing with a pipelined backbone to locally handle transactions while obeying an ordering rule
WO2013095387A1 (en) 2011-12-20 2013-06-27 Intel Corporation Secure replay protected storage
US9411748B2 (en) 2011-12-20 2016-08-09 Intel Corporation Secure replay protected storage
US9122508B2 (en) 2012-06-15 2015-09-01 International Business Machines Corporation Real time measurement of I/O interrupt delay times by hypervisor by selectively starting and/or stopping corresponding LPARs

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4181974A (en) * 1978-01-05 1980-01-01 Honeywell Information Systems, Inc. System providing multiple outstanding information requests
YU40357B (en) * 1978-01-05 1985-12-31 Honeywell Inf Systems System facilitating a higher number of contemporary information claims
US4488232A (en) * 1981-10-02 1984-12-11 Hughes Aircraft Company Self-adjusting, distributed control, access method for a multiplexed single-signal data bus
US4481625A (en) 1981-10-21 1984-11-06 Elxsi High speed data bus system
JPH0632056B2 (ja) * 1985-05-31 1994-04-27 松下電器産業株式会社 デ−タ処理装置
US4807118A (en) * 1987-01-14 1989-02-21 Hewlett-Packard Company Method for handling slot requests over a network
US5235684A (en) * 1988-06-30 1993-08-10 Wang Laboratories, Inc. System bus having multiplexed command/id and data
US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
US5197137A (en) * 1989-07-28 1993-03-23 International Business Machines Corporation Computer architecture for the concurrent execution of sequential programs
US5555425A (en) * 1990-03-07 1996-09-10 Dell Usa, L.P. Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters
JP3524110B2 (ja) * 1992-11-06 2004-05-10 株式会社ルネサステクノロジ マイクロコンピュータシステム
US5528764A (en) 1992-12-24 1996-06-18 Ncr Corporation Bus system with cache snooping signals having a turnaround time between agents driving the bus for keeping the bus from floating for an extended period
US5615343A (en) * 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
US5568620A (en) 1993-06-30 1996-10-22 Intel Corporation Method and apparatus for performing bus transactions in a computer system
US5551005A (en) 1994-02-25 1996-08-27 Intel Corporation Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches
KR100360064B1 (ko) 1994-03-01 2003-03-10 인텔 코오퍼레이션 고도로파이프라인된버스구조
US5535340A (en) 1994-05-20 1996-07-09 Intel Corporation Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
US5758106A (en) * 1994-06-30 1998-05-26 Digital Equipment Corporation Arbitration unit which requests control of the system bus prior to determining whether such control is required
US5699516A (en) * 1994-12-22 1997-12-16 Motorola, Inc. Method and apparatus for implementing a in-order termination bus protocol within a data processing system
US5696910A (en) * 1995-09-26 1997-12-09 Intel Corporation Method and apparatus for tracking transactions in a pipelined bus

Also Published As

Publication number Publication date
KR100253753B1 (ko) 2000-04-15
DE19580990T1 (de) 1997-08-21
KR970705792A (ko) 1997-10-09
DE19580990C2 (de) 1999-11-11
US5937171A (en) 1999-08-10
JPH10505184A (ja) 1998-05-19
US5615343A (en) 1997-03-25
AU3506295A (en) 1996-03-27
USRE38388E1 (en) 2004-01-13
JP2006092575A (ja) 2006-04-06
JP3771260B2 (ja) 2006-04-26
JP4157127B2 (ja) 2008-09-24
BR9508906C1 (pt) 2004-10-19
WO1996007970A1 (en) 1996-03-14
US6405271B1 (en) 2002-06-11

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