BR9506745A - Processo para determinar e dispositivo para assegurar que informação digital armazenada numa memória seja corretamente legível - Google Patents

Processo para determinar e dispositivo para assegurar que informação digital armazenada numa memória seja corretamente legível

Info

Publication number
BR9506745A
BR9506745A BR9506745A BR9506745A BR9506745A BR 9506745 A BR9506745 A BR 9506745A BR 9506745 A BR9506745 A BR 9506745A BR 9506745 A BR9506745 A BR 9506745A BR 9506745 A BR9506745 A BR 9506745A
Authority
BR
Brazil
Prior art keywords
ensuring
memory
determining
information stored
digital information
Prior art date
Application number
BR9506745A
Other languages
English (en)
Inventor
Leif Mikael Larsson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR9506745A publication Critical patent/BR9506745A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/104—Asynchronous transfer mode [ATM] switching fabrics
    • H04L49/105—ATM switching elements
    • H04L49/108—ATM switching elements using shared central buffer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/55—Prevention, detection or correction of errors
    • H04L49/555—Error detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/103—Packet switching elements characterised by the switching fabric construction using a shared central buffer; using a shared memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3009—Header conversion, routing tables or routing tags

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Detection And Correction Of Errors (AREA)
BR9506745A 1994-02-10 1995-02-02 Processo para determinar e dispositivo para assegurar que informação digital armazenada numa memória seja corretamente legível BR9506745A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9400435A SE503589C2 (sv) 1994-02-10 1994-02-10 Förfarande och anordning för övervakning av ett minne
PCT/SE1995/000103 WO1995022109A1 (en) 1994-02-10 1995-02-02 Method and device to control a memory

Publications (1)

Publication Number Publication Date
BR9506745A true BR9506745A (pt) 1997-09-16

Family

ID=20392871

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9506745A BR9506745A (pt) 1994-02-10 1995-02-02 Processo para determinar e dispositivo para assegurar que informação digital armazenada numa memória seja corretamente legível

Country Status (14)

Country Link
US (2) US5644708A (pt)
EP (1) EP0744052B1 (pt)
JP (1) JP2989668B2 (pt)
KR (1) KR100306196B1 (pt)
CN (1) CN1140496A (pt)
AU (1) AU677510B2 (pt)
BR (1) BR9506745A (pt)
DE (1) DE69527280D1 (pt)
FI (1) FI963119A (pt)
MX (1) MX9601051A (pt)
NO (1) NO963297L (pt)
SE (1) SE503589C2 (pt)
TW (1) TW299537B (pt)
WO (1) WO1995022109A1 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374376B1 (en) * 1998-09-03 2002-04-16 Micron Technology, Inc. Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test
JP2002288041A (ja) * 2001-03-23 2002-10-04 Sony Corp 情報処理装置および方法、プログラム格納媒体、並びにプログラム

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914741A (en) * 1973-11-01 1975-10-21 Bell Telephone Labor Inc Fault detection arrangement for digital transmission system
US4020459A (en) * 1975-10-28 1977-04-26 Bell Telephone Laboratories, Incorporated Parity generation and bus matching arrangement for synchronized duplicated data processing units
US4019033A (en) * 1975-12-29 1977-04-19 Honeywell Information Systems, Inc. Control store checking system and method
MX4130E (es) * 1977-05-20 1982-01-04 Amdahl Corp Mejoras en sistema de procesamiento de datos y escrutinio de informacion utilizando sumas de comprobacion
US4271521A (en) * 1979-07-09 1981-06-02 The Anaconda Company Address parity check system
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
NL8600217A (nl) * 1986-01-30 1987-08-17 Philips Nv Dataverwerkende inrichting bevattende een geheugeninrichting voorzien van een coincidentieschakeling die in een foutherkennings- en een coincidentiemode schakelbaar is.
US4809278A (en) * 1986-04-21 1989-02-28 Unisys Corporation Specialized parity detection system for wide memory structure
DE69019822T2 (de) * 1990-06-27 1995-12-14 Ibm Verfahren und Vorrichtung zur Prüfung des Inhalts und der Adresse einer Speicheranordnung.
JPH04141900A (ja) * 1990-10-01 1992-05-15 Nec Ic Microcomput Syst Ltd 半導体集積回路
US5392302A (en) * 1991-03-13 1995-02-21 Quantum Corp. Address error detection technique for increasing the reliability of a storage subsystem
EP0544964B1 (en) * 1991-11-29 1997-02-19 International Business Machines Corporation Store and forward apparatus and method of maintaining integrity of data during storage
SE470002B (sv) * 1992-03-13 1993-10-18 Ellemtel Utvecklings Ab Förfarande för att förhindra att det på någon av ett antal kanaler på en gemensam överföringsledning sänds datapaket med högre intensitet än ett för kanalen förutbestämt värde samt anordning för utövande av sättet
US5537425A (en) * 1992-09-29 1996-07-16 International Business Machines Corporation Parity-based error detection in a memory controller
SE470544B (sv) * 1992-11-24 1994-07-25 Ellemtel Utvecklings Ab För en bitfelsövervakning i en väljarutrustning avsedd anordning
US5477553A (en) * 1994-07-22 1995-12-19 Professional Computer Systems, Inc. Compressed memory address parity checking apparatus and method

Also Published As

Publication number Publication date
KR970701390A (ko) 1997-03-17
TW299537B (pt) 1997-03-01
DE69527280D1 (de) 2002-08-08
SE503589C2 (sv) 1996-07-15
FI963119A0 (fi) 1996-08-08
SE9400435L (sv) 1995-08-11
AU1826695A (en) 1995-08-29
EP0744052B1 (en) 2002-07-03
WO1995022109A1 (en) 1995-08-17
KR100306196B1 (ko) 2001-11-30
FI963119A (fi) 1996-08-08
AU677510B2 (en) 1997-04-24
MX9601051A (es) 1997-06-28
JPH09500471A (ja) 1997-01-14
CN1140496A (zh) 1997-01-15
US5644708A (en) 1997-07-01
NO963297D0 (no) 1996-08-07
JP2989668B2 (ja) 1999-12-13
EP0744052A1 (en) 1996-11-27
US5996093A (en) 1999-11-30
SE9400435D0 (sv) 1994-02-10
NO963297L (no) 1996-10-08

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Legal Events

Date Code Title Description
FD5 Application fees: dismissal - article 86 of industrial property law