BR9502022A - Sistema de computador que inclui uma unidade de processamento de acesso paralelo à memória cache externa e memória e método para transferir informações entre eles - Google Patents
Sistema de computador que inclui uma unidade de processamento de acesso paralelo à memória cache externa e memória e método para transferir informações entre elesInfo
- Publication number
- BR9502022A BR9502022A BR9502022A BR9502022A BR9502022A BR 9502022 A BR9502022 A BR 9502022A BR 9502022 A BR9502022 A BR 9502022A BR 9502022 A BR9502022 A BR 9502022A BR 9502022 A BR9502022 A BR 9502022A
- Authority
- BR
- Brazil
- Prior art keywords
- memory
- processing unit
- computer system
- transferring information
- external cache
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/245,786 US6226722B1 (en) | 1994-05-19 | 1994-05-19 | Integrated level two cache and controller with multiple ports, L1 bypass and concurrent accessing |
Publications (1)
Publication Number | Publication Date |
---|---|
BR9502022A true BR9502022A (pt) | 1996-01-30 |
Family
ID=22928068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR9502022A BR9502022A (pt) | 1994-05-19 | 1995-05-11 | Sistema de computador que inclui uma unidade de processamento de acesso paralelo à memória cache externa e memória e método para transferir informações entre eles |
Country Status (11)
Country | Link |
---|---|
US (1) | US6226722B1 (pt) |
EP (1) | EP0760133A1 (pt) |
JP (1) | JPH07319767A (pt) |
KR (1) | KR950033837A (pt) |
CN (1) | CN1089462C (pt) |
BR (1) | BR9502022A (pt) |
CA (1) | CA2142799A1 (pt) |
CZ (1) | CZ9603197A3 (pt) |
HU (1) | HUT76241A (pt) |
PL (1) | PL176554B1 (pt) |
WO (1) | WO1995032472A1 (pt) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000181796A (ja) * | 1998-12-14 | 2000-06-30 | Nec Corp | 情報処理装置 |
US6578110B1 (en) * | 1999-01-21 | 2003-06-10 | Sony Computer Entertainment, Inc. | High-speed processor system and cache memories with processing capabilities |
US6484237B1 (en) * | 1999-07-15 | 2002-11-19 | Texas Instruments Incorporated | Unified multilevel memory system architecture which supports both cache and addressable SRAM |
US6625707B2 (en) * | 2001-06-25 | 2003-09-23 | Intel Corporation | Speculative memory command preparation for low latency |
US6919592B2 (en) * | 2001-07-25 | 2005-07-19 | Nantero, Inc. | Electromechanical memory array using nanotube ribbons and method for making same |
US6643165B2 (en) * | 2001-07-25 | 2003-11-04 | Nantero, Inc. | Electromechanical memory having cell selection circuitry constructed with nanotube technology |
US7566478B2 (en) * | 2001-07-25 | 2009-07-28 | Nantero, Inc. | Methods of making carbon nanotube films, layers, fabrics, ribbons, elements and articles |
US6574130B2 (en) * | 2001-07-25 | 2003-06-03 | Nantero, Inc. | Hybrid circuit having nanotube electromechanical memory |
US6835591B2 (en) * | 2001-07-25 | 2004-12-28 | Nantero, Inc. | Methods of nanotube films and articles |
US6706402B2 (en) | 2001-07-25 | 2004-03-16 | Nantero, Inc. | Nanotube films and articles |
US6789169B2 (en) * | 2001-10-04 | 2004-09-07 | Micron Technology, Inc. | Embedded DRAM cache memory and method having reduced latency |
US6784028B2 (en) * | 2001-12-28 | 2004-08-31 | Nantero, Inc. | Methods of making electromechanical three-trace junction devices |
US7176505B2 (en) * | 2001-12-28 | 2007-02-13 | Nantero, Inc. | Electromechanical three-trace junction devices |
KR100541366B1 (ko) * | 2002-07-19 | 2006-01-16 | 주식회사 하이닉스반도체 | 고속 데이터 억세스를 위한 디램 |
US6892281B2 (en) * | 2002-10-03 | 2005-05-10 | Intel Corporation | Apparatus, method, and system for reducing latency of memory devices |
US7467377B2 (en) * | 2002-10-22 | 2008-12-16 | Intel Corporation | Methods and apparatus for compiler managed first cache bypassing |
US6941421B2 (en) * | 2002-10-29 | 2005-09-06 | International Business Machines Corporation | Zero delay data cache effective address generation |
US20040221117A1 (en) * | 2003-05-02 | 2004-11-04 | Shelor Charles F. | Logic and method for reading data from cache |
US20060248287A1 (en) * | 2005-04-29 | 2006-11-02 | Ibm Corporation | Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures |
US7562190B1 (en) | 2005-06-17 | 2009-07-14 | Sun Microsystems, Inc. | Cache protocol enhancements in a proximity communication-based off-chip cache memory architecture |
US7444473B1 (en) * | 2005-06-17 | 2008-10-28 | Sun Microsystems, Inc. | Speculative memory accesses in a proximity communication-based off-chip cache memory architecture |
US7496712B1 (en) | 2005-06-17 | 2009-02-24 | Sun Microsystems, Inc. | Proximity communication-based off-chip cache memory architectures |
US20070130114A1 (en) * | 2005-06-20 | 2007-06-07 | Xiao-Feng Li | Methods and apparatus to optimize processing throughput of data structures in programs |
US7596661B2 (en) * | 2005-09-01 | 2009-09-29 | Mediatek Inc. | Processing modules with multilevel cache architecture |
US8055847B2 (en) * | 2008-07-07 | 2011-11-08 | International Business Machines Corporation | Efficient processing of data requests with the aid of a region cache |
JP5118731B2 (ja) | 2010-08-12 | 2013-01-16 | 株式会社東芝 | キャッシュユニット及びプロセッシングシステム |
US10474584B2 (en) * | 2012-04-30 | 2019-11-12 | Hewlett Packard Enterprise Development Lp | Storing cache metadata separately from integrated circuit containing cache controller |
US9405687B2 (en) * | 2013-11-04 | 2016-08-02 | Intel Corporation | Method, apparatus and system for handling cache misses in a processor |
KR102161689B1 (ko) * | 2013-12-10 | 2020-10-05 | 삼성전자 주식회사 | L2 캐시 특성을 조절할 수 있는 멀티-코어 cpu 시스템, 이의 동작 방법, 및 이를 포함하는 장치들 |
CN105701040B (zh) * | 2014-11-28 | 2018-12-07 | 杭州华为数字技术有限公司 | 一种激活内存的方法及装置 |
US9658963B2 (en) | 2014-12-23 | 2017-05-23 | Intel Corporation | Speculative reads in buffered memory |
JP6367704B2 (ja) * | 2014-12-25 | 2018-08-01 | 株式会社バイオス | 記憶制御システム及び記憶制御装置 |
JP6478843B2 (ja) * | 2015-07-07 | 2019-03-06 | ルネサスエレクトロニクス株式会社 | 半導体装置及びキャッシュメモリ制御方法 |
US11055221B2 (en) * | 2019-03-22 | 2021-07-06 | Samsung Electronics Co., Ltd. | Speculative DRAM read, in parallel with cache level search, leveraging interconnect directory |
US11288067B2 (en) * | 2019-05-24 | 2022-03-29 | Texas Instruments Incorporated | Vector reverse |
US11422947B2 (en) * | 2020-08-12 | 2022-08-23 | International Business Machines Corporation | Determining page size via page table cache |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3896419A (en) * | 1974-01-17 | 1975-07-22 | Honeywell Inf Systems | Cache memory store in a processor of a data processing system |
US4161024A (en) | 1977-12-22 | 1979-07-10 | Honeywell Information Systems Inc. | Private cache-to-CPU interface in a bus oriented data processing system |
US4823259A (en) * | 1984-06-29 | 1989-04-18 | International Business Machines Corporation | High speed buffer store arrangement for quick wide transfer of data |
US4797814A (en) * | 1986-05-01 | 1989-01-10 | International Business Machines Corporation | Variable address mode cache |
US5202972A (en) * | 1988-12-29 | 1993-04-13 | International Business Machines Corporation | Store buffer apparatus in a multiprocessor system |
US5155828A (en) * | 1989-07-05 | 1992-10-13 | Hewlett-Packard Company | Computing system with a cache memory and an additional look-aside cache memory |
US5214765A (en) * | 1989-08-31 | 1993-05-25 | Sun Microsystems, Inc. | Method and apparatus for executing floating point instructions utilizing complimentary floating point pipeline and multi-level caches |
US5261066A (en) * | 1990-03-27 | 1993-11-09 | Digital Equipment Corporation | Data processing system and method with small fully-associative cache and prefetch buffers |
US5210845A (en) * | 1990-11-28 | 1993-05-11 | Intel Corporation | Controller for two-way set associative cache |
US5345576A (en) * | 1991-12-31 | 1994-09-06 | Intel Corporation | Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss |
-
1994
- 1994-05-19 US US08/245,786 patent/US6226722B1/en not_active Expired - Fee Related
- 1994-12-27 WO PCT/EP1994/004315 patent/WO1995032472A1/en not_active Application Discontinuation
- 1994-12-27 HU HU9603142A patent/HUT76241A/hu unknown
- 1994-12-27 EP EP95905594A patent/EP0760133A1/en not_active Withdrawn
- 1994-12-27 PL PL94316998A patent/PL176554B1/pl not_active IP Right Cessation
- 1994-12-27 CZ CZ19963197A patent/CZ9603197A3/cs unknown
-
1995
- 1995-02-17 CA CA002142799A patent/CA2142799A1/en not_active Abandoned
- 1995-05-09 CN CN95106102A patent/CN1089462C/zh not_active Expired - Fee Related
- 1995-05-10 JP JP7111435A patent/JPH07319767A/ja active Pending
- 1995-05-11 BR BR9502022A patent/BR9502022A/pt not_active Application Discontinuation
- 1995-05-18 KR KR1019950012401A patent/KR950033837A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
CZ9603197A3 (cs) | 2002-06-12 |
WO1995032472A1 (en) | 1995-11-30 |
CA2142799A1 (en) | 1995-11-20 |
CN1123933A (zh) | 1996-06-05 |
CN1089462C (zh) | 2002-08-21 |
PL316998A1 (en) | 1997-03-03 |
US6226722B1 (en) | 2001-05-01 |
EP0760133A1 (en) | 1997-03-05 |
HU9603142D0 (en) | 1997-01-28 |
HUT76241A (en) | 1997-07-28 |
KR950033837A (ko) | 1995-12-26 |
PL176554B1 (pl) | 1999-06-30 |
JPH07319767A (ja) | 1995-12-08 |
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Legal Events
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FA10 | Dismissal: dismissal - article 33 of industrial property law |