BR9405567A - Gerador de sequência de bits pseudo-rand6omicos, dispositivo de comunicação e processo para gerar sequência de bits pseudo-randÈmicos. - Google Patents

Gerador de sequência de bits pseudo-rand6omicos, dispositivo de comunicação e processo para gerar sequência de bits pseudo-randÈmicos.

Info

Publication number
BR9405567A
BR9405567A BR9405567-0A BR9405567A BR9405567A BR 9405567 A BR9405567 A BR 9405567A BR 9405567 A BR9405567 A BR 9405567A BR 9405567 A BR9405567 A BR 9405567A
Authority
BR
Brazil
Prior art keywords
pseudo
bit stream
random bit
input bit
shift register
Prior art date
Application number
BR9405567-0A
Other languages
English (en)
Inventor
Larry C Puhl
Louis David Finkesltein
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of BR9405567A publication Critical patent/BR9405567A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02Digital function generators
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H04L9/0668Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator producing a non-linear pseudorandom sequence
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12Details relating to cryptographic hardware or logic circuitry

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Storage Device Security (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Facsimile Transmission Control (AREA)

Abstract

• proporcionado um aparelho e processo para gerar uma seq³ência bit pseudo-aleatória. Um primeiro bit de entrada 260 é determinado como uma função dos bits armazenados em um registrador de deslocamento 252 de acordo com um primeiro algoritmo de realimentação. Além disso, um segundo bit de entrada 262 é determinado como uma função de bits armazenados no registrador de deslocamento 252 de acordo com um segundo algoritmo de realimentação. Subseq³entemente, um bit de entrada específico 268 a ser apresentado para o registrador de deslocamento 252 é selecionado de forma determinista a partir do grupo consistindo do primeiro bit de entrada 260 e do segundo bit de entrada 262 de tal modo que uma seq³ência pseudo-randómica não linear pode ser produzida pelo registrador de deslocamento 252. Além disso, é descrita uma unidade de comunicação que utiliza a seq³ência de bits pseudo-randómica na criptografia de um sinal a ser transmitido e na descriptografia de um sinal recebido.
BR9405567-0A 1993-08-30 1994-07-11 Gerador de sequência de bits pseudo-rand6omicos, dispositivo de comunicação e processo para gerar sequência de bits pseudo-randÈmicos. BR9405567A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/114,804 US5365585A (en) 1993-08-30 1993-08-30 Method and apparatus for encryption having a feedback register with selectable taps
PCT/US1994/007774 WO1995006906A1 (en) 1993-08-30 1994-07-11 Method and apparatus for encryption having a feedback register with selectable taps

Publications (1)

Publication Number Publication Date
BR9405567A true BR9405567A (pt) 1999-09-08

Family

ID=22357530

Family Applications (1)

Application Number Title Priority Date Filing Date
BR9405567-0A BR9405567A (pt) 1993-08-30 1994-07-11 Gerador de sequência de bits pseudo-rand6omicos, dispositivo de comunicação e processo para gerar sequência de bits pseudo-randÈmicos.

Country Status (12)

Country Link
US (1) US5365585A (pt)
EP (1) EP0672273B1 (pt)
JP (1) JPH08503569A (pt)
KR (1) KR0168504B1 (pt)
BR (1) BR9405567A (pt)
CA (1) CA2146439C (pt)
DE (1) DE69429157T2 (pt)
FI (1) FI951946A0 (pt)
GB (1) GB2286274B (pt)
HK (1) HK1002338A1 (pt)
SG (1) SG76452A1 (pt)
WO (1) WO1995006906A1 (pt)

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Also Published As

Publication number Publication date
JPH08503569A (ja) 1996-04-16
GB2286274B (en) 1997-07-09
CA2146439C (en) 1998-09-22
GB2286274A (en) 1995-08-09
CA2146439A1 (en) 1995-03-09
DE69429157D1 (de) 2002-01-03
KR950704733A (ko) 1995-11-20
SG76452A1 (en) 2000-11-21
EP0672273A1 (en) 1995-09-20
FI951946A (fi) 1995-04-25
DE69429157T2 (de) 2002-06-06
WO1995006906A1 (en) 1995-03-09
GB9507790D0 (en) 1995-06-14
EP0672273B1 (en) 2001-11-21
KR0168504B1 (ko) 1999-01-15
FI951946A0 (fi) 1995-04-25
EP0672273A4 (en) 1997-05-28
HK1002338A1 (en) 1998-08-14
US5365585A (en) 1994-11-15

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Owner name: MOTOROLA SOLUTIONS, INC. (US)

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Owner name: MOTOROLA MOBILITY, INC. (US)

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Owner name: MOTOROLA MOBILITY, INC. (US)