BR8407181A - Processo para compensar o erro de truncamento em um sinal amostrado e dispositivo para executar o processo - Google Patents

Processo para compensar o erro de truncamento em um sinal amostrado e dispositivo para executar o processo

Info

Publication number
BR8407181A
BR8407181A BR8407181A BR8407181A BR8407181A BR 8407181 A BR8407181 A BR 8407181A BR 8407181 A BR8407181 A BR 8407181A BR 8407181 A BR8407181 A BR 8407181A BR 8407181 A BR8407181 A BR 8407181A
Authority
BR
Brazil
Prior art keywords
pct
compensate
perform
signal
truncation error
Prior art date
Application number
BR8407181A
Other languages
English (en)
Inventor
Ingemar Erik Dalqvist
Gunnar Anders Eriksson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR8407181A publication Critical patent/BR8407181A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0461—Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49984—Rounding away from zero

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Noise Elimination (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Complex Calculations (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Electronic Switches (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Error Detection And Correction (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Optical Communication System (AREA)
BR8407181A 1983-11-24 1984-10-31 Processo para compensar o erro de truncamento em um sinal amostrado e dispositivo para executar o processo BR8407181A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8306483A SE440300B (sv) 1983-11-24 1983-11-24 Forfarande for att i en samplad signal kompensera for trunkeringsfel samt anordning for utforande av forfarandet
PCT/SE1984/000367 WO1985002508A1 (en) 1983-11-24 1984-10-31 A method to compensate for the truncation error in a sampled signal and a device for carrying out the method

Publications (1)

Publication Number Publication Date
BR8407181A true BR8407181A (pt) 1985-11-05

Family

ID=20353446

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8407181A BR8407181A (pt) 1983-11-24 1984-10-31 Processo para compensar o erro de truncamento em um sinal amostrado e dispositivo para executar o processo

Country Status (22)

Country Link
US (1) US4750146A (pt)
EP (1) EP0162076B1 (pt)
KR (1) KR900008410B1 (pt)
AT (1) ATE30653T1 (pt)
AU (1) AU569928B2 (pt)
BR (1) BR8407181A (pt)
CA (1) CA1248603A (pt)
DE (1) DE3467275D1 (pt)
DK (1) DK162868C (pt)
ES (1) ES8601596A1 (pt)
FI (1) FI82795C (pt)
GR (1) GR80983B (pt)
IE (1) IE55857B1 (pt)
IN (1) IN161619B (pt)
IT (1) IT1177290B (pt)
MX (1) MX156872A (pt)
MY (1) MY100565A (pt)
NO (1) NO167348C (pt)
PT (1) PT79474B (pt)
SE (1) SE440300B (pt)
WO (1) WO1985002508A1 (pt)
YU (1) YU45678B (pt)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01169627A (ja) * 1987-12-25 1989-07-04 Toshiba Corp 高精度加算装置
JP2957183B2 (ja) * 1988-07-29 1999-10-04 日本電気株式会社 巡回型ディジタルフィルタ
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置
JPH04332215A (ja) * 1991-05-08 1992-11-19 Matsushita Electric Ind Co Ltd オフセット除去装置
JP3103914B2 (ja) * 1992-08-21 2000-10-30 ソニー株式会社 データの丸め処理回路およびデータの復元回路
US5493343A (en) * 1994-12-28 1996-02-20 Thomson Consumer Electronics, Inc. Compensation for truncation error in a digital video signal decoder
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal
US6240431B1 (en) * 1998-10-31 2001-05-29 Hewlett-Packard Company Decompression of limited range floating point numbers
US6253222B1 (en) * 1998-10-31 2001-06-26 Hewlett-Packard Company Compression of limited range floating point numbers
US6401107B1 (en) * 1999-11-03 2002-06-04 Motorola, Inc. Method and processor for reducing computational error in a processor having no rounding support
US9450601B1 (en) 2015-04-02 2016-09-20 Microsoft Technology Licensing, Llc Continuous rounding of differing bit lengths

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891837A (en) * 1972-07-03 1975-06-24 Drew E Sunstein Digital linearity and bias error compensating by adding an extra bit
US4195350A (en) * 1978-06-19 1980-03-25 Cbs Inc. Method and apparatus for eliminating deadband in digital recursive filters
US4282581A (en) * 1979-10-15 1981-08-04 Sperry Corporation Automatic overflow/imminent overflow detector
US4280196A (en) * 1979-11-14 1981-07-21 Hewlett-Packard Company Correction of zero drift, gain drift, and distortion errors in analog storage devices
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals

Also Published As

Publication number Publication date
IE842975L (en) 1985-05-24
DE3467275D1 (en) 1987-12-10
YU197584A (en) 1987-10-31
FI852458A0 (fi) 1985-06-20
MX156872A (es) 1988-10-06
PT79474A (en) 1984-12-01
AU569928B2 (en) 1988-02-25
FI82795C (sv) 1991-04-10
ES537892A0 (es) 1985-10-16
ATE30653T1 (de) 1987-11-15
PT79474B (en) 1986-08-05
IN161619B (pt) 1988-01-02
NO167348B (no) 1991-07-15
DK335385A (da) 1985-07-23
IE55857B1 (en) 1991-01-30
FI852458L (fi) 1985-06-20
CA1248603A (en) 1989-01-10
SE8306483L (sv) 1985-05-25
DK335385D0 (da) 1985-07-23
KR850003641A (ko) 1985-06-20
SE440300B (sv) 1985-07-22
MY100565A (en) 1990-11-15
EP0162076B1 (en) 1987-11-04
IT1177290B (it) 1987-08-26
DK162868B (da) 1991-12-16
IT8423695A1 (it) 1986-05-22
AU3613184A (en) 1985-06-13
SE8306483D0 (sv) 1983-11-24
US4750146A (en) 1988-06-07
ES8601596A1 (es) 1985-10-16
WO1985002508A1 (en) 1985-06-06
GR80983B (en) 1984-11-29
NO167348C (no) 1991-10-23
KR900008410B1 (ko) 1990-11-20
IT8423695A0 (it) 1984-11-22
YU45678B (sh) 1992-07-20
FI82795B (fi) 1990-12-31
EP0162076A1 (en) 1985-11-27
NO854118L (no) 1985-10-24
DK162868C (da) 1992-05-04

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Legal Events

Date Code Title Description
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 31/10/99