BR8306511A - Sistema para tratamento de erro de bit unico em uma unidade de armazenamento intermediaria - Google Patents

Sistema para tratamento de erro de bit unico em uma unidade de armazenamento intermediaria

Info

Publication number
BR8306511A
BR8306511A BR8306511A BR8306511A BR8306511A BR 8306511 A BR8306511 A BR 8306511A BR 8306511 A BR8306511 A BR 8306511A BR 8306511 A BR8306511 A BR 8306511A BR 8306511 A BR8306511 A BR 8306511A
Authority
BR
Brazil
Prior art keywords
storage unit
bit error
single bit
intermediate storage
treating single
Prior art date
Application number
BR8306511A
Other languages
English (en)
Inventor
Toshio Matsumoto
Motokazu Kato
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of BR8306511A publication Critical patent/BR8306511A/pt

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
BR8306511A 1982-12-25 1983-11-25 Sistema para tratamento de erro de bit unico em uma unidade de armazenamento intermediaria BR8306511A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57231874A JPS59117800A (ja) 1982-12-25 1982-12-25 バツフア・ストレ−ジの１ビツトエラ−処理方式

Publications (1)

Publication Number Publication Date
BR8306511A true BR8306511A (pt) 1984-07-31

Family

ID=16930371

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8306511A BR8306511A (pt) 1982-12-25 1983-11-25 Sistema para tratamento de erro de bit unico em uma unidade de armazenamento intermediaria

Country Status (9)

Country Link
US (1) US4598402A (pt)
EP (1) EP0112622B1 (pt)
JP (1) JPS59117800A (pt)
KR (1) KR870001307B1 (pt)
AU (1) AU547385B2 (pt)
BR (1) BR8306511A (pt)
CA (1) CA1206265A (pt)
DE (1) DE3381024D1 (pt)
ES (1) ES8407224A1 (pt)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR8503913A (pt) * 1984-08-18 1986-05-27 Fujitsu Ltd Sistema e processo de recuperacao de erros em um processador de dados do tipo de canalizacao tendo um dispositivo de memoria de controle e processo de recuperacao de erros em um processador de dados do tipo de canalizacao
DE3678893D1 (de) * 1985-10-03 1991-05-29 Mitsubishi Electric Corp Rechnerprogrammdebugsystem.
US4931990A (en) * 1987-11-19 1990-06-05 Bruce C. Perkin Hardened bubble memory circuit
US5283763A (en) * 1989-09-21 1994-02-01 Ncr Corporation Memory control system and method
US5604753A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for performing error correction on data from an external memory
US6199152B1 (en) 1996-08-22 2001-03-06 Transmeta Corporation Translated memory protection apparatus for an advanced microprocessor
US6011908A (en) * 1996-12-23 2000-01-04 Transmeta Corporation Gated store buffer for an advanced microprocessor
US6968469B1 (en) 2000-06-16 2005-11-22 Transmeta Corporation System and method for preserving internal processor context when the processor is powered down and restoring the internal processor context when processor is restored
EP1444580B1 (en) * 2001-11-09 2005-10-05 Sun Microsystems, Inc. Method and apparatus for fixing bit errors encountered during cache references without blocking
US7099221B2 (en) * 2004-05-06 2006-08-29 Micron Technology, Inc. Memory controller method and system compensating for memory cell data losses
US20060010339A1 (en) * 2004-06-24 2006-01-12 Klein Dean A Memory system and method having selective ECC during low power refresh
US7340668B2 (en) * 2004-06-25 2008-03-04 Micron Technology, Inc. Low power cost-effective ECC memory system and method
US7116602B2 (en) * 2004-07-15 2006-10-03 Micron Technology, Inc. Method and system for controlling refresh to avoid memory cell data losses
US6965537B1 (en) * 2004-08-31 2005-11-15 Micron Technology, Inc. Memory system and method using ECC to achieve low power refresh
EP1701095B1 (de) 2005-02-07 2012-01-18 Siemens Aktiengesellschaft Hitzeschild
US7894289B2 (en) 2006-10-11 2011-02-22 Micron Technology, Inc. Memory system and method using partial ECC to achieve low power refresh and fast access to data
US7900120B2 (en) 2006-10-18 2011-03-01 Micron Technology, Inc. Memory system and method using ECC with flag bit to identify modified data
US7995334B2 (en) 2010-01-06 2011-08-09 Apple Inc. Printed circuit board
US10296405B2 (en) * 2016-07-05 2019-05-21 SK Hynix Inc. Nonvolatile memory system and error determination method thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51127626A (en) * 1975-04-30 1976-11-06 Hitachi Ltd Information processor
IT1089225B (it) * 1977-12-23 1985-06-18 Honeywell Inf Systems Memoria con dispositivo rivelatore e correttore a intervento selettivo
US4201337A (en) * 1978-09-01 1980-05-06 Ncr Corporation Data processing system having error detection and correction circuits
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator
JPS598852B2 (ja) * 1979-07-30 1984-02-28 富士通株式会社 エラ−処理方式
JPS6051749B2 (ja) * 1979-08-31 1985-11-15 富士通株式会社 エラ−訂正方式
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
US4380812A (en) * 1980-04-25 1983-04-19 Data General Corporation Refresh and error detection and correction technique for a data processing system
EP0039227A3 (en) * 1980-04-25 1982-09-01 Data General Corporation Data processing system
US4371930A (en) * 1980-06-03 1983-02-01 Burroughs Corporation Apparatus for detecting, correcting and logging single bit memory read errors
US4493075A (en) * 1982-05-17 1985-01-08 National Semiconductor Corporation Self repairing bulk memory
US4458349A (en) * 1982-06-16 1984-07-03 International Business Machines Corporation Method for storing data words in fault tolerant memory to recover uncorrectable errors

Also Published As

Publication number Publication date
EP0112622A3 (en) 1987-01-14
ES526994A0 (es) 1984-08-16
KR870001307B1 (ko) 1987-07-11
AU2050083A (en) 1984-06-28
JPS59117800A (ja) 1984-07-07
KR840007190A (ko) 1984-12-05
US4598402A (en) 1986-07-01
EP0112622B1 (en) 1989-12-27
CA1206265A (en) 1986-06-17
JPS6310460B2 (pt) 1988-03-07
ES8407224A1 (es) 1984-08-16
DE3381024D1 (de) 1990-02-01
EP0112622A2 (en) 1984-07-04
AU547385B2 (en) 1985-10-17

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Legal Events

Date Code Title Description
B21A Patent or certificate of addition expired [chapter 21.1 patent gazette]

Free format text: PATENTE EXTINTA EM 25/11/98