BR8104634A - Arranjo de circuito - Google Patents

Arranjo de circuito

Info

Publication number
BR8104634A
BR8104634A BR8104634A BR8104634A BR8104634A BR 8104634 A BR8104634 A BR 8104634A BR 8104634 A BR8104634 A BR 8104634A BR 8104634 A BR8104634 A BR 8104634A BR 8104634 A BR8104634 A BR 8104634A
Authority
BR
Brazil
Prior art keywords
circuit arrangement
arrangement
circuit
Prior art date
Application number
BR8104634A
Other languages
English (en)
Inventor
Mario Landi
Giovanni Chiabrando
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of BR8104634A publication Critical patent/BR8104634A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
BR8104634A 1980-07-24 1981-07-20 Arranjo de circuito BR8104634A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8023659A IT1209338B (it) 1980-07-24 1980-07-24 Disposizione circuitale per il trasferimento di dati tra la memoria di un elaboratore elettronico e le unita' di interfaccia delle periferiche ad esso collegate.

Publications (1)

Publication Number Publication Date
BR8104634A true BR8104634A (pt) 1982-04-06

Family

ID=11208952

Family Applications (1)

Application Number Title Priority Date Filing Date
BR8104634A BR8104634A (pt) 1980-07-24 1981-07-20 Arranjo de circuito

Country Status (5)

Country Link
BR (1) BR8104634A (pt)
DE (1) DE3129296A1 (pt)
FR (1) FR2487549A1 (pt)
GB (1) GB2084768A (pt)
IT (1) IT1209338B (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3241376A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Dma-steuereinrichtung zur uebertragung von daten zwischen einem datensender und einem datenempfaenger
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
JP2550496B2 (ja) * 1989-03-30 1996-11-06 三菱電機株式会社 Ｄｍａコントローラ

Also Published As

Publication number Publication date
FR2487549A1 (fr) 1982-01-29
IT1209338B (it) 1989-07-16
DE3129296A1 (de) 1982-03-04
IT8023659A0 (it) 1980-07-24
GB2084768A (en) 1982-04-15

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