BR7906842A - Mecanismo sincronizador para controle de substituicao de paginas - Google Patents

Mecanismo sincronizador para controle de substituicao de paginas

Info

Publication number
BR7906842A
BR7906842A BR7906842A BR7906842A BR7906842A BR 7906842 A BR7906842 A BR 7906842A BR 7906842 A BR7906842 A BR 7906842A BR 7906842 A BR7906842 A BR 7906842A BR 7906842 A BR7906842 A BR 7906842A
Authority
BR
Brazil
Prior art keywords
synchronizing mechanism
substitution control
page substitution
page
control
Prior art date
Application number
BR7906842A
Other languages
English (en)
Inventor
G Mitchell
L Loen
F Soltis
R Collins
R Hoffman
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of BR7906842A publication Critical patent/BR7906842A/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1081—Address translation for peripheral access to main memory, e.g. direct memory access [DMA]
BR7906842A 1978-10-23 1979-10-23 Mecanismo sincronizador para controle de substituicao de paginas BR7906842A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/954,034 US4277826A (en) 1978-10-23 1978-10-23 Synchronizing mechanism for page replacement control

Publications (1)

Publication Number Publication Date
BR7906842A true BR7906842A (pt) 1980-09-16

Family

ID=25494849

Family Applications (1)

Application Number Title Priority Date Filing Date
BR7906842A BR7906842A (pt) 1978-10-23 1979-10-23 Mecanismo sincronizador para controle de substituicao de paginas

Country Status (6)

Country Link
US (1) US4277826A (pt)
EP (1) EP0010198B1 (pt)
JP (1) JPS5558879A (pt)
BR (1) BR7906842A (pt)
DE (1) DE2965742D1 (pt)
IT (1) IT1162587B (pt)

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JPH02273843A (ja) * 1989-04-14 1990-11-08 Nec Corp スワッピング装置
US5133058A (en) * 1989-09-18 1992-07-21 Sun Microsystems, Inc. Page-tagging translation look-aside buffer for a computer memory system
US5249286A (en) * 1990-05-29 1993-09-28 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
EP0459233A3 (en) * 1990-05-29 1992-04-08 National Semiconductor Corporation Selectively locking memory locations within a microprocessor's on-chip cache
CA2045789A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites Granularity hint for translation buffer in high performance processor
JPH04230508A (ja) * 1990-10-29 1992-08-19 Internatl Business Mach Corp <Ibm> 低電力消費メモリ装置
EP0549924A1 (en) * 1992-01-03 1993-07-07 International Business Machines Corporation Asynchronous co-processor data mover method and means
JPH05274152A (ja) * 1992-03-27 1993-10-22 Hitachi Ltd オブジェクト管理方式
US5640607A (en) * 1992-04-21 1997-06-17 Microsoft Corporation Method for sending bit mapped image by appending special code to text string and transmitting the text string separately from compressed residual image
US5493663A (en) * 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5463739A (en) * 1992-12-22 1995-10-31 International Business Machines Corporation Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold
FR2701578B1 (fr) * 1993-02-16 1995-03-31 Gemplus Card Int Procédé d'écriture dans une mémoire non volatile, notamment dans une carte à mémoire.
US5377337A (en) * 1993-06-08 1994-12-27 International Business Machines Corporation Method and means for enabling virtual addressing control by software users over a hardware page transfer control entity
US5568634A (en) * 1994-04-21 1996-10-22 Gemplus Card International Method of writing in a non-volatile memory, notably in a memory card employing memory allocation strategies on size and occupancy basis
US5889996A (en) * 1996-12-16 1999-03-30 Novell Inc. Accelerator for interpretive environments
US5983310A (en) 1997-02-13 1999-11-09 Novell, Inc. Pin management of accelerator for interpretive environments
US5813042A (en) * 1997-02-19 1998-09-22 International Business Machines Corp. Methods and systems for control of memory
US6141732A (en) * 1998-03-24 2000-10-31 Novell, Inc. Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks
US6578193B1 (en) 1998-03-24 2003-06-10 Novell, Inc. Endian-neutral loader for interpretive environment
US6356996B1 (en) 1998-03-24 2002-03-12 Novell, Inc. Cache fencing for interpretive environments
US6279095B1 (en) * 1998-11-09 2001-08-21 Compaq Computer Corporation Method and apparatus for omnibus wiring of virtual mapping table entries
US6662289B1 (en) * 2001-05-15 2003-12-09 Hewlett-Packard Development Company, Lp. Method and apparatus for direct conveyance of physical addresses from user level code to peripheral devices in virtual memory systems
CA2419900A1 (en) * 2003-02-26 2004-08-26 Ibm Canada Limited - Ibm Canada Limitee Relocating pages that are pinned in a buffer pool in a database system
KR100529329B1 (ko) * 2003-06-30 2005-11-17 삼성전자주식회사 다기능 수행 장치의 인쇄 방법 및 장치와 그 수행 장치를제어하는 컴퓨터 프로그램을 저장하는 컴퓨터로 읽을 수있는 기록 매체
US8214622B2 (en) * 2004-05-27 2012-07-03 International Business Machines Corporation Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment
GB0505289D0 (en) * 2005-03-15 2005-04-20 Symbian Software Ltd Computing device with automated page based rem shadowing and method of operation
US7734842B2 (en) * 2006-03-28 2010-06-08 International Business Machines Corporation Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages
US7908457B2 (en) * 2008-05-05 2011-03-15 International Business Machines Corporation Retaining an association between a virtual address based buffer and a user space application that owns the buffer
US7941568B2 (en) * 2008-05-05 2011-05-10 International Business Machines Corporation Mapping a virtual address to PCI bus address
US7543124B1 (en) 2008-07-09 2009-06-02 International Business Machines Corporation Method for preventing page replacement of unreferenced read-ahead file pages
US8250111B2 (en) * 2009-02-27 2012-08-21 International Business Machines Corporation Automatic detection and correction of hot pages in a database system
US8131976B2 (en) * 2009-04-13 2012-03-06 International Business Machines Corporation Tracking effective addresses in an out-of-order processor
US9164923B2 (en) * 2011-07-01 2015-10-20 Intel Corporation Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

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US3786427A (en) * 1971-06-29 1974-01-15 Ibm Dynamic address translation reversed
US3693165A (en) * 1971-06-29 1972-09-19 Ibm Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
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JPS5922977B2 (ja) 1975-06-30 1984-05-30 ハネイウエル・インフオメ−シヨン・システムスインコ−ポレ−テツド 入出力装置によるペ−ジメモリ呼び出し方法
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Also Published As

Publication number Publication date
JPS5740586B2 (pt) 1982-08-28
IT7926079A0 (it) 1979-09-28
IT1162587B (it) 1987-04-01
US4277826A (en) 1981-07-07
JPS5558879A (en) 1980-05-01
EP0010198B1 (de) 1983-06-22
EP0010198A2 (de) 1980-04-30
DE2965742D1 (en) 1983-07-28
EP0010198A3 (en) 1980-10-01

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Legal Events

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MK Patent expired

Effective date: 19941023