BR7901391A - Memoria de massa em estado solido,organizada por palavras e auto-corretiva,para sistema de controle de programa armazenado - Google Patents

Memoria de massa em estado solido,organizada por palavras e auto-corretiva,para sistema de controle de programa armazenado

Info

Publication number
BR7901391A
BR7901391A BR7901391A BR7901391A BR7901391A BR 7901391 A BR7901391 A BR 7901391A BR 7901391 A BR7901391 A BR 7901391A BR 7901391 A BR7901391 A BR 7901391A BR 7901391 A BR7901391 A BR 7901391A
Authority
BR
Brazil
Prior art keywords
corrective
organized
words
self
control system
Prior art date
Application number
BR7901391A
Other languages
English (en)
Inventor
R Manfreddi
E Garetti
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Publication of BR7901391A publication Critical patent/BR7901391A/pt

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/007Digital input from or digital output to memories of the shift register type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287Organisation of a multiplicity of shift registers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q3/00Selecting arrangements
    • H04Q3/42Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575Software application
    • H04Q3/54591Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13168Error Correction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Read Only Memory (AREA)
  • Exchange Systems With Centralized Control (AREA)
BR7901391A 1978-03-09 1979-03-07 Memoria de massa em estado solido,organizada por palavras e auto-corretiva,para sistema de controle de programa armazenado BR7901391A (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67499/78A IT1108375B (it) 1978-03-09 1978-03-09 Memoria di massa allo stato solido con autocorrezione e organizzata a parole per un sistema di controllo a programma registrato

Publications (1)

Publication Number Publication Date
BR7901391A true BR7901391A (pt) 1979-10-02

Family

ID=11302932

Family Applications (1)

Application Number Title Priority Date Filing Date
BR7901391A BR7901391A (pt) 1978-03-09 1979-03-07 Memoria de massa em estado solido,organizada por palavras e auto-corretiva,para sistema de controle de programa armazenado

Country Status (10)

Country Link
US (1) US4216532A (pt)
JP (1) JPS54126434A (pt)
BE (1) BE874402A (pt)
BR (1) BR7901391A (pt)
CA (1) CA1114513A (pt)
DE (1) DE2909151C2 (pt)
FR (1) FR2419563A1 (pt)
GB (1) GB2016180B (pt)
IT (1) IT1108375B (pt)
NL (1) NL7901871A (pt)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1109655B (it) * 1978-06-28 1985-12-23 Cselt Centro Studi Lab Telecom Memoria di massa allo stato solido organizzata a bit autocorrettiva e riconfigurabile per un sistema di controllo a programma registrato
CA1232355A (en) * 1983-09-02 1988-02-02 Wang Laboratories, Inc. Single in-line memory module
GB2172126A (en) * 1985-01-24 1986-09-10 John Richard Mumford Interchangeable solid state memory device
US6842802B2 (en) * 2001-11-30 2005-01-11 Aftg-Tg, L.L.C. Programmatic time-gap defect correction apparatus and method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735105A (en) * 1971-06-11 1973-05-22 Ibm Error correcting system and method for monolithic memories
US3953837A (en) * 1974-11-27 1976-04-27 Texas Instruments Incorporated Dual serial-parallel-serial analog memory
DE2524802A1 (de) * 1975-06-04 1976-12-16 Siemens Ag Arbeitsspeicheranordnung
US4161788A (en) * 1977-04-21 1979-07-17 Texas Instruments Incorporated Bubble memory controller with multipage data handling

Also Published As

Publication number Publication date
GB2016180A (en) 1979-09-19
US4216532A (en) 1980-08-05
IT7867499A0 (it) 1978-03-09
BE874402A (fr) 1979-06-18
DE2909151C2 (de) 1983-06-09
CA1114513A (en) 1981-12-15
DE2909151A1 (de) 1979-09-13
NL7901871A (nl) 1979-09-11
FR2419563A1 (fr) 1979-10-05
IT1108375B (it) 1985-12-09
FR2419563B1 (pt) 1984-01-27
GB2016180B (en) 1982-06-09
JPS54126434A (en) 1979-10-01

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