BR112022025548A2 - Técnicas de circuito para robustez de descarga eletrostática aperfeiçoada (esd) - Google Patents

Técnicas de circuito para robustez de descarga eletrostática aperfeiçoada (esd)

Info

Publication number
BR112022025548A2
BR112022025548A2 BR112022025548A BR112022025548A BR112022025548A2 BR 112022025548 A2 BR112022025548 A2 BR 112022025548A2 BR 112022025548 A BR112022025548 A BR 112022025548A BR 112022025548 A BR112022025548 A BR 112022025548A BR 112022025548 A2 BR112022025548 A2 BR 112022025548A2
Authority
BR
Brazil
Prior art keywords
esd
robustness
electrostatic discharge
circuit techniques
enhanced electrostatic
Prior art date
Application number
BR112022025548A
Other languages
English (en)
Inventor
Dundigal Sreeker
Jalilizeinali Reza
Chaitanya Chillara Krishna
Chen Wen-Yi
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022025548A2 publication Critical patent/BR112022025548A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/38—Impedance-matching networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

TÉCNICAS DE CIRCUITO PARA ROBUSTEZ DE DESCARGA ELETROSTÁTICA APERFEIÇOADA (ESD). Um chip inclui um pad e um acionador possuindo uma saída acoplada ao pad. O chip também inclui um ou mais diodos acoplados entre o pad e um barramento de aterramento, onde os um ou mais diodos estão em uma direção de avanço, do pad para o barramento de aterramento.
BR112022025548A 2020-06-30 2021-06-23 Técnicas de circuito para robustez de descarga eletrostática aperfeiçoada (esd) BR112022025548A2 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202063046331P 2020-06-30 2020-06-30
US17/354,659 US20210407990A1 (en) 2020-06-30 2021-06-22 Circuit techniques for enhanced electrostatic discharge (esd) robustness
PCT/US2021/038623 WO2022005832A1 (en) 2020-06-30 2021-06-23 Circuit techniques for enhanced electrostatic discharge (esd) robustness

Publications (1)

Publication Number Publication Date
BR112022025548A2 true BR112022025548A2 (pt) 2023-01-31

Family

ID=79031485

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022025548A BR112022025548A2 (pt) 2020-06-30 2021-06-23 Técnicas de circuito para robustez de descarga eletrostática aperfeiçoada (esd)

Country Status (7)

Country Link
US (1) US20210407990A1 (pt)
EP (1) EP4173042A1 (pt)
KR (1) KR20230029658A (pt)
CN (1) CN115699312A (pt)
BR (1) BR112022025548A2 (pt)
TW (1) TW202207411A (pt)
WO (1) WO2022005832A1 (pt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI823418B (zh) * 2022-06-09 2023-11-21 世界先進積體電路股份有限公司 靜電放電保護電路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6671146B1 (en) * 1999-01-19 2003-12-30 Seiko Epson Corporation Electrostatic protection circuit and semiconductor integrated circuit using the same
DE10342305A1 (de) * 2003-09-12 2005-04-14 Infineon Technologies Ag ESD-Schutzvorrichtung
DE102006023429B4 (de) * 2006-05-18 2011-03-10 Infineon Technologies Ag ESD-Schutz-Element zur Verwendung in einem elektrischen Schaltkreis
KR100855265B1 (ko) * 2006-06-30 2008-09-01 주식회사 하이닉스반도체 정전기 방전 보호 회로
US8982581B2 (en) * 2010-06-30 2015-03-17 Xilinx, Inc. Electro-static discharge protection for die of a multi-chip module

Also Published As

Publication number Publication date
CN115699312A (zh) 2023-02-03
US20210407990A1 (en) 2021-12-30
KR20230029658A (ko) 2023-03-03
EP4173042A1 (en) 2023-05-03
WO2022005832A1 (en) 2022-01-06
TW202207411A (zh) 2022-02-16

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing