BR112018004665A2 - formação de ponte de sinal de entrada/saída e virtualização em uma rede de múltiplos nós - Google Patents

formação de ponte de sinal de entrada/saída e virtualização em uma rede de múltiplos nós

Info

Publication number
BR112018004665A2
BR112018004665A2 BR112018004665A BR112018004665A BR112018004665A2 BR 112018004665 A2 BR112018004665 A2 BR 112018004665A2 BR 112018004665 A BR112018004665 A BR 112018004665A BR 112018004665 A BR112018004665 A BR 112018004665A BR 112018004665 A2 BR112018004665 A2 BR 112018004665A2
Authority
BR
Brazil
Prior art keywords
gps
processing unit
peripheral devices
virtual
virtualization
Prior art date
Application number
BR112018004665A
Other languages
English (en)
Inventor
Jee MISHRA Lalan
Pitigoi-Aron Radu
Dominic Wietfeldt Richard
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112018004665A2 publication Critical patent/BR112018004665A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Information Transfer Systems (AREA)
  • Logic Circuits (AREA)
  • Bus Control (AREA)

Abstract

em um aspecto, um circuito integrado obtém um conjunto de sinais de entrada/saída de propósito geral (gpio) para um ou mais dispositivos periféricos, obtém um primeiro pacote de gpio virtual que inclui o conjunto de sinais de gpio independentemente de uma unidade de processamento central e transmite o primeiro pacote de gpio virtual para os um ou mais dispositivos periféricos através de um barramento de i3c independentemente da unidade de processamento central. o circuito integrado pode obter adicionalmente um conjunto de sinais de configuração para configurar um ou mais pinos de gpio dos um ou mais dispositivos periféricos, obter um segundo pacote de gpio virtual que inclui o conjunto de sinais de configuração independentemente da unidade de processamento central e transmitir o segundo pacote de gpio virtual para os um ou mais dispositivos periféricos através do barramento de i3c independentemente da unidade de processamento central.
BR112018004665A 2015-09-10 2016-08-22 formação de ponte de sinal de entrada/saída e virtualização em uma rede de múltiplos nós BR112018004665A2 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562216891P 2015-09-10 2015-09-10
US201562265612P 2015-12-10 2015-12-10
US201662349609P 2016-06-13 2016-06-13
US15/242,368 US10140242B2 (en) 2015-09-10 2016-08-19 General purpose input/output (GPIO) signal bridging with I3C bus interfaces and virtualization in a multi-node network
PCT/US2016/048082 WO2017044301A1 (en) 2015-09-10 2016-08-22 Input/output signal bridging and virtualization in a multi-node network

Publications (1)

Publication Number Publication Date
BR112018004665A2 true BR112018004665A2 (pt) 2018-09-25

Family

ID=58236893

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018004665A BR112018004665A2 (pt) 2015-09-10 2016-08-22 formação de ponte de sinal de entrada/saída e virtualização em uma rede de múltiplos nós

Country Status (7)

Country Link
US (1) US10140242B2 (pt)
EP (1) EP3347824A1 (pt)
JP (1) JP2018533120A (pt)
KR (1) KR20180050728A (pt)
CN (1) CN108027791A (pt)
BR (1) BR112018004665A2 (pt)
WO (1) WO2017044301A1 (pt)

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Also Published As

Publication number Publication date
CN108027791A (zh) 2018-05-11
EP3347824A1 (en) 2018-07-18
JP2018533120A (ja) 2018-11-08
US10140242B2 (en) 2018-11-27
KR20180050728A (ko) 2018-05-15
WO2017044301A1 (en) 2017-03-16
US20170075852A1 (en) 2017-03-16

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B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette]