BR112022018896A2 - Processamento de modificação de fluxo de dados para reduzir os efeitos de potência durante processamento paralelo - Google Patents

Processamento de modificação de fluxo de dados para reduzir os efeitos de potência durante processamento paralelo

Info

Publication number
BR112022018896A2
BR112022018896A2 BR112022018896A BR112022018896A BR112022018896A2 BR 112022018896 A2 BR112022018896 A2 BR 112022018896A2 BR 112022018896 A BR112022018896 A BR 112022018896A BR 112022018896 A BR112022018896 A BR 112022018896A BR 112022018896 A2 BR112022018896 A2 BR 112022018896A2
Authority
BR
Brazil
Prior art keywords
data
processing
sub
blocks
reduce power
Prior art date
Application number
BR112022018896A
Other languages
English (en)
Portuguese (pt)
Inventor
Jun Park Hee
Gerard Hofmann Richard
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112022018896A2 publication Critical patent/BR112022018896A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • Medical Informatics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Image Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Power Sources (AREA)
  • Complex Calculations (AREA)
BR112022018896A 2020-03-30 2021-03-29 Processamento de modificação de fluxo de dados para reduzir os efeitos de potência durante processamento paralelo BR112022018896A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/834,986 US11507423B2 (en) 2020-03-30 2020-03-30 Processing data stream modification to reduce power effects during parallel processing
PCT/US2021/070327 WO2021203125A1 (en) 2020-03-30 2021-03-29 Processing data stream modification to reduce power effects during parallel processing

Publications (1)

Publication Number Publication Date
BR112022018896A2 true BR112022018896A2 (pt) 2022-11-08

Family

ID=75640050

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112022018896A BR112022018896A2 (pt) 2020-03-30 2021-03-29 Processamento de modificação de fluxo de dados para reduzir os efeitos de potência durante processamento paralelo

Country Status (9)

Country Link
US (2) US11507423B2 (https=)
EP (1) EP4127928A1 (https=)
JP (2) JP7750847B2 (https=)
KR (1) KR20220154698A (https=)
CN (2) CN115315688B (https=)
BR (1) BR112022018896A2 (https=)
PH (1) PH12022551885A1 (https=)
TW (1) TWI876016B (https=)
WO (1) WO2021203125A1 (https=)

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US11972348B2 (en) 2020-10-30 2024-04-30 Apple Inc. Texture unit circuit in neural network processor
US12277494B2 (en) 2020-11-19 2025-04-15 Apple Inc. Multi-dimensional tensor support extension in neural network processor
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Also Published As

Publication number Publication date
EP4127928A1 (en) 2023-02-08
US20230078991A1 (en) 2023-03-16
CN115315688B (zh) 2025-12-23
WO2021203125A1 (en) 2021-10-07
TWI876016B (zh) 2025-03-11
KR20220154698A (ko) 2022-11-22
CN115315688A (zh) 2022-11-08
CN121807567A (zh) 2026-04-07
JP7750847B2 (ja) 2025-10-07
US11983567B2 (en) 2024-05-14
JP2026015712A (ja) 2026-01-30
TW202143032A (zh) 2021-11-16
US20210303359A1 (en) 2021-09-30
US11507423B2 (en) 2022-11-22
PH12022551885A1 (en) 2023-11-20
JP2023519665A (ja) 2023-05-12

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