BR112019005755A2 - amplificador de detecção de corrente travada diferencial de cancelamento de compensação de transistor de mos - Google Patents
amplificador de detecção de corrente travada diferencial de cancelamento de compensação de transistor de mosInfo
- Publication number
- BR112019005755A2 BR112019005755A2 BR112019005755A BR112019005755A BR112019005755A2 BR 112019005755 A2 BR112019005755 A2 BR 112019005755A2 BR 112019005755 A BR112019005755 A BR 112019005755A BR 112019005755 A BR112019005755 A BR 112019005755A BR 112019005755 A2 BR112019005755 A2 BR 112019005755A2
- Authority
- BR
- Brazil
- Prior art keywords
- input
- detection
- voltages
- voltage
- detection amplifier
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title abstract 9
- 239000003990 capacitor Substances 0.000 abstract 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1697—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/06—Sense amplifier related aspects
- G11C2207/063—Current sense amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
são providos amplificadores de detecção (sas) de corrente travada (clsas) de zona morta de detecção zero (zs) de cancelamento de compensação (oc) (oczs-sas) de transistor de semicondutor de óxido metálico (mos), para detecção de voltagens diferenciais. um oczs-sa é configurado para amplificar as voltagens diferenciais de entrada de dados e de referência, recebidas com uma voltagem de compensação de amplificador de detecção menor para fornecer margem de detecção maior entre estados de armazenamento diferentes de célula(s) de bits de memória. o oczs-sa é configurado para cancelar as voltagens de compensação de transistores de entrada e de entrada de complemento, e manter os transistores de entrada e de entrada de complemento em seus estados ativados durante as fases de detecção, de modo que a detecção não seja realizada em suas zonas mortas quando sua voltagem de porta para fonte (vgs) estiver abaixo de suas respectivas voltagens de limiar. em outros aspectos, capacitores de amplificadores de detecção são configurados para armazenar diretamente as voltagens de entrada de dados e de referência nas portas de transistores de entrada e de entrada de complemento durante fases de captura de voltagem para evitar área de leiaute adicional que de outra forma seria consumida com circuitos de capacitor de detecção, adicionais.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/274,034 US9852783B1 (en) | 2016-09-23 | 2016-09-23 | Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages |
US15/274,034 | 2016-09-23 | ||
PCT/US2017/052068 WO2018057460A1 (en) | 2016-09-23 | 2017-09-18 | Mos transistor offset-cancelling differential current-latched sense amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
BR112019005755A2 true BR112019005755A2 (pt) | 2019-06-11 |
BR112019005755B1 BR112019005755B1 (pt) | 2024-02-06 |
Family
ID=59969283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112019005755-2A BR112019005755B1 (pt) | 2016-09-23 | 2017-09-18 | Amplificador de detecção de corrente travada diferencial de cancelamento de compensação de transistor de mos |
Country Status (7)
Country | Link |
---|---|
US (1) | US9852783B1 (pt) |
EP (1) | EP3516654B1 (pt) |
KR (1) | KR102511912B1 (pt) |
CN (1) | CN111316358B (pt) |
AU (2) | AU2017332696A1 (pt) |
BR (1) | BR112019005755B1 (pt) |
WO (1) | WO2018057460A1 (pt) |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
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US9818478B2 (en) | 2012-12-07 | 2017-11-14 | Attopsemi Technology Co., Ltd | Programmable resistive device and memory using diode as selector |
US10923204B2 (en) | 2010-08-20 | 2021-02-16 | Attopsemi Technology Co., Ltd | Fully testible OTP memory |
US10916317B2 (en) | 2010-08-20 | 2021-02-09 | Attopsemi Technology Co., Ltd | Programmable resistance memory on thin film transistor technology |
US10586832B2 (en) | 2011-02-14 | 2020-03-10 | Attopsemi Technology Co., Ltd | One-time programmable devices using gate-all-around structures |
US10726914B2 (en) | 2017-04-14 | 2020-07-28 | Attopsemi Technology Co. Ltd | Programmable resistive memories with low power read operation and novel sensing scheme |
US11062786B2 (en) | 2017-04-14 | 2021-07-13 | Attopsemi Technology Co., Ltd | One-time programmable memories with low power read operation and novel sensing scheme |
US10535413B2 (en) * | 2017-04-14 | 2020-01-14 | Attopsemi Technology Co., Ltd | Low power read operation for programmable resistive memories |
US11615859B2 (en) | 2017-04-14 | 2023-03-28 | Attopsemi Technology Co., Ltd | One-time programmable memories with ultra-low power read operation and novel sensing scheme |
US9997239B1 (en) * | 2017-05-02 | 2018-06-12 | Everspin Technologies, Inc. | Word line overdrive in memory and method therefor |
US10770160B2 (en) | 2017-11-30 | 2020-09-08 | Attopsemi Technology Co., Ltd | Programmable resistive memory formed by bit slices from a standard cell library |
US11309005B2 (en) * | 2018-10-31 | 2022-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Current steering in reading magnetic tunnel junction |
US10726917B1 (en) * | 2019-01-23 | 2020-07-28 | Micron Technology, Inc. | Techniques for read operations |
US10658022B1 (en) | 2019-02-13 | 2020-05-19 | International Business Machines Corporation | High gain sense amplifier with offset cancellation for magnetoresistive random access memory |
US11910723B2 (en) * | 2019-10-31 | 2024-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory device with electrically parallel source lines |
US11322195B2 (en) | 2019-11-27 | 2022-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Compute in memory system |
KR102239742B1 (ko) * | 2020-03-02 | 2021-04-12 | 인천대학교 산학협력단 | 읽기 오류의 제거가 가능한 비휘발성 플립플롭의 데이터 복원 모드에서의 동작 방법 |
US11353909B2 (en) * | 2020-03-27 | 2022-06-07 | Synaptics Incorporated | Operational amplifier, integrated circuit, and method for operating the same |
US11087800B1 (en) * | 2020-04-10 | 2021-08-10 | Sandisk Technologies Llc | Sense amplifier architecture providing small swing voltage sensing |
US11018687B1 (en) * | 2020-05-13 | 2021-05-25 | Qualcomm Incorporated | Power-efficient compute-in-memory analog-to-digital converters |
CN113160859B (zh) * | 2021-03-31 | 2021-12-14 | 珠海博雅科技有限公司 | 灵敏放大器及存储器 |
CN113419200B (zh) * | 2021-07-09 | 2022-05-10 | 福州大学 | 探测Bi2Te3表面态六角翘曲的电流诱导自旋极化的方法 |
KR102652188B1 (ko) * | 2023-09-08 | 2024-03-28 | 연세대학교 산학협력단 | 전류 래치 센스 앰프 및 메모리 장치 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2885597B2 (ja) * | 1993-03-10 | 1999-04-26 | 株式会社東芝 | 半導体メモリ |
US6396733B1 (en) | 2000-07-17 | 2002-05-28 | Micron Technology, Inc. | Magneto-resistive memory having sense amplifier with offset control |
US6803794B2 (en) | 2003-02-26 | 2004-10-12 | Raytheon Company | Differential capacitance sense amplifier |
US7649559B2 (en) * | 2006-08-30 | 2010-01-19 | Aptina Imaging Corporation | Amplifier offset cancellation devices, systems, and methods |
US8233342B2 (en) * | 2008-03-14 | 2012-07-31 | International Business Machines Corporation | Apparatus and method for implementing write assist for static random access memory arrays |
JP5412639B2 (ja) * | 2008-10-31 | 2014-02-12 | 国立大学法人東京工業大学 | 比較器及びアナログデジタル変換器 |
US8521500B2 (en) * | 2010-08-24 | 2013-08-27 | International Business Machines Corporation | Method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models |
US8072244B1 (en) * | 2010-08-31 | 2011-12-06 | National Tsing Hua University | Current sensing amplifier and method thereof |
KR20120058057A (ko) * | 2010-11-29 | 2012-06-07 | 삼성전자주식회사 | 오프셋 제거 회로, 샘플링 회로 및 이미지 센서 |
US9140747B2 (en) * | 2013-07-22 | 2015-09-22 | Qualcomm Incorporated | Sense amplifier offset voltage reduction |
US9165630B2 (en) * | 2013-08-30 | 2015-10-20 | Qualcomm Incorporated | Offset canceling dual stage sensing circuit |
US9111623B1 (en) * | 2014-02-12 | 2015-08-18 | Qualcomm Incorporated | NMOS-offset canceling current-latched sense amplifier |
US9384792B2 (en) * | 2014-04-09 | 2016-07-05 | Globalfoundries Inc. | Offset-cancelling self-reference STT-MRAM sense amplifier |
US20150341023A1 (en) * | 2014-05-22 | 2015-11-26 | Spansion Llc | Methods, Circuits, Devices and Systems for Comparing Signals |
US9711206B2 (en) * | 2014-06-05 | 2017-07-18 | Micron Technology, Inc. | Performing logical operations using sensing circuitry |
US9691462B2 (en) * | 2014-09-27 | 2017-06-27 | Qualcomm Incorporated | Latch offset cancelation for magnetoresistive random access memory |
-
2016
- 2016-09-23 US US15/274,034 patent/US9852783B1/en active Active
-
2017
- 2017-09-18 KR KR1020197008130A patent/KR102511912B1/ko active IP Right Grant
- 2017-09-18 BR BR112019005755-2A patent/BR112019005755B1/pt active IP Right Grant
- 2017-09-18 WO PCT/US2017/052068 patent/WO2018057460A1/en active Search and Examination
- 2017-09-18 AU AU2017332696A patent/AU2017332696A1/en not_active Abandoned
- 2017-09-18 CN CN201780058407.1A patent/CN111316358B/zh active Active
- 2017-09-18 EP EP17772855.7A patent/EP3516654B1/en active Active
-
2022
- 2022-07-28 AU AU2022209322A patent/AU2022209322A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
BR112019005755B1 (pt) | 2024-02-06 |
KR20190053854A (ko) | 2019-05-20 |
CN111316358A (zh) | 2020-06-19 |
AU2022209322A1 (en) | 2022-09-01 |
EP3516654B1 (en) | 2020-10-21 |
AU2017332696A1 (en) | 2019-03-07 |
CN111316358B (zh) | 2023-09-22 |
WO2018057460A1 (en) | 2018-03-29 |
US9852783B1 (en) | 2017-12-26 |
EP3516654A1 (en) | 2019-07-31 |
KR102511912B1 (ko) | 2023-03-17 |
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Legal Events
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B350 | Update of information on the portal [chapter 15.35 patent gazette] | ||
B06W | Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette] | ||
B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 18/09/2017, OBSERVADAS AS CONDICOES LEGAIS |