BR112018016564A2 - método em um circuito receptor de processamento de um sinal - Google Patents

método em um circuito receptor de processamento de um sinal

Info

Publication number
BR112018016564A2
BR112018016564A2 BR112018016564A BR112018016564A BR112018016564A2 BR 112018016564 A2 BR112018016564 A2 BR 112018016564A2 BR 112018016564 A BR112018016564 A BR 112018016564A BR 112018016564 A BR112018016564 A BR 112018016564A BR 112018016564 A2 BR112018016564 A2 BR 112018016564A2
Authority
BR
Brazil
Prior art keywords
clock
input
circuit
adc
signal
Prior art date
Application number
BR112018016564A
Other languages
English (en)
Other versions
BR112018016564B1 (pt
Inventor
Axmon Joakim
HILL Johan
Breschel Michael
Liu Yuhang
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of BR112018016564A2 publication Critical patent/BR112018016564A2/pt
Publication of BR112018016564B1 publication Critical patent/BR112018016564B1/pt

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0001—Arrangements for dividing the transmission path
    • H04L5/0003—Two-dimensional division
    • H04L5/0005—Time-frequency
    • H04L5/0007—Time-frequency the frequencies being orthogonal, e.g. OFDM(A), DMT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
    • H04L27/2689—Link with other circuits, i.e. special connections between synchronisation arrangements and other circuits for achieving synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

é descrito um circuito receptor que compreende um circuito de conversor analógico para digital (adc) que tem uma entrada analógica, uma entrada de relógio e uma saída digital, e um circuito divisor de relógio que tem uma entrada de relógio de referência e uma entrada seletora de fase, e que tem uma saída de relógio acoplada na entrada de relógio do circuito adc. o circuito divisor de relógio é configurado para dividir um sinal de relógio de referência acoplado na entrada de relógio de referência em uma frequência de relógio de referência, para produzir um sinal de saída de relógio em uma frequência de relógio adc, na saída de relógio, de maneira tal que a frequência de relógio de referência seja um múltiplo de número inteiro n da frequência de relógio adc. o circuito divisor de relógio é adicionalmente configurado para selecionar a partir de uma pluralidade de fases selecionáveis do sinal de saída de relógio, responsivo a um sinal seletor de fase aplicado na entrada seletora de fase.
BR112018016564-6A 2016-02-15 2017-02-14 Método em um circuito receptor de processamento de um sinal BR112018016564B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662295327P 2016-02-15 2016-02-15
US62/295327 2016-02-15
PCT/EP2017/053234 WO2017140651A1 (en) 2016-02-15 2017-02-14 Receiver circuit and methods

Publications (2)

Publication Number Publication Date
BR112018016564A2 true BR112018016564A2 (pt) 2019-01-02
BR112018016564B1 BR112018016564B1 (pt) 2024-03-12

Family

ID=58044069

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018016564-6A BR112018016564B1 (pt) 2016-02-15 2017-02-14 Método em um circuito receptor de processamento de um sinal

Country Status (7)

Country Link
US (2) US10797835B2 (pt)
EP (1) EP3417546B1 (pt)
JP (1) JP6585307B2 (pt)
BR (1) BR112018016564B1 (pt)
DK (1) DK3417546T3 (pt)
PH (1) PH12018501698A1 (pt)
WO (1) WO2017140651A1 (pt)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL3687104T3 (pl) 2016-02-15 2022-07-18 Telefonaktiebolaget Lm Ericsson (Publ) Sposób i aparat do generowania sygnałów OFDM NB-IOT z niższą częstotliwością próbkowania
US10797835B2 (en) * 2016-02-15 2020-10-06 Telefonaktiebolaget Lm Ericsson (Publ) Receiver circuit and methods

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KR20140111496A (ko) 2013-03-11 2014-09-19 삼성전자주식회사 이동 통신 시스템에서 등화기 수신기 및 그 방법
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Also Published As

Publication number Publication date
EP3417546A1 (en) 2018-12-26
EP3417546B1 (en) 2021-04-07
US20200403742A1 (en) 2020-12-24
WO2017140651A1 (en) 2017-08-24
BR112018016564B1 (pt) 2024-03-12
JP2019505130A (ja) 2019-02-21
US10797835B2 (en) 2020-10-06
PH12018501698A1 (en) 2019-06-10
DK3417546T3 (da) 2021-05-31
US20200112404A1 (en) 2020-04-09
US11239961B2 (en) 2022-02-01
JP6585307B2 (ja) 2019-10-02

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Legal Events

Date Code Title Description
B350 Update of information on the portal [chapter 15.35 patent gazette]
B06W Patent application suspended after preliminary examination (for patents with searches from other patent authorities) chapter 6.23 patent gazette]
B15K Others concerning applications: alteration of classification

Free format text: AS CLASSIFICACOES ANTERIORES ERAM: H03L 7/099 , H04B 1/40

Ipc: H03L 7/099 (2006.01), H03M 1/06 (2006.01), H03M 1/

B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 14/02/2017, OBSERVADAS AS CONDICOES LEGAIS