BR112018001208B1 - Operações simd de largura misturada tendo operações de elemento par e elemento ímpar usando par de registros para elementos de dados largos - Google Patents

Operações simd de largura misturada tendo operações de elemento par e elemento ímpar usando par de registros para elementos de dados largos Download PDF

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Publication number
BR112018001208B1
BR112018001208B1 BR112018001208-4A BR112018001208A BR112018001208B1 BR 112018001208 B1 BR112018001208 B1 BR 112018001208B1 BR 112018001208 A BR112018001208 A BR 112018001208A BR 112018001208 B1 BR112018001208 B1 BR 112018001208B1
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BR
Brazil
Prior art keywords
data elements
simd
source
bit
instruction
Prior art date
Application number
BR112018001208-4A
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English (en)
Portuguese (pt)
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BR112018001208A2 (pt
Inventor
Eric Wayne Mahurin
Ajay Anant Ingle
Original Assignee
Qualcomm Incorporated
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Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018001208A2 publication Critical patent/BR112018001208A2/pt
Publication of BR112018001208B1 publication Critical patent/BR112018001208B1/pt

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30112—Register structure comprising data of variable length

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
BR112018001208-4A 2015-07-21 2016-06-21 Operações simd de largura misturada tendo operações de elemento par e elemento ímpar usando par de registros para elementos de dados largos BR112018001208B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/805,456 US10489155B2 (en) 2015-07-21 2015-07-21 Mixed-width SIMD operations using even/odd register pairs for wide data elements
US14/805,456 2015-07-21
PCT/US2016/038487 WO2017014892A1 (en) 2015-07-21 2016-06-21 Mixed-width simd operations having even-element and odd-element operations using register pair for wide data elements

Publications (2)

Publication Number Publication Date
BR112018001208A2 BR112018001208A2 (pt) 2018-09-11
BR112018001208B1 true BR112018001208B1 (pt) 2023-12-26

Family

ID=56204087

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018001208-4A BR112018001208B1 (pt) 2015-07-21 2016-06-21 Operações simd de largura misturada tendo operações de elemento par e elemento ímpar usando par de registros para elementos de dados largos

Country Status (9)

Country Link
US (1) US10489155B2 (https=)
EP (1) EP3326060B1 (https=)
JP (1) JP6920277B2 (https=)
KR (1) KR102121866B1 (https=)
CN (1) CN107851010B (https=)
BR (1) BR112018001208B1 (https=)
ES (1) ES2795832T3 (https=)
HU (1) HUE049260T2 (https=)
WO (1) WO2017014892A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2540943B (en) * 2015-07-31 2018-04-11 Advanced Risc Mach Ltd Vector arithmetic instruction
US10698685B2 (en) * 2017-05-03 2020-06-30 Intel Corporation Instructions for dual destination type conversion, mixed precision accumulation, and mixed precision atomic memory operations
CN109298886A (zh) * 2017-07-25 2019-02-01 合肥君正科技有限公司 Simd指令执行方法、装置及处理器
US20190272175A1 (en) * 2018-03-01 2019-09-05 Qualcomm Incorporated Single pack & unpack network and method for variable bit width data formats for computational machines
US10528346B2 (en) 2018-03-29 2020-01-07 Intel Corporation Instructions for fused multiply-add operations with variable precision input operands
CN111324354B (zh) * 2019-12-27 2023-04-18 湖南科技大学 一种融合寄存器对需求的寄存器选择方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673321A (en) 1995-06-29 1997-09-30 Hewlett-Packard Company Efficient selection and mixing of multiple sub-word items packed into two or more computer words
US6202141B1 (en) 1998-06-16 2001-03-13 International Business Machines Corporation Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors
US7127593B2 (en) * 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US6922716B2 (en) 2001-07-13 2005-07-26 Motorola, Inc. Method and apparatus for vector processing
US7107305B2 (en) 2001-10-05 2006-09-12 Intel Corporation Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
KR100553252B1 (ko) * 2002-02-01 2006-02-20 아바고테크놀로지스코리아 주식회사 휴대용 단말기의 전력 증폭 장치
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7668897B2 (en) 2003-06-16 2010-02-23 Arm Limited Result partitioning within SIMD data processing systems
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
GB2409068A (en) * 2003-12-09 2005-06-15 Advanced Risc Mach Ltd Data element size control within parallel lanes of processing
GB2411975B (en) * 2003-12-09 2006-10-04 Advanced Risc Mach Ltd Data processing apparatus and method for performing arithmetic operations in SIMD data processing
US7353244B2 (en) * 2004-04-16 2008-04-01 Marvell International Ltd. Dual-multiply-accumulator operation optimized for even and odd multisample calculations
US7400271B2 (en) * 2005-06-21 2008-07-15 International Characters, Inc. Method and apparatus for processing character streams
CN1964490A (zh) * 2005-11-09 2007-05-16 松下电器产业株式会社 一种滤波器及滤波方法
WO2013095338A1 (en) 2011-12-19 2013-06-27 Intel Corporation Simd integer multiply-accumulate instruction for multi-precision arithmetic
CN104011644B (zh) * 2011-12-22 2017-12-08 英特尔公司 用于产生按照数值顺序的相差恒定跨度的整数的序列的处理器、方法、系统和指令
US10628156B2 (en) 2013-07-09 2020-04-21 Texas Instruments Incorporated Vector SIMD VLIW data path architecture

Also Published As

Publication number Publication date
EP3326060A1 (en) 2018-05-30
US10489155B2 (en) 2019-11-26
US20170024209A1 (en) 2017-01-26
CN107851010A (zh) 2018-03-27
JP6920277B2 (ja) 2021-08-18
EP3326060B1 (en) 2020-03-25
ES2795832T3 (es) 2020-11-24
HUE049260T2 (hu) 2020-09-28
WO2017014892A1 (en) 2017-01-26
JP2018525731A (ja) 2018-09-06
KR20180030986A (ko) 2018-03-27
BR112018001208A2 (pt) 2018-09-11
CN107851010B (zh) 2021-11-12
KR102121866B1 (ko) 2020-06-11

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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