BR112017027664A2 - interface relay sdio única com várias unidades sdio - Google Patents

interface relay sdio única com várias unidades sdio

Info

Publication number
BR112017027664A2
BR112017027664A2 BR112017027664A BR112017027664A BR112017027664A2 BR 112017027664 A2 BR112017027664 A2 BR 112017027664A2 BR 112017027664 A BR112017027664 A BR 112017027664A BR 112017027664 A BR112017027664 A BR 112017027664A BR 112017027664 A2 BR112017027664 A2 BR 112017027664A2
Authority
BR
Brazil
Prior art keywords
sound
unit
audio
units
relay interface
Prior art date
Application number
BR112017027664A
Other languages
English (en)
Inventor
Szeto Victor
Original Assignee
Qualcomm Technologies Int Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Technologies Int Ltd filed Critical Qualcomm Technologies Int Ltd
Publication of BR112017027664A2 publication Critical patent/BR112017027664A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)

Abstract

a presente invenção se refere a um sistema e método que se comunicam com uma de duas ou mais unidades secure digital input output (sdio), das quais apenas uma unidade sdio responde quando está sendo endereçada. a unidade sdio tem uma porta de entrada de clock sdio, uma porta de saída de barramento de dados sdio e uma porta de comando bidirecional sdio. cada unidade sdio tem um indicador de endereço dentro dela, associado com cada unidade sdio. uma unidade sdio não responderá a um comando sdio, a menos que um endereço de unidade sdio codificado no comando sdio corresponda a seu indicador de endereço.
BR112017027664A 2015-06-22 2016-06-16 interface relay sdio única com várias unidades sdio BR112017027664A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/746,036 US9811485B2 (en) 2015-06-22 2015-06-22 Single relay SDIO interface with multiple SDIO units
PCT/EP2016/063949 WO2016207064A1 (en) 2015-06-22 2016-06-16 Single relay sdio interface with multiple sdio units

Publications (1)

Publication Number Publication Date
BR112017027664A2 true BR112017027664A2 (pt) 2018-08-28

Family

ID=56178333

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112017027664A BR112017027664A2 (pt) 2015-06-22 2016-06-16 interface relay sdio única com várias unidades sdio

Country Status (6)

Country Link
US (1) US9811485B2 (pt)
EP (1) EP3311292A1 (pt)
JP (1) JP2018523206A (pt)
CN (1) CN107771328B (pt)
BR (1) BR112017027664A2 (pt)
WO (1) WO2016207064A1 (pt)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110457744B (zh) * 2019-06-27 2023-01-20 山东方寸微电子科技有限公司 一种sd/sdio设备仿真模型框架及其设计方法
CN110971621B (zh) * 2020-01-09 2023-07-11 成都三零嘉微电子有限公司 基于sdio接口的嵌入式多cpu互联电路、互联方法及驱动方法
CN112286446B (zh) * 2020-09-17 2022-12-20 杭州华澜微电子股份有限公司 一种存储装置及其控制方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7225357B2 (en) * 2003-01-21 2007-05-29 Zentek Technology Japan, Inc. SDIO card development system
US20050086413A1 (en) 2003-10-15 2005-04-21 Super Talent Electronics Inc. Capacity Expansion of Flash Memory Device with a Daisy-Chainable Structure and an Integrated Hub
US7873385B2 (en) * 2006-04-05 2011-01-18 Palm, Inc. Antenna sharing techniques
US20090177816A1 (en) * 2008-01-04 2009-07-09 Gerald Marx Method and system for communication with sd memory and sdio devices
WO2009145518A2 (ko) * 2008-05-26 2009-12-03 에스케이텔레콤 주식회사 무선 통신 모듈을 추가한 메모리 카드 및 이를 사용하기 위한 단말기와 ｗｐａｎ 통신 모듈을 가진 메모리 카드 및 이를 사용한 ｗｐａｎ 통신 방법
US9483429B2 (en) * 2008-07-14 2016-11-01 Texas Instruments Incorporated Unified input/output controller for integrated wireless devices
US8856501B2 (en) 2009-12-14 2014-10-07 Sandisk Technologies Inc. Method and system for controlling operation of interconnected devices by circulating host capability without a centralized manager
CN101835282B (zh) * 2010-04-23 2012-11-07 华为终端有限公司 一种无线上网模块、用户终端、安全数码卡、无线通信方法
US8731002B2 (en) 2011-03-25 2014-05-20 Invensense, Inc. Synchronization, re-synchronization, addressing, and serialized signal processing for daisy-chained communication devices
CN102508804A (zh) * 2011-10-20 2012-06-20 豪威科技(上海)有限公司 Sd/sdio主控制器
US20130143622A1 (en) 2011-12-02 2013-06-06 Huizhou Tcl Mobile Communication Co., Ltd. LTE Communication Card and LTE Communication System
EP2645638A1 (en) 2012-03-29 2013-10-02 Robert Bosch Gmbh Communication system with chain or ring topology
US9557802B2 (en) * 2013-08-01 2017-01-31 Mediatek Inc. Method of controlling SDIO device and related SDIO system and SDIO device
US10119713B2 (en) * 2015-01-19 2018-11-06 Lennox Industries Inc. Distributed heating, ventilation, and air conditioning system with concurrent network connections and multi-zone control
US10127172B2 (en) * 2015-06-22 2018-11-13 Qualcomm Technologies International, Ltd. Single SDIO interface with multiple SDIO units
US9830280B2 (en) * 2015-06-22 2017-11-28 Qualcomm Incorporated Multiple access single SDIO interface with multiple SDIO units

Also Published As

Publication number Publication date
EP3311292A1 (en) 2018-04-25
US20160371209A1 (en) 2016-12-22
WO2016207064A1 (en) 2016-12-29
CN107771328A (zh) 2018-03-06
US9811485B2 (en) 2017-11-07
CN107771328B (zh) 2020-09-08
JP2018523206A (ja) 2018-08-16

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Legal Events

Date Code Title Description
B11A Dismissal acc. art.33 of ipl - examination not requested within 36 months of filing
B11Y Definitive dismissal acc. article 33 of ipl - extension of time limit for request of examination expired