BR112017011104A2 - sistemas, aparelhos e métodos para execução de especulação de dados - Google Patents
sistemas, aparelhos e métodos para execução de especulação de dadosInfo
- Publication number
- BR112017011104A2 BR112017011104A2 BR112017011104A BR112017011104A BR112017011104A2 BR 112017011104 A2 BR112017011104 A2 BR 112017011104A2 BR 112017011104 A BR112017011104 A BR 112017011104A BR 112017011104 A BR112017011104 A BR 112017011104A BR 112017011104 A2 BR112017011104 A2 BR 112017011104A2
- Authority
- BR
- Brazil
- Prior art keywords
- dsx
- systems
- methods
- hardware
- instruction
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
- G06F9/528—Mutual exclusion algorithms by using speculative mechanisms
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
?sistemas, aparelhos e métodos para execução de especulação de dados? são descritos sistemas, métodos e aparelhos para execução de especulação de dados (dsx). em algumas modalidades, um aparelho de hardware para realizar dsx compreende um decodificador de hardware para decodificar uma instrução, em, que a instrução inclui um código de operação e um operando para armazenar uma porção de um endereço de fallback, hardware de execução para executar a instrução decodificada para iniciar uma região de execução especulativa de dados (dsx) por meio da ativação de hardware de rastreamento de dsx para rastrear acessos de memória especulativa e para detectar violações de ordenamento na região de dsx, e armazenar o endereço de fallback.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/582,717 US10303525B2 (en) | 2014-12-24 | 2014-12-24 | Systems, apparatuses, and methods for data speculation execution |
PCT/US2015/062249 WO2016105786A1 (en) | 2014-12-24 | 2015-11-24 | Systems, apparatuses, and methods for data speculation execution |
Publications (1)
Publication Number | Publication Date |
---|---|
BR112017011104A2 true BR112017011104A2 (pt) | 2017-12-26 |
Family
ID=56151336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BR112017011104A BR112017011104A2 (pt) | 2014-12-24 | 2015-11-24 | sistemas, aparelhos e métodos para execução de especulação de dados |
Country Status (9)
Country | Link |
---|---|
US (1) | US10303525B2 (pt) |
EP (1) | EP3238032A4 (pt) |
JP (1) | JP6867082B2 (pt) |
KR (1) | KR102453594B1 (pt) |
CN (1) | CN107003853B (pt) |
BR (1) | BR112017011104A2 (pt) |
SG (1) | SG11201704300TA (pt) |
TW (1) | TWI657371B (pt) |
WO (1) | WO2016105786A1 (pt) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10942744B2 (en) | 2014-12-24 | 2021-03-09 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061583B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10387158B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10387156B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061589B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
WO2017086983A1 (en) * | 2015-11-19 | 2017-05-26 | Hewlett Packard Enterprise Development Lp | Prediction models for concurrency control types |
GB2554096B (en) * | 2016-09-20 | 2019-03-20 | Advanced Risc Mach Ltd | Handling of inter-element address hazards for vector instructions |
CN107506329B (zh) * | 2017-08-18 | 2018-06-19 | 浙江大学 | 一种自动支持循环迭代流水线的粗粒度可重构阵列及其配置方法 |
WO2020119050A1 (en) | 2018-12-11 | 2020-06-18 | Huawei Technologies Co., Ltd. | Write-write conflict detection for multi-master shared storage database |
CN114489518B (zh) * | 2022-03-28 | 2022-09-09 | 山东大学 | 测序数据质量控制方法及系统 |
Family Cites Families (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4864930A (en) | 1985-05-09 | 1989-09-12 | Graphics Microsystems, Inc. | Ink control system |
US5511172A (en) | 1991-11-15 | 1996-04-23 | Matsushita Electric Co. Ind, Ltd. | Speculative execution processor |
DE69327688T2 (de) | 1992-08-12 | 2000-09-07 | Advanced Micro Devices Inc | Befehlsdecoder |
JP3670290B2 (ja) | 1995-02-14 | 2005-07-13 | 富士通株式会社 | 特殊機能を提供する高性能投機的実行プロセッサの構造及び方法 |
US5872947A (en) | 1995-10-24 | 1999-02-16 | Advanced Micro Devices, Inc. | Instruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructions |
KR100203131B1 (ko) | 1996-06-24 | 1999-06-15 | 김영환 | 반도체 소자의 초저접합 형성방법 |
US6128703A (en) | 1997-09-05 | 2000-10-03 | Integrated Device Technology, Inc. | Method and apparatus for memory prefetch operation of volatile non-coherent data |
US6640315B1 (en) | 1999-06-26 | 2003-10-28 | Board Of Trustees Of The University Of Illinois | Method and apparatus for enhancing instruction level parallelism |
US6748589B1 (en) | 1999-10-20 | 2004-06-08 | Transmeta Corporation | Method for increasing the speed of speculative execution |
US6629234B1 (en) | 2000-03-30 | 2003-09-30 | Ip. First, L.L.C. | Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction |
US6854048B1 (en) | 2001-08-08 | 2005-02-08 | Sun Microsystems | Speculative execution control with programmable indicator and deactivation of multiaccess recovery mechanism |
US7117347B2 (en) | 2001-10-23 | 2006-10-03 | Ip-First, Llc | Processor including fallback branch prediction mechanism for far jump and far call instructions |
US6845442B1 (en) | 2002-04-30 | 2005-01-18 | Advanced Micro Devices, Inc. | System and method of using speculative operand sources in order to speculatively bypass load-store operations |
US6950925B1 (en) | 2002-08-28 | 2005-09-27 | Advanced Micro Devices, Inc. | Scheduler for use in a microprocessor that supports data-speculative execution |
US20040049657A1 (en) * | 2002-09-10 | 2004-03-11 | Kling Ralph M. | Extended register space apparatus and methods for processors |
TWI231450B (en) | 2002-10-22 | 2005-04-21 | Ip First Llc | Processor including fallback branch prediction mechanism for far jump and far call instructions |
US6862664B2 (en) | 2003-02-13 | 2005-03-01 | Sun Microsystems, Inc. | Method and apparatus for avoiding locks by speculatively executing critical sections |
US20040163082A1 (en) | 2003-02-13 | 2004-08-19 | Marc Tremblay | Commit instruction to support transactional program execution |
US7363470B2 (en) | 2003-05-02 | 2008-04-22 | Advanced Micro Devices, Inc. | System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor |
US7185323B2 (en) | 2003-05-16 | 2007-02-27 | Sun Microsystems, Inc. | Using value speculation to break constraining dependencies in iterative control flow structures |
US7500087B2 (en) | 2004-03-09 | 2009-03-03 | Intel Corporation | Synchronization of parallel processes using speculative execution of synchronization instructions |
US20070006195A1 (en) | 2004-03-31 | 2007-01-04 | Christof Braun | Method and structure for explicit software control of data speculation |
TWI305323B (en) | 2004-08-23 | 2009-01-11 | Faraday Tech Corp | Method for verification branch prediction mechanisms and readable recording medium for storing program thereof |
US7856537B2 (en) | 2004-09-30 | 2010-12-21 | Intel Corporation | Hybrid hardware and software implementation of transactional memory access |
US20070118696A1 (en) | 2005-11-22 | 2007-05-24 | Intel Corporation | Register tracking for speculative prefetching |
US7404041B2 (en) | 2006-02-10 | 2008-07-22 | International Business Machines Corporation | Low complexity speculative multithreading system based on unmodified microprocessor core |
CN100568173C (zh) * | 2006-09-01 | 2009-12-09 | 上海大学 | 多微控制器系统任务调用方法 |
US7711678B2 (en) * | 2006-11-17 | 2010-05-04 | Microsoft Corporation | Software transaction commit order and conflict management |
US7681015B2 (en) | 2007-01-30 | 2010-03-16 | Nema Labs Ab | Generating and comparing memory access ranges for speculative throughput computing |
JP5154119B2 (ja) | 2007-03-26 | 2013-02-27 | テレフオンアクチーボラゲット エル エム エリクソン(パブル) | プロセッサ |
US9075622B2 (en) | 2008-01-23 | 2015-07-07 | Arm Limited | Reducing errors in pre-decode caches |
CN101546282B (zh) * | 2008-03-28 | 2011-05-18 | 国际商业机器公司 | 用于在处理器中执行写拷贝的方法和设备 |
US8739141B2 (en) | 2008-05-19 | 2014-05-27 | Oracle America, Inc. | Parallelizing non-countable loops with hardware transactional memory |
WO2010014200A1 (en) | 2008-07-28 | 2010-02-04 | Advanced Micro Devices, Inc. | Virtualizable advanced synchronization facility |
US9569254B2 (en) | 2009-07-28 | 2017-02-14 | International Business Machines Corporation | Automatic checkpointing and partial rollback in software transaction memory |
US20120227045A1 (en) | 2009-12-26 | 2012-09-06 | Knauth Laura A | Method, apparatus, and system for speculative execution event counter checkpointing and restoring |
US8438571B2 (en) | 2010-02-24 | 2013-05-07 | International Business Machines Corporation | Thread speculative execution and asynchronous conflict |
CN101872299B (zh) * | 2010-07-06 | 2013-05-01 | 浙江大学 | 冲突预测实现方法及所用冲突预测处理装置事务存储器 |
US20120079245A1 (en) | 2010-09-25 | 2012-03-29 | Cheng Wang | Dynamic optimization for conditional commit |
US10387324B2 (en) | 2011-12-08 | 2019-08-20 | Intel Corporation | Method, apparatus, and system for efficiently handling multiple virtual address mappings during transactional execution canceling the transactional execution upon conflict between physical addresses of transactional accesses within the transactional execution |
CN102725741B (zh) * | 2011-12-31 | 2014-11-05 | 华为技术有限公司 | 高速缓冲存储器控制方法、装置和系统 |
US9268596B2 (en) | 2012-02-02 | 2016-02-23 | Intel Corparation | Instruction and logic to test transactional execution status |
WO2013115818A1 (en) | 2012-02-02 | 2013-08-08 | Intel Corporation | A method, apparatus, and system for transactional speculation control instructions |
WO2013115816A1 (en) | 2012-02-02 | 2013-08-08 | Intel Corporation | A method, apparatus, and system for speculative abort control mechanisms |
US9652242B2 (en) | 2012-05-02 | 2017-05-16 | Apple Inc. | Apparatus for predicate calculation in processor instruction set |
US8688661B2 (en) * | 2012-06-15 | 2014-04-01 | International Business Machines Corporation | Transactional processing |
US9298631B2 (en) | 2012-06-15 | 2016-03-29 | International Business Machines Corporation | Managing transactional and non-transactional store observability |
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US9811340B2 (en) | 2012-06-18 | 2017-11-07 | Intel Corporation | Method and apparatus for reconstructing real program order of instructions in multi-strand out-of-order processor |
US9396115B2 (en) | 2012-08-02 | 2016-07-19 | International Business Machines Corporation | Rewind only transactions in a data processing system supporting transactional storage accesses |
US9367471B2 (en) | 2012-09-10 | 2016-06-14 | Apple Inc. | Fetch width predictor |
GB2519107B (en) * | 2013-10-09 | 2020-05-13 | Advanced Risc Mach Ltd | A data processing apparatus and method for performing speculative vector access operations |
US9262206B2 (en) | 2014-02-27 | 2016-02-16 | International Business Machines Corporation | Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments |
US9454370B2 (en) | 2014-03-14 | 2016-09-27 | International Business Machines Corporation | Conditional transaction end instruction |
US10387156B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US20160357556A1 (en) | 2014-12-24 | 2016-12-08 | Elmoustapha Ould-Ahmed-Vall | Systems, apparatuses, and methods for data speculation execution |
US9785442B2 (en) | 2014-12-24 | 2017-10-10 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061583B2 (en) * | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10387158B2 (en) | 2014-12-24 | 2019-08-20 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
US10061589B2 (en) | 2014-12-24 | 2018-08-28 | Intel Corporation | Systems, apparatuses, and methods for data speculation execution |
-
2014
- 2014-12-24 US US14/582,717 patent/US10303525B2/en active Active
-
2015
- 2015-11-23 TW TW104138794A patent/TWI657371B/zh active
- 2015-11-24 BR BR112017011104A patent/BR112017011104A2/pt not_active Application Discontinuation
- 2015-11-24 WO PCT/US2015/062249 patent/WO2016105786A1/en active Application Filing
- 2015-11-24 EP EP15873991.2A patent/EP3238032A4/en not_active Ceased
- 2015-11-24 SG SG11201704300TA patent/SG11201704300TA/en unknown
- 2015-11-24 CN CN201580064697.1A patent/CN107003853B/zh active Active
- 2015-11-24 JP JP2017526678A patent/JP6867082B2/ja active Active
- 2015-11-24 KR KR1020177014244A patent/KR102453594B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
EP3238032A4 (en) | 2018-08-15 |
JP6867082B2 (ja) | 2021-04-28 |
SG11201704300TA (en) | 2017-07-28 |
TWI657371B (zh) | 2019-04-21 |
CN107003853A (zh) | 2017-08-01 |
US20160188382A1 (en) | 2016-06-30 |
JP2017539008A (ja) | 2017-12-28 |
EP3238032A1 (en) | 2017-11-01 |
WO2016105786A1 (en) | 2016-06-30 |
KR20170098803A (ko) | 2017-08-30 |
CN107003853B (zh) | 2020-12-22 |
KR102453594B1 (ko) | 2022-10-12 |
US10303525B2 (en) | 2019-05-28 |
TW201643700A (zh) | 2016-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
BR112017011104A2 (pt) | sistemas, aparelhos e métodos para execução de especulação de dados | |
CL2017003263A1 (es) | Arquitectura basada en bloques con ejecución paralela de bloques sucesivos. | |
BR112017016219A2 (pt) | rastreamento de fluxo de dados através de monitoramento de memória | |
CL2015002234A1 (es) | Codificador y decodificador de audio con programa de informacion o metadatos de la estructura de la subcorriente. | |
FI20165256A (fi) | Laitteisto, menetelmä ja tietokoneohjelma videokoodaukseen ja -dekoodaukseen | |
BR112018006098A2 (pt) | sistemas e métodos para processamento de vídeo | |
WO2016003820A3 (en) | System and methods for expandably wide operand instructions | |
FI20165114A (fi) | Laitteisto, menetelmä ja tietokoneohjelma videokoodausta ja videokoodauksen purkua varten | |
BR112015030001A2 (pt) | instruções de acesso à memória de múltiplos registradores, processadores, métodos e sistemas | |
JP2017516228A5 (pt) | ||
BR112015030098A2 (pt) | métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados | |
WO2013188120A3 (en) | Zero cycle load | |
GB2549883A (en) | Advanced processor architecture | |
GB2517877A (en) | Controlling an order for processing data elements during vector processing | |
BR112017025783A2 (pt) | sistemas e métodos de pagamento multimodo | |
WO2014139466A3 (en) | Data cache system and method | |
BR112012028406A2 (pt) | método, pelo menos uma memória e pelo menos um código de programa de computador configurados, com pelo menos um processadro de dados e aparelho | |
BR112013031001A2 (pt) | método, programa de computador e aparelho | |
JP2016509714A5 (pt) | ||
BR112018007547A2 (pt) | adaptação relacionada à tela de conteúdo ambisonic de alta ordem (hoa) | |
GB201302373D0 (en) | Speculative load issue | |
WO2011086473A3 (en) | Hardware virtualization for media processing | |
NZ738808A (en) | Wireless access tag duplication system and method | |
BR112018072180A2 (pt) | metódos para codificar e decodificar utilizando um código polar, codificador de informação, decodificador de informação e mémória legível por computador | |
BR112017011910A2 (pt) | método para acessar dados em uma memória em um endereço não alinhado |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
B11B | Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements |