BR112015030098A2 - métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados - Google Patents

métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados

Info

Publication number
BR112015030098A2
BR112015030098A2 BR112015030098A BR112015030098A BR112015030098A2 BR 112015030098 A2 BR112015030098 A2 BR 112015030098A2 BR 112015030098 A BR112015030098 A BR 112015030098A BR 112015030098 A BR112015030098 A BR 112015030098A BR 112015030098 A2 BR112015030098 A2 BR 112015030098A2
Authority
BR
Brazil
Prior art keywords
compressed data
mode
instruction
instructions
masked
Prior art date
Application number
BR112015030098A
Other languages
English (en)
Other versions
BR112015030098B1 (pt
Inventor
L Toll Bret
M Guy Buford
Naik Mishali
Singhal Ronak
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112015030098A2 publication Critical patent/BR112015030098A2/pt
Publication of BR112015030098B1 publication Critical patent/BR112015030098B1/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)

Abstract

“métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados” trata-se de um processador que inclui um primeiro modo no qual o processador não deve usar mascaramento de operação de dados compactados e um segundo modo no qual o processador deve usar mascaramento de operação de dados compactados. uma unidade de decodificação para decodificar uma instrução de dados compactados não mascarada para uma determinada operação de dados compactados no primeiro modo e para decodificar uma instrução de dados compactados mascarada para uma versão mascarada da determinada operação de dados compactados no segundo modo. as instruções têm um mesmo comprimento de instrução. a instrução mascarada tem bit(s) para especificar uma máscara. a(s) unidade(s) de execução são acopladas à unidade de decodificação. a(s) unidade(s) de execução, em resposta à unidade de decodificação que decodifica a instrução não mascarada no primeiro modo, deve(devem) realizar a determinada operação de dados compactados. a(s) unidade(s) de execução, em resposta à unidade de decodificação que decodifica a instrução mascarada no segundo modo, deve(devem) realizar a versão mascarada da certa operação de dados compactados.
BR112015030098-7A 2013-06-26 2014-06-17 Métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados BR112015030098B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/931,739 US9990202B2 (en) 2013-06-28 2013-06-28 Packed data element predication processors, methods, systems, and instructions
US13/931,739 2013-06-28
PCT/US2014/042797 WO2014209687A1 (en) 2013-06-28 2014-06-17 Packed data element predication processors, methods, systems, and instructions

Publications (2)

Publication Number Publication Date
BR112015030098A2 true BR112015030098A2 (pt) 2017-07-25
BR112015030098B1 BR112015030098B1 (pt) 2022-04-26

Family

ID=52116850

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112015030098-7A BR112015030098B1 (pt) 2013-06-26 2014-06-17 Métodos, sistemas e instruções de processadores de predicação de elemento de dados compactados

Country Status (8)

Country Link
US (5) US9990202B2 (pt)
EP (1) EP3014418B1 (pt)
KR (2) KR20180006501A (pt)
CN (1) CN105247475B (pt)
BR (1) BR112015030098B1 (pt)
RU (1) RU2612597C1 (pt)
TW (1) TWI536187B (pt)
WO (1) WO2014209687A1 (pt)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9477467B2 (en) 2013-03-30 2016-10-25 Intel Corporation Processors, methods, and systems to implement partial register accesses with masked full register accesses
US9990202B2 (en) 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions
US10001995B2 (en) * 2015-06-02 2018-06-19 Intel Corporation Packed data alignment plus compute instructions, processors, methods, and systems
US10459723B2 (en) * 2015-07-20 2019-10-29 Qualcomm Incorporated SIMD instructions for multi-stage cube networks
US9785800B2 (en) 2015-12-23 2017-10-10 Intel Corporation Non-tracked control transfers within control transfer enforcement
US20170185400A1 (en) 2015-12-23 2017-06-29 Intel Corporation Mode-specific endbranch for control flow termination
US20170192781A1 (en) * 2015-12-30 2017-07-06 Robert Valentine Systems, Apparatuses, and Methods for Strided Loads
US11204764B2 (en) * 2016-03-31 2021-12-21 Intel Corporation Processors, methods, systems, and instructions to Partition a source packed data into lanes
US10891131B2 (en) * 2016-09-22 2021-01-12 Intel Corporation Processors, methods, systems, and instructions to consolidate data elements and generate index updates
WO2018112193A1 (en) 2016-12-14 2018-06-21 Novetechnologies, LLC Livestock biosecurity system and method of use
RU2659492C1 (ru) * 2017-08-18 2018-07-02 Федеральное государственное бюджетное образовательное учреждение высшего образования "Вятский государственный университет" (ВятГУ) Блок унификации с параллельным сопоставлением термов
US10678540B2 (en) * 2018-05-08 2020-06-09 Arm Limited Arithmetic operation with shift
DE102018113475A1 (de) * 2018-06-06 2019-12-12 Infineon Technologies Ag Rechenwerk zum rechnen mit maskierten daten
US11328209B1 (en) 2021-06-02 2022-05-10 SambaNova Systems, Inc. Dual cycle tensor dropout in a neural network
US11256987B1 (en) 2021-06-02 2022-02-22 SambaNova Systems, Inc. Memory efficient dropout, with reordering of dropout mask elements

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903228A (en) * 1988-11-09 1990-02-20 International Business Machines Corporation Single cycle merge/logic unit
CA2045705A1 (en) * 1990-06-29 1991-12-30 Richard Lee Sites In-register data manipulation in reduced instruction set processor
US5787303A (en) * 1991-10-31 1998-07-28 Kabushiki Kaisha Toshiba Digital computer system capable of processing a plurality of instructions in parallel based on a VLIW architecture
US5606677A (en) * 1992-11-30 1997-02-25 Texas Instruments Incorporated Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
US5781457A (en) * 1994-03-08 1998-07-14 Exponential Technology, Inc. Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU
CA2156889C (en) 1994-09-30 1999-11-02 Edward L. Schwartz Method and apparatus for encoding and decoding data
CN101794212B (zh) 1995-08-31 2015-01-07 英特尔公司 控制移位分组数据的位校正的装置
US6052769A (en) 1998-03-31 2000-04-18 Intel Corporation Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6484255B1 (en) 1999-09-20 2002-11-19 Intel Corporation Selective writing of data elements from packed data based upon a mask using predication
US6629115B1 (en) * 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US7127593B2 (en) * 2001-06-11 2006-10-24 Broadcom Corporation Conditional execution with multiple destination stores
US7017032B2 (en) 2001-06-11 2006-03-21 Broadcom Corporation Setting execution conditions
US6986023B2 (en) 2002-08-09 2006-01-10 Intel Corporation Conditional execution of coprocessor instruction based on main processor arithmetic flags
US7002595B2 (en) * 2002-10-04 2006-02-21 Broadcom Corporation Processing of color graphics data
US20050149701A1 (en) 2003-12-24 2005-07-07 Inching Chen Method, apparatus and system for pair-wise minimum and minimum mask instructions
US7873812B1 (en) * 2004-04-05 2011-01-18 Tibet MIMAR Method and system for efficient matrix multiplication in a SIMD processor architecture
US20070186210A1 (en) * 2006-02-06 2007-08-09 Via Technologies, Inc. Instruction set encoding in a dual-mode computer processing environment
US20080016320A1 (en) * 2006-06-27 2008-01-17 Amitabh Menon Vector Predicates for Sub-Word Parallel Operations
US7676647B2 (en) * 2006-08-18 2010-03-09 Qualcomm Incorporated System and method of processing data using scalar/vector instructions
US8180998B1 (en) * 2007-09-10 2012-05-15 Nvidia Corporation System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations
US9529592B2 (en) * 2007-12-27 2016-12-27 Intel Corporation Vector mask memory access instructions to perform individual and sequential memory access operations if an exception occurs during a full width memory access operation
US8156391B2 (en) 2008-05-27 2012-04-10 Lsi Corporation Data controlling in the MBIST chain architecture
US8434074B2 (en) * 2010-02-24 2013-04-30 Intel Corporation Register allocation with SIMD architecture using write masks
US8667042B2 (en) * 2010-09-24 2014-03-04 Intel Corporation Functional unit for vector integer multiply add instruction
US9600285B2 (en) 2011-12-22 2017-03-21 Intel Corporation Packed data operation mask concatenation processors, methods, systems and instructions
JP2013186547A (ja) * 2012-03-06 2013-09-19 Fujitsu Ltd 演算処理装置、携帯端末および演算処理方法
US20130339680A1 (en) * 2012-06-15 2013-12-19 International Business Machines Corporation Nontransactional store instruction
US9256427B2 (en) * 2012-12-11 2016-02-09 International Business Machines Corporation Tracking multiple conditions in a general purpose register and instruction therefor
US9990202B2 (en) * 2013-06-28 2018-06-05 Intel Corporation Packed data element predication processors, methods, systems, and instructions

Also Published As

Publication number Publication date
BR112015030098B1 (pt) 2022-04-26
US20150006858A1 (en) 2015-01-01
KR20150141999A (ko) 2015-12-21
EP3014418A4 (en) 2017-03-08
US20200026518A1 (en) 2020-01-23
WO2014209687A1 (en) 2014-12-31
US10430193B2 (en) 2019-10-01
US20230108016A1 (en) 2023-04-06
EP3014418B1 (en) 2020-11-18
US20180293074A1 (en) 2018-10-11
CN105247475B (zh) 2019-11-15
TW201508521A (zh) 2015-03-01
CN105247475A (zh) 2016-01-13
US9990202B2 (en) 2018-06-05
US10963257B2 (en) 2021-03-30
RU2612597C1 (ru) 2017-03-09
US20210216325A1 (en) 2021-07-15
KR20180006501A (ko) 2018-01-17
EP3014418A1 (en) 2016-05-04
US11442734B2 (en) 2022-09-13
TWI536187B (zh) 2016-06-01

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B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 17/06/2014, OBSERVADAS AS CONDICOES LEGAIS.