BR112015029108B1 - Controlador de memória, método e meio de armazenamento em computador para sistemas de armazenamento e memória tornada pseudônimo - Google Patents

Controlador de memória, método e meio de armazenamento em computador para sistemas de armazenamento e memória tornada pseudônimo Download PDF

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Publication number
BR112015029108B1
BR112015029108B1 BR112015029108-2A BR112015029108A BR112015029108B1 BR 112015029108 B1 BR112015029108 B1 BR 112015029108B1 BR 112015029108 A BR112015029108 A BR 112015029108A BR 112015029108 B1 BR112015029108 B1 BR 112015029108B1
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Brazil
Prior art keywords
memory
block
data
request
storage system
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BR112015029108-2A
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English (en)
Portuguese (pt)
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BR112015029108A2 (pt
Inventor
William R. Tipton
Surendra Verma
Landy Wang
Malcolm James Smith
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Microsoft Technology Licensing, Llc
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Application filed by Microsoft Technology Licensing, Llc filed Critical Microsoft Technology Licensing, Llc
Publication of BR112015029108A2 publication Critical patent/BR112015029108A2/pt
Publication of BR112015029108B1 publication Critical patent/BR112015029108B1/pt

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    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614Improving the reliability of storage systems
    • G06F3/0619Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065Replication mechanisms
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21Employing a record carrier using a specific recording technology
    • G06F2212/214Solid state disk

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Memory System (AREA)
BR112015029108-2A 2013-05-29 2014-05-28 Controlador de memória, método e meio de armazenamento em computador para sistemas de armazenamento e memória tornada pseudônimo BR112015029108B1 (pt)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361828636P 2013-05-29 2013-05-29
US61/828,636 2013-05-29
US14/036,298 2013-09-25
US14/036,298 US9678689B2 (en) 2013-05-29 2013-09-25 Storage systems and aliased memory
PCT/US2014/039634 WO2014193862A2 (en) 2013-05-29 2014-05-28 Storage systems and aliased memory

Publications (2)

Publication Number Publication Date
BR112015029108A2 BR112015029108A2 (pt) 2017-07-25
BR112015029108B1 true BR112015029108B1 (pt) 2022-05-17

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BR112015029108-2A BR112015029108B1 (pt) 2013-05-29 2014-05-28 Controlador de memória, método e meio de armazenamento em computador para sistemas de armazenamento e memória tornada pseudônimo

Country Status (8)

Country Link
US (2) US9678689B2 (https=)
EP (1) EP3005126B1 (https=)
JP (1) JP6324494B2 (https=)
CN (1) CN105339909B (https=)
BR (1) BR112015029108B1 (https=)
ES (1) ES2865575T3 (https=)
RU (1) RU2669008C2 (https=)
WO (1) WO2014193862A2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
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US9678689B2 (en) * 2013-05-29 2017-06-13 Microsoft Technology Licensing, Llc Storage systems and aliased memory
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US9740414B2 (en) * 2015-10-29 2017-08-22 Pure Storage, Inc. Optimizing copy operations
KR20170076878A (ko) * 2015-12-24 2017-07-05 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
US10210088B2 (en) 2015-12-28 2019-02-19 Nxp Usa, Inc. Computing system with a cache invalidation unit, a cache invalidation unit and a method of operating a cache invalidation unit in a computing system
US11237758B2 (en) * 2016-08-06 2022-02-01 Wolley Inc. Apparatus and method of wear leveling for storage class memory using address cache
US10387304B2 (en) * 2017-12-28 2019-08-20 Intel Corporation Virtual transfer of data between memory and storage domains
TWI771926B (zh) * 2021-02-25 2022-07-21 慧榮科技股份有限公司 資料儲存裝置以及非揮發式記憶體控制方法

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JPH05158782A (ja) * 1991-12-06 1993-06-25 Hitachi Ltd 記憶装置
US6438672B1 (en) * 1999-06-03 2002-08-20 Agere Systems Guardian Corp. Memory aliasing method and apparatus
US6611907B1 (en) * 1999-10-21 2003-08-26 Matsushita Electric Industrial Co., Ltd. Semiconductor memory card access apparatus, a computer-readable recording medium, an initialization method, and a semiconductor memory card
US6625725B1 (en) * 1999-12-22 2003-09-23 Intel Corporation Speculative reuse of code regions
GB2372589B (en) * 2001-02-21 2003-01-22 3Com Corp Memory aliasing in a processor system
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JP2004362464A (ja) * 2003-06-06 2004-12-24 Sony Corp 不揮発メモリを利用したコンピュータシステム
US20050138307A1 (en) * 2003-12-18 2005-06-23 Grimsrud Knut S. Storage performance improvement using data replication on a disk
US20110029723A1 (en) 2004-08-06 2011-02-03 Super Talent Electronics, Inc. Non-Volatile Memory Based Computer Systems
US8417915B2 (en) * 2005-08-05 2013-04-09 Arm Limited Alias management within a virtually indexed and physically tagged cache memory
US7872657B1 (en) * 2006-06-16 2011-01-18 Nvidia Corporation Memory addressing scheme using partition strides
US7747817B2 (en) * 2006-06-28 2010-06-29 Unity Semiconductor Corporation Performing data operations using non-volatile third dimension memory
JP4783229B2 (ja) * 2006-07-19 2011-09-28 パナソニック株式会社 キャッシュメモリシステム
JP2009009665A (ja) * 2007-06-29 2009-01-15 Elpida Memory Inc 半導体記憶装置
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US9678689B2 (en) * 2013-05-29 2017-06-13 Microsoft Technology Licensing, Llc Storage systems and aliased memory

Also Published As

Publication number Publication date
CN105339909B (zh) 2018-08-24
EP3005126A2 (en) 2016-04-13
US20170262207A1 (en) 2017-09-14
RU2669008C2 (ru) 2018-10-05
EP3005126B1 (en) 2021-03-31
ES2865575T3 (es) 2021-10-15
WO2014193862A2 (en) 2014-12-04
US20140359203A1 (en) 2014-12-04
BR112015029108A2 (pt) 2017-07-25
US10216437B2 (en) 2019-02-26
RU2015151012A (ru) 2017-06-01
JP6324494B2 (ja) 2018-05-16
CN105339909A (zh) 2016-02-17
JP2016524228A (ja) 2016-08-12
WO2014193862A3 (en) 2015-04-09
US9678689B2 (en) 2017-06-13

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B350 Update of information on the portal [chapter 15.35 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

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B21F Lapse acc. art. 78, item iv - on non-payment of the annual fees in time

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