BR112013015793A2 - método, núcleo de processamento implementado em um chip semicondutor e sistema de computação - Google Patents

método, núcleo de processamento implementado em um chip semicondutor e sistema de computação

Info

Publication number
BR112013015793A2
BR112013015793A2 BR112013015793A BR112013015793A BR112013015793A2 BR 112013015793 A2 BR112013015793 A2 BR 112013015793A2 BR 112013015793 A BR112013015793 A BR 112013015793A BR 112013015793 A BR112013015793 A BR 112013015793A BR 112013015793 A2 BR112013015793 A2 BR 112013015793A2
Authority
BR
Brazil
Prior art keywords
semiconductor chip
computing system
core processing
processing implemented
implemented
Prior art date
Application number
BR112013015793A
Other languages
English (en)
Inventor
T Forsyth Andrew
J Hughes Christopher
Ido Hideki
Wiedemeier Jeffrey
Corbal Jesus
C Hall Jonathan
J Charney Mark
B Girkar Milind
Valentine Robert
Chen Yen-Kuang
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of BR112013015793A2 publication Critical patent/BR112013015793A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
BR112013015793A 2010-12-22 2011-12-05 método, núcleo de processamento implementado em um chip semicondutor e sistema de computação BR112013015793A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/976,616 US8972698B2 (en) 2010-12-22 2010-12-22 Vector conflict instructions
PCT/US2011/063307 WO2012087548A2 (en) 2010-12-22 2011-12-05 Vector conflict instructions

Publications (1)

Publication Number Publication Date
BR112013015793A2 true BR112013015793A2 (pt) 2017-08-01

Family

ID=46314722

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112013015793A BR112013015793A2 (pt) 2010-12-22 2011-12-05 método, núcleo de processamento implementado em um chip semicondutor e sistema de computação

Country Status (8)

Country Link
US (1) US8972698B2 (pt)
JP (2) JP2014504418A (pt)
KR (1) KR101494559B1 (pt)
CN (1) CN103502934B (pt)
BR (1) BR112013015793A2 (pt)
DE (1) DE112011104555B4 (pt)
GB (1) GB2500337B (pt)
WO (1) WO2012087548A2 (pt)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012134532A1 (en) 2011-04-01 2012-10-04 Intel Corporation Vector friendly instruction format and execution thereof
US20120260062A1 (en) * 2011-04-07 2012-10-11 International Business Machines Corporation System and method for providing dynamic addressability of data elements in a register file with subword parallelism
US9021233B2 (en) 2011-09-28 2015-04-28 Arm Limited Interleaving data accesses issued in response to vector access instructions
WO2013081588A1 (en) * 2011-11-30 2013-06-06 Intel Corporation Instruction and logic to provide vector horizontal compare functionality
US10318291B2 (en) 2011-11-30 2019-06-11 Intel Corporation Providing vector horizontal compare functionality within a vector register
CN104011670B (zh) 2011-12-22 2016-12-28 英特尔公司 用于基于向量写掩码的内容而在通用寄存器中存储两个标量常数之一的指令
WO2013095672A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Multi-register gather instruction
CN104137059B (zh) * 2011-12-23 2018-10-09 英特尔公司 多寄存器分散指令
US10678541B2 (en) * 2011-12-29 2020-06-09 Intel Corporation Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions
US9588762B2 (en) 2012-03-15 2017-03-07 International Business Machines Corporation Vector find element not equal instruction
US9459867B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a specified memory boundary indicated by the instruction
US9715383B2 (en) 2012-03-15 2017-07-25 International Business Machines Corporation Vector find element equal instruction
US9459864B2 (en) * 2012-03-15 2016-10-04 International Business Machines Corporation Vector string range compare
US9268566B2 (en) 2012-03-15 2016-02-23 International Business Machines Corporation Character data match determination by loading registers at most up to memory block boundary and comparing
US9280347B2 (en) 2012-03-15 2016-03-08 International Business Machines Corporation Transforming non-contiguous instruction specifiers to contiguous instruction specifiers
US9454367B2 (en) 2012-03-15 2016-09-27 International Business Machines Corporation Finding the length of a set of character data having a termination character
US9454366B2 (en) 2012-03-15 2016-09-27 International Business Machines Corporation Copying character data having a termination character from one memory location to another
US9459868B2 (en) 2012-03-15 2016-10-04 International Business Machines Corporation Instruction to load data up to a dynamically determined memory boundary
US9710266B2 (en) 2012-03-15 2017-07-18 International Business Machines Corporation Instruction to compute the distance to a specified memory boundary
US10095516B2 (en) 2012-06-29 2018-10-09 Intel Corporation Vector multiplication with accumulation in large register space
US9355068B2 (en) * 2012-06-29 2016-05-31 Intel Corporation Vector multiplication with operand base system conversion and re-conversion
US9298456B2 (en) * 2012-08-21 2016-03-29 Apple Inc. Mechanism for performing speculative predicated instructions
US9842046B2 (en) 2012-09-28 2017-12-12 Intel Corporation Processing memory access instructions that have duplicate memory indices
US9665368B2 (en) * 2012-09-28 2017-05-30 Intel Corporation Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register
KR101877190B1 (ko) 2012-12-26 2018-07-10 인텔 코포레이션 인접한 수집/분산 연산들의 통합
US9442723B2 (en) * 2012-12-28 2016-09-13 Intel Corporation Method and apparatus for integral image computation instructions
US9804839B2 (en) * 2012-12-28 2017-10-31 Intel Corporation Instruction for determining histograms
US9411592B2 (en) 2012-12-29 2016-08-09 Intel Corporation Vector address conflict resolution with vector population count functionality
US9411584B2 (en) * 2012-12-29 2016-08-09 Intel Corporation Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality
US9372692B2 (en) 2012-12-29 2016-06-21 Intel Corporation Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
US20140281418A1 (en) * 2013-03-14 2014-09-18 Shihjong J. Kuo Multiple Data Element-To-Multiple Data Element Comparison Processors, Methods, Systems, and Instructions
US9348589B2 (en) 2013-03-19 2016-05-24 Apple Inc. Enhanced predicate registers having predicates corresponding to element widths
US9817663B2 (en) 2013-03-19 2017-11-14 Apple Inc. Enhanced Macroscalar predicate operations
US9880839B2 (en) * 2014-04-24 2018-01-30 Intel Corporation Instruction that performs a scatter write
JP6253514B2 (ja) 2014-05-27 2017-12-27 ルネサスエレクトロニクス株式会社 プロセッサ
US9891913B2 (en) * 2014-12-23 2018-02-13 Intel Corporation Method and apparatus for performing conflict detection using vector comparison operations
US20160179550A1 (en) * 2014-12-23 2016-06-23 Intel Corporation Fast vector dynamic memory conflict detection
US10203955B2 (en) * 2014-12-31 2019-02-12 Intel Corporation Methods, apparatus, instructions and logic to provide vector packed tuple cross-comparison functionality
US10423411B2 (en) 2015-09-26 2019-09-24 Intel Corporation Data element comparison processors, methods, systems, and instructions
US20170185413A1 (en) * 2015-12-23 2017-06-29 Intel Corporation Processing devices to perform a conjugate permute instruction
EP3394761B1 (en) * 2015-12-24 2023-08-30 Intel Corporation Conflict mask generation
CN111176608A (zh) * 2016-04-26 2020-05-19 中科寒武纪科技股份有限公司 一种用于执行向量比较运算的装置和方法
US10191744B2 (en) 2016-07-01 2019-01-29 Intel Corporation Apparatuses, methods, and systems for element sorting of vectors
WO2018022528A1 (en) * 2016-07-27 2018-02-01 Intel Corporation System and method for multiplexing vector compare
US10564964B2 (en) * 2016-08-23 2020-02-18 International Business Machines Corporation Vector cross-compare count and sequence instructions
US11436010B2 (en) 2017-06-30 2022-09-06 Intel Corporation Method and apparatus for vectorizing indirect update loops
US11257956B2 (en) 2018-03-30 2022-02-22 Intel Corporation Thin film transistor with selectively doped oxide thin film
US11362215B2 (en) * 2018-03-30 2022-06-14 Intel Corporation Top-gate doped thin film transistor
US11163564B1 (en) * 2018-10-08 2021-11-02 Verisilicon Microelectronics (Shanghai) Co., Ltd. Vector compare and store instruction that stores index values to memory
US11403256B2 (en) 2019-05-20 2022-08-02 Micron Technology, Inc. Conditional operations in a vector processor having true and false vector index registers
US11340904B2 (en) 2019-05-20 2022-05-24 Micron Technology, Inc. Vector index registers
US11507374B2 (en) * 2019-05-20 2022-11-22 Micron Technology, Inc. True/false vector index registers and methods of populating thereof
US11327862B2 (en) 2019-05-20 2022-05-10 Micron Technology, Inc. Multi-lane solutions for addressing vector elements using vector index registers
GB2599652B (en) * 2020-10-06 2023-01-18 Advanced Risc Mach Ltd Masked-vector-comparison instruction
GB2619904B (en) * 2022-03-10 2024-07-03 Advanced Risc Mach Ltd Data processing apparatus, method and virtual machine

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0320864A (ja) * 1989-05-20 1991-01-29 Fujitsu Ltd ファジィ計算用ベクトル命令セットを有する情報処理装置
JP2621555B2 (ja) * 1990-03-12 1997-06-18 日本電気株式会社 ベクトル化処理方式
JP2002108837A (ja) * 2000-09-29 2002-04-12 Nec Corp 計算機システムとその計算制御方法
JP2004032435A (ja) * 2002-06-26 2004-01-29 Nippon Telenet Kk 発信代行装置及び発信代行方法
US7617496B2 (en) 2004-04-23 2009-11-10 Apple Inc. Macroscalar processor architecture
US7395419B1 (en) 2004-04-23 2008-07-01 Apple Inc. Macroscalar processor architecture
US7730282B2 (en) * 2004-08-11 2010-06-01 International Business Machines Corporation Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector
US20080091924A1 (en) * 2006-10-13 2008-04-17 Jouppi Norman P Vector processor and system for vector processing
US7624251B2 (en) 2006-11-01 2009-11-24 Apple Inc. Instructions for efficiently accessing unaligned partial vectors
US7620797B2 (en) 2006-11-01 2009-11-17 Apple Inc. Instructions for efficiently accessing unaligned vectors
US7660952B2 (en) * 2007-03-01 2010-02-09 International Business Machines Corporation Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode
US8019977B2 (en) 2007-05-14 2011-09-13 Apple Inc. Generating predicate values during vector processing
US8078847B2 (en) 2007-05-14 2011-12-13 Apple Inc. Detecting memory-hazard conflicts during vector processing
US8060728B2 (en) 2007-05-14 2011-11-15 Apple Inc. Generating stop indicators during vector processing
US8019976B2 (en) 2007-05-14 2011-09-13 Apple, Inc. Memory-hazard detection and avoidance instructions for vector processing
US8600120B2 (en) 2008-01-03 2013-12-03 Apple Inc. Personal computing device control using face detection and recognition
US9513905B2 (en) 2008-03-28 2016-12-06 Intel Corporation Vector instructions to enable efficient synchronization and parallel reduction operations
US8446426B2 (en) 2008-04-28 2013-05-21 Apple Inc. Technique for visually compositing a group of graphical objects
US20110035568A1 (en) 2008-08-15 2011-02-10 Apple Inc. Select first and select last instructions for processing vectors
US8959316B2 (en) 2008-08-15 2015-02-17 Apple Inc. Actual instruction and actual-fault instructions for processing vectors
US20100325399A1 (en) * 2008-08-15 2010-12-23 Apple Inc. Vector test instruction for processing vectors
US8209525B2 (en) 2008-08-15 2012-06-26 Apple Inc. Method and apparatus for executing program code
US8417921B2 (en) 2008-08-15 2013-04-09 Apple Inc. Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector
US8271832B2 (en) 2008-08-15 2012-09-18 Apple Inc. Non-faulting and first-faulting instructions for processing vectors
US8745360B2 (en) 2008-09-24 2014-06-03 Apple Inc. Generating predicate values based on conditional data dependency in vector processors
US8181001B2 (en) 2008-09-24 2012-05-15 Apple Inc. Conditional data-dependency resolution in vector processors
US8176299B2 (en) 2008-09-24 2012-05-08 Apple Inc. Generating stop indicators based on conditional data dependency in vector processors
US8310494B2 (en) 2008-09-30 2012-11-13 Apple Inc. Method for reducing graphics rendering failures
US7728742B2 (en) 2008-09-30 2010-06-01 Apple Inc. Method and apparatus for compressing and decompressing data
US7800519B2 (en) 2008-09-30 2010-09-21 Apple Inc. Method and apparatus for compressing and decompressing data
US8868847B2 (en) 2009-03-11 2014-10-21 Apple Inc. Multi-core processor snoop filtering
US8433883B2 (en) 2009-06-11 2013-04-30 Cray Inc. Inclusive “OR” bit matrix compare resolution of vector update conflict masks
US8688957B2 (en) * 2010-12-21 2014-04-01 Intel Corporation Mechanism for conflict detection using SIMD

Also Published As

Publication number Publication date
KR20130096315A (ko) 2013-08-29
WO2012087548A2 (en) 2012-06-28
JP6187988B2 (ja) 2017-08-30
US20120166761A1 (en) 2012-06-28
KR101494559B1 (ko) 2015-02-17
GB201311032D0 (en) 2013-08-07
US8972698B2 (en) 2015-03-03
CN103502934B (zh) 2017-01-18
GB2500337B (en) 2020-07-15
GB2500337A (en) 2013-09-18
JP2016028351A (ja) 2016-02-25
WO2012087548A3 (en) 2012-08-16
JP2014504418A (ja) 2014-02-20
CN103502934A (zh) 2014-01-08
DE112011104555T5 (de) 2013-09-26
DE112011104555B4 (de) 2023-03-30

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B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements