BR102015002978A2 - temperature controlled electronic circuit, temperature controlled two transistor system, and method for extending and equalizing the effective life of a plurality of transistors - Google Patents

Abstract

temperature controlled electronic circuit, temperature controlled two transistor system, and method for prolonging and equalizing the effective life of a plurality of transistors. a system and method for prolonging equalizing the effective life of the plurality of transistors operating in parallel. The temperature of each transistor is measured and compared to the average temperature of the transistor system. A temperature difference is determined between the average temperature of the transistors and the measured temperature of each transistor. The gate resistance and emitter gate resistance of each transistor are varied based on temperature differences to control the measured temperature of each transistor, controlling the current through each transistor, thereby thermally balancing the transistors.

Description

“ELECTRONIC CIRCUIT WITH CONTROL I) AND TEMPERATURE, SYSTEM OF TWO TEMPERATURE CONTROL TRANSISTORS, AND METHOD FOR PROLONGING AND LOCALIZING THE EFFECTIVE LIFE OF T RANSISTORS” TECHNICAL FIELD [001] The field of achievement presented here is balanc thermally parallel transistors and, more particularly, adjust the current of each of the parallel transistors to equalize operating temperatures and thus achieve equal thermal degradation of the parallel transistors.

BACKGROUND [002] Transistor parameters such as conduction resistance and gate capacitance are subject to the effects of temperature, aging and defect. However, manufacturing differences result in transistor performance that varies from one to another. Because each transistor performs differently, parallel operation of transistors may not have identical conditions. Therefore, manufacturing differences make it difficult to control the performance of each transistor relative to each other in a parallel system. The preceding typical parallel operation requires that each of the transistors be forced to carry an equal amount of current or, in other words, each transistor to have the same load. Traditionally, this is considered the best means of balancing the temperature through a parallel transistor system in an attempt to wear out each transistor in the system at the same rate. However, current balancing may result in relative overloading of some transistors that have higher conduction resistances as a result of manufacturing differences and therefore higher temperatures compared to other transistors that have lower conduction resistances. Transistors associated with higher temperatures wear out and age more rapidly. 1004] Vehicles such as an aircraft may have one or more turbines requiring use and an engine with a motor controller for starting each turbine. The motorcycle controller * includes multiple parallel transistors, radially. Aircraft engine controllers are designed and built to meet the highest requirements regardless of their eventual use. For example, similarly designed engine controllers could drive a 100 kilowatt (50 kW) engine or a 50 kV engine. Therefore, most Vpxevpqveevev;.: ... * WçVXÇvCvepcS motor controllers: C: C: -S ·: S; ·: - ·.:.: Are over sized and underused I desirable have a lighter, more flexible motor controller with parallel outputs capable of driving multiple motors. For example, multiple controllers could be combined in parallel to provide a custom and correctly sized control system where different controllers could be applied accordingly. the needs of the vehicle. ; 005] is related to these and other provisions as described herein.

It should be criticized that this Summary is provided to introduce a selection of concepts in a simplified manner, which is further described below in the Detailed Description. This Summary is not intended to be used to limit the scope of the retv subject indicated. According to an embodiment described herein, a temperature-controlled, electronically controlled circuit is provided. The Indian circuitry is configured to operate in parallel. Temperature sensors are thermally coupled to each of the transistors to produce a temperature output signal indicative of a measured temperature of each of the transistors: The electronic circuitry also includes a core to monitor each temperature output signal of each of the transistors. temperature sensors and, in response to the temperature outputs, provide controller outputs for varying a gate resistor Rq and a gate emitter resistor R (jj; associated with each of the transistors. The gate resistor Rr «and the gate emitter resistor Rge vary the current for each of the transistors, but also reduce the transmis- sion values> 1 min in the newest range, the controller is configured to increase the R <port resistance to a or more than> transistors, in response to the temperature difference being greater than zero, to decrease the tempera- ture, measure one or more of the transistors and for a different emitter port resistance. R for one or more of the transistors in response to the temperature difference being greater than zero. To decrease the measured temperature of one or more transistors, The controller may be additionally configured to decrease the gate resistance R <; for one or more of the transistors in response to the temperature difference to be less than zero to increase the measured temperature of one or more transistors and to increase the emitter resistor R (> f ·: for one or more transistors in response to the temperature difference). lower than zero to increase the measured temperature of one or more transistors. [UORJ] According to another embodiment described herein, a two transistor system is provided having a temperature control system. The two transistor system includes a first transistor and second transistor configured to operate in parallel The two transistor system also includes a first temperature sensor and a second: temperature sensor The first temperature sensor is thermally coupled to the first transistor to produce a first output signal. indicative of a first measured temperature of the first transistor. The second temperature sensor is thermally coupled to the second transistor to produce a second temperature output signal indicative of a second measured temperature of the second 1 rans i.e. The two transistor system also includes a controller for monitoring the first and second temperature outputs and, in response to first and second temperature outputs, provide controller outputs for varying a first gate resistor Rgi and a first gate resistor Rgi. associated with the first transistor and for varying a second gate resistor Rc, 2 and a second gate emitter resistor Rge2 associated with the second transistor, Rgi and Rgki vary the current for the first transistor and Rg2 and Rge2 vary the current for the second transistor, for thermally balance the first and second transistors. According to yet another embodiment described herein, a method is provided for extending and equalizing the effective life of the plurality of transistors. The method includes operating the transistors in parallel and measuring a temperature of each transistor with a temperature sensor. The method also includes determining an average transistor temperature and determining a temperature difference between the average transistor temperature and the measured temperature of each transistor. The method then includes varying the resistance based on temperature differences to control the temperature. transistors, controlling the current through each of the transistors, thereby thermally balancing the transistors. In one or more configurations, the method includes increasing the gate resistance for one or more of the transistors, in order to have a temperature greater than zero, to decrease the measured temperature of one, more transistors and decrease the resistance. . emitter port for one or more of the transistors, in response to the temperature difference being greater than zero, to decrease the measured temperature of one or more transistors. The method may also include decreasing the gate resistance for one or more of the transistors, in response to the temperature difference being less than zero, for increasing the measured temperature of one or more transistors and for mimicking the gate emitter resistance for one or more. more transistors, in response to the temperature difference being less than zero, to increase the measured temperature of one or more transistors. The features, functions and advantages that have been discussed may be obtained independently in various embodiments of the present description or may be combined in still other embodiments, the further details of which may be seen with reference to the following description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS 100; The embodiments presented herein will be more fully understood from the detailed description and accompanying drawings, in which: Figure 3 illustrates two parallel-operated transistors, in which forced currents from the two transistors result in different degrees of degradation. thermal;

Figure 2 illustrates portions of a switching waveform of the two transistors of Figure 1 where currents are not balanced;

Figure 3 uses a two-transistor circuit arrangement using a common gate driver and controller to achieve equal thermal degradation according to at least one embodiment described herein;

Figure 4 illustrates a configuration of an electronic circuit with two parallel transistors utilizing separate gate drivers and a controller for obtaining equal thermal degradation according to at least one embodiment described herein; Fig. 5 shows a configuration of an electronic circuit with three or more transistors in parallel using separate gate actuators and a controller to achieve equal thermal degradation according to at least one embodiment described herein;

Figure 6 illustrates a controller configuration for use with parent transistor systems according to at least one embodiment described herein;

Figure 7 illustrates a configuration of a flow chart for controlling transistor systems in parallel with the controller according to at least one embodiment described herein;

Figure 8 illustrates a configuration of an electronic circuit with a DC input and a three-phase AC output and featuring two inverters in parallel using separate gate triggers and a switch to achieve equal thermal degradation according to at least one embodiment. described herein;

Figure 9 illustrates a configuration of an electronic circuit with DC to DC converters in parallel using separate gate actuators and a controller to achieve equal thermal degradation according to at least one embodiment described herein; and Figure 10 illustrates a configuration of a method for effecting the effective life of transistors operating in parallel according to at least one embodiment described herein.

The various figures presented in this application illustrate variations and different aspects of the embodiments of the present disclosure. Accordingly, the detailed description in each illustration will describe the differences identified in the corresponding illustration.

DETAILED DESCRIPTION The following detailed description is directed to thermally balancing parallel transistors and, more particularly, to adjusting current for each of the parallel transistors, to equalize the operating temperatures of each transistor: and thus to obtain degradation. η- »,! ct · 'will: - other parameters will perform in many different ways. Specifically, one or more electrical circuit configurations control the operation of the transistors in parallel, such that the temperature of each transistor is equal to or substantially close to the temperature of other transistors. Temperature control of the transistor is obtained by controlling the current that the transistor conducts, such that the parallel transistors are always in the same thermal condition, such that they achieve equal wear and aging velocity and therefore better thermal and thermal management. health of transistor system. There is no intention to limit the principles of this disclosure to the particular embodiments described. The transistor system can have any number of transistors in parallel. For example, an electronic circuit may print a two-man system. where the transistors may be of the following type: eg, doo * irun: may be, for example, a Field Ion Transistor (FE 1), such as a pIFIVI Field Bed Junction Transistor. 1 Metal-Oxide Semiconductor Field Oxide Transistor (ΜΟχί ΓΊ> or Isolated Gate Field Effect Transistor (IGFET), or it may be a bipolar transistor such as an Isolated Gate Bipolar runsistor t IGBT), Switching drives for transistors can be generated by a logic circuit or a controller. In one or more configurations, the parallel transistors are gate control circuit implementations. In the following detailed description, references are made to the accompanying drawings which are shown here and which are shown by way of illustration of specific embodiments or examples. Referring now to the drawings, in which equal numerals represent equal elements across the various figures, aspects of the present description will be presented. Figure 1 illustrates an electronic circuit 10 having a DC input voltage V1, and a first transistor T (and a second transistor 72 operated in parallel with a gate actuator 12 and gate actuator 5 4. respectively). The loading of the uel currents <; for the transistor as and the transistor T2, respectively, may differ. because eMcmamnle the impedances Z '· f R, and L (f) and Z, <: (Re L from the drain to the source of transistors 1' and Γ; it may differ, lick, the gate signals of the transistors 11 and T; may be different internally, the conduction resistance and capacitance of transistors Τ 'and T; may be different.The' transistors T and Ϊ; provide emitter carrier voltages V <, and V, | 2 with faults /. t Rj and L 1) and Zr and * Rf: and L;) e where transistors ii and h of transistors Tj and T; are equally forced, the temperatures of transistors II and Γ; Therefore, transistors I and 12 are subjected to different degrees of thermal degradation and aging. (0016) Figure 2 illustrates part of the switching waveforms of transistors 1 and I of electronic circuit 10, when the transou * and ': co-cons are unbalanced. () Behavior of transistor currents ie in the region *. dfoámka and the region of the siacfonáno state are related to the different parameters as a result of the fabrication of the transistors Ί t and the electronic circuit 10. Based on the different waveforms? Ji Figure 2. the hor eq lil brio of thermal conditions between transistors I and U requires better control of the parallel operation of transistors I and T2. Figure 3 illustrates an electronic circuit 30 utilizing a common port and acicriator 22 to provide drive signals to transistors 1 and fo; a controller 24 for equal thermal degradation of the transistors T »and! fo One or more different configurations may include separate and synchronized gate triggers to provide drive signals to the transistors. Transistors Electronic Circuit 30 also includes TPS and TpS temperature sensors: · Each tim e of the US and idid temperature sensors is acted on to a d> st an si Stores I and prod_ and prod, z first and second signals. temperature output indicative of a measured temperature transistor 1 and a temperature of transistor 12. Controller 24 monitors each temperature output of each of the temperature sensors S and S; In response to temperature outputs, controller 24 provides controller outputs for varying the heats of the variable resistors. For example, with respect to transistor Tj, controller 24 provides controller output O i to vary the gate resistance R e! : Provides C <i [: j controller output to vary the Ron-emitter port resistance With respect to the controlled transistor! 24 r-roté fashion t: e crad olico- (to vary the R-port resistance and provide controller output. Chan: to vary the emitter port resistance. Rmm The controller outputs C, C.> c, and C (i adjust A voltage across the fan controller controller 24 is used to vary the resistor port R, and provides output of controller C to vary the resistor port resistor R, and thus the controller raids. and C 2 adjust a current behind resistor R 1, a current across resistor R 1, and a current through resistor R 1 by modifying the values of R 1. Rms R 1 and R 2 are the values of V. These are varied, which leads to a modification of the transistor currents i and h in both dynamic and steady state regions, to thermally balance the wool transistors, T2.When thermally balanced, the temperature of each of the transistors 1 ·, V: is substantially the same as the transient currents tor i, b conducted by transistors T ·, T :, are different. In other words, the transistors Ί t. i - are thermally balanced when the chains of trans stores. e are unbalanced. {0018] Controller 24 is configured to determine measured temperatures 1 · „·, fp; : from transistors T, ΊΤ, based on temperature outputs provided by temperature sensors Ί PSj, 1 -S2, from which an average temperature Tpnnkt of wool transistors, T2 is determined. A temperature difference ΔΤρ is calculated based on the difference between the average temperature Tp-M of the transistors' wool, 14 and the measured temperature T-, 1. 1: de vack one of the transistors f, 1. \ s controller outputs 1. <

Cqei and Cge2 are provided based on the temperature difference ΔΤρ of each of the T5, T2 transistors. Controller 24 increases the gate resistance R (, i, Rg2 for one or more of the transistors in a transistor system, such as the Ti, T2 transistors, in response to the temperature difference ΔΤρ being greater than zero, in order to decrease the measured temperature Tpmi, Trm2 of the transistors Tt, T2.The controller 24 also decreases the emitter port resistance Rgei »Rge2 for one or more of the transistors in the transistor system, such as the transistors T!? T2, in response to the difference. temperature ΔΤρ to be greater than zero, in order to decrease the measured temperature Tpmi, Tpm2 of transistors Tb T2 Controller 24 decreases the gate resistance Roi, Rg2 for transistors Ti, T2, in response to the temperature difference ΔΤρ being smaller zero, to increase the measured temperature TPmi, Tpm2 of transistors Tj, T2. Figure 4 illustrates an electronic circuit 40 using separate and synchronized gate actuators 22, 26 to provide signal drive to TT T transistors? to obtain thermal degradation of transistors Τι, T2. Electronic circuit 40 is similar to electronic circuit 30 except for the use of the two gate actuators 22, 26. Figure 5 illustrates an electronic circuit 50 which is a configuration that expands on electronic circuit 40 of Figure 4. Electronic circuit 50 includes three transistors and parallel or more where N represents the number of transistors in parallel. All electronic circuit door 50 gateways are synchronized. Controller outputs C (n, Cgei, Cg2, Cgi: - ··· C.gn »Cgen of controller 24 are provided based on the temperature difference ΔΤρ of each of the transistors Tt, T2, ...! the values of Rgi, Rq2, · ** R-on * R-gei, Rgi 2i ... R <i \, the values of Vou, Vge2, -V (; kn, H, g »G2, * ·· h, s are varied, which leads to a modification in transistor currents ii, 12, ... In both dynamic and steady state regions, to thermally balance transistors T ?, T2, ... Tn. [0020 ] igure ·>: - μ ama,., η; ao ο · - grater 24. \ measured temperature Ί,, Γ. 2 · ... ΤΓ \ is sensed by the temperature sensors Í PS. Í4S :,, Γ Sn. The average temperature In, y of the transistors!,! _. ... I. In parallel is calculated by taking j meda; of the medical temperature Γ ·. Γ.>. I, \ temperature difference ATp of each of the transistors' 1, 14, ... T \ is calculated by subtracting the measured temperature i1 ... t.s from each of the> transistors T | , 14, ... T> of average temperature Ip-jd Temperature differences ΔΤ,) Π, ι,. \ Tro. ... ΔΤ. · Γη \ are then provided to controllers der; \ ada-ínie-ra4propordonJ ', PIDj PID it. PID-1b. Plí> 2iu PIí> 2h. ... PJD-Na. PI D-Brightness level, for general controller outputs C,, C <f. (... (t. <·. C'c .c ively. The control outputs C \. (m, í c <4 Cgn »C * control the values of R.. R ... R«%. Rui, Rt ... R - of each existing transistor I. 1 ·. \ Existing general PJD controller technology can be applied here The function of these PI D controllers is to minimize temperature differences \ !, t s. \ F , r ... \ T ,,% to near zero, by adjusting the levels of -me · therefore the reminder Another localized measure equal to mr average temperature that is, the temperature of other transistors 1 t ~ ':, ... Tc is controlled to be equal to each other The saturation block SI a, S1 b, SN a SNb is used to limit a>. PID values in a pre-specified range Figure 1 illustrates a control flow diagram 1 O Corresponding to controller 24 of Figure 6. Control flow 100 starts at block 102 with the upper and lower limits for the outputs being obtained. controller Cgr, C <r where k 'r 1.2 ... K, where N equals the total number of parallel transistors in the transistor system. In block 104. the measured temperatures Tpíllk for each transistor are ueemtmaoas and in block Lüó. average temperature fp- ,. from the group of Ram-d Stores 4. I. K and the temperature differences \ T. „Of each of the transistors are calculated. e) block 108 initially designates k 1 e. at decision block 'Frog se ina einioi unite 0. then the control flow graph advances along the YES branch to block 1 12, where the controller output i ratai; aü ie x'cant, increases the temperature of the particular transistor, Ne decision block! 10. m \ f _ no and do not swim '/ cro, then tluxocia m-de eomro and as * a * lorgu do r.inn * \ V) pa; u> decision block M \ i decision block 114, if ATpmí> is less than zero, then control flowchart 100 advances along the YES branch. to block 1 16, where the output of the Cuk controller is decreased and therefore the particle transistor temperature decreases! However. if VI is not greater than or less than zero. then Y1 would be approximately zero, which indicates that a particular transistor has a measured temperature fpi. which is approximately the same as the average temperature i p. . · The transistor system. In such an echo, the control flow chart 100 advances to block 11 to increment to the next transistor. From block 118, the control flowchart RM) advances to decision block 120. to determine if k: V If not, the rare -mgac process does not go back to block 104, where the measured temperatures:, , of the transistors T. T>, ... T \ are again determined for equu hiai tennivamer.u. so α> η: ι i ca the intrinsistor system. At decision block 5 2A - if k is less than or equal to N, then the process returns to just before decision block 1! () Described above, 10022J To increase the temperature of a transistor, the controller output C is larger that the maximum controller output C <*, and then the SIM branch is followed to block 124, where the controller output (2, k is set equal to the maximum controller output €, if the controller output t t not greater than the maximum controller output C., then branch N (t) is followed to block 2 'N <m of .. output cuiitnMdor (, and dinbnu.da In decision block 1 28. if the controller output CR »is less than minimum dog, ie the SIM branch is followed to block 130, where the controller output is set equal to R., minimum. Λ from block 13 <> the process continues to If the controller output is not less than C, min, then the branch is NOT followed directly to block 118. [0023 ] To decrease the temperature of a transistor, the controller output Cã * is decreased as shown in block 116. Next, in decision block 1 32, if the controller output Cm is less than the minimum controller output so , then the SIM branch is followed to block 134. where the controller output C. * is set equal to the minimum controller output Cã. If the controller output L. is not smaller than the control output adopted C. minimum, then <. »branch is NOT followed to block 13th. where the controller change Cã.ix is increased. In decision block 138, if the controller output K a .. is greater than Cd - max then the YES branch is followed to block '40. where the controller output Cã is set equal to R. Minimum. From block 140, the process continues to block! 18 described above, if the controller output Cda κ is not larger than Khan. maximum, then the branch is NOT followed directly to block 1. [0024] Figure 8 illustrates a configuration of an electronic circuit 80 with two parallel inputs 82, 84 using separate gate icons 22. 2nd and controller 24 to obtain equal thermal degradation of m mores cu; for! and 82. 84. Each invcrsur 82.84 includes several transistors connected in specific configurations and may be a boost or additive converter. Although electronic circuit 80 with inverters 82 and 84 displays only transistors T, Ί8 operating in parallel, other pairs of transistors T> Tã, 18, 74. \ 18. 12, 18 », T: and Tu of inverters 82 and 84 may also be set in parallel operation and controlled with the controller output of controller 24 to thermally balance the transistor system. Also, more than two inverters can be operated in parallel. Figure 9 illustrates a configuration of an electronic diagram 90 with parallel € to DC converters having C capacitors. C, inductors 1, L · and tiiocos D. D; Cl-to-DC converters have separate gate actuators 22. 26 and controller 24 to achieve equal thermal degradation of parallel V-to-DC converters. More than two DC to DC converters can be operated in to loop, and controlled with the controller output from controller 24 for thermal balancing of the DC to DC converters. Figure 10 illustrates a method 200 for prolonging and equalizing the effective life of the plurality of transistors. Unless otherwise indicated, more or less operations may be performed than shown in the figures and described herein. Additionally, unless otherwise indicated, these operations may also be performed in a different order from those described herein. Method 20 «> starts at operation> 2; 0. where the plurality of transistors IV 14 ... I \ is operated in parallel. Next, on Moco 220, the temperature of each of the transistors Γ, 14, ... T \ is measured with a temperature min. S,. Γ S-, .. Γ-Μ. At block 230, the process determines an average temperature TpT: that of transistors Ij. ΊΝ ... I \. At block 240, the process determines a temperature difference YFp between the average temperature Tpru of the transistor system Γ. T ?. ... T% and the measured temperature Tp of each of the 1 C transistors. - I · In the process bump 254. resistances R ,; , R <2 ... Rr s- Rui .. R *; u ... R <% are varied based on the temperature differences ATp to control the measured temperature Ip of each of the transistors I, 14, ... 1 '* .- controlling the current i. i_ ... iN through each of the transistors Ί Ί 2, ... T \. thereby thermally balancing transistors 1 ', f :, ... 14, [0028] Method 200 may also include providing controller output Cf. C.-i, C <With, ... C <%. C \, tA based on the temperature difference of each of the transistors 1 ', T :, ... 14., increasing the gate resistance Roi, Rg2, · · Rgn for one or more of the transi stores Tj, T2> ... Tn, in response to the temperature difference ΔΤρ being greater than zero, to decrease the measured temperature Tp of each of the transistors T |, T2, ... TN and decrease the emitter gate resistance Rgei, Rge; 2,. .. Rgen for transistors Tj, T2, ... Tn, in response to the temperature difference ΔΤρ being greater than zero, to decrease the measured temperature Tp of each of the transistors Tj. T2, ... TN. Method 200 may also include decreasing the gate resistance Rgi, Rg2, - Rgn for one or more of the transistors Ti, T2, ... Tn, in response to the temperature difference ΔΤρ being less than zero, to increase the measured temperature Tp of each of one or more transistors Ti, T2, ...

Tn. and increase the emitter port resistance Rgei »Rge2- · - Rgen for one or more of the transistors Ts, T2, ... TN, in response to the temperature difference ΔΤρ being less than zero, to increase the measured temperature Tp of each or more transistors Tj, T2, ... 1 \. Additionally, the description comprises embodiments according to the following clauses. Clause 1: A temperature controlled electronic circuit, comprising: plurality of transistors configured to operate in parallel, plurality of temperature sensors, each of the plurality of temperature sensors thermally coupled to each of the plurality of transistors. for producing a temperature output signal indicative of a temperature of each of the plurality of transistors; and a controller for monitoring each temperature output signal from each of the plurality of temperature sensors, and in response to temperature outputs providing controller outputs for varying an R-gate resistor (l and an emitter-gate resistor Rge associated with each other). of the plurality of transistors, where each gate resistor R (j and each emitter gate resistor Rgj; vary the current for each of the plurality of transistors, respectively to thermally balance the plurality of transistors.) Clause 2: The electronic circuit of Clause 1, further comprising at least one gate trigger configured to provide a trigger signal to one or more of the plurality of transistors. Clause 3: The electronic circuit of Clause 1. wherein the at least one gate trigger is a trigger common gateway configured to provide drive signals to each of said plurality of transistors. 4: The electronic circuit of Clause 1, wherein the at least one gate driver comprises separate and synchronized gate drivers to provide drive signals to each of the plurality of transistors. Clause 5: The electronic circuit of Clause 1, where the plurality of transistors consist of a two transistor system comprising a first transistor and a second transistor, the temperature sensors comprise a first and a second thermally coupled temperature sensor. to the first and second transistors, respectively, where the controller provides controller output in response to a first temperature output signal indicative of the temperature of the first transistor and in response to a second temperature output signal indicative of the temperature of the second transistor, and wherein the controller output comprises controller outputs Coi and Cg2 for varying the gate resistor Rgi and the emitter carrier resistance Roeu respectively associated with the first transistor and further comprises controller outputs Cgei and Cge2 for varying the gate resistance R <j and the resistance. sender port Rge2, respectively associated with the undo transistor. Clause 6: The electronic circuit of Clause 1, where the controller output costs a lens through a R <t. a delayed voltage of an R, a voltage across a R (and a voltage across an Rciia. 10037J Chapter 7: The electronic circuit of Clause L where the controller outputs adjust a current through a resistor R (j. a current through a resistor R <i a current through a resistor R <- and a current through a bad resistor Clause 8: The electronic circuit of Ciaus 1. where the controller is configured to determine the temperature of each of the plurality of transistors, based on the temperature outputs provided by the temperature sensors, an average temperature of the plurality of transistors based on the temperature of each of the plurality of transistors, and a temperature difference between the average temperature of each one. plurality of transistors and the temperature of each of the transistors, where a controller outputs are provided based on the temperature difference of each of the plurality of transistors. Clause 9: The electronic circuit of Clause 1, where the temperature of each transistor unit is saroune.umiei same, and where the current conducted by each of the plurality of transistors is different, to balance tennually the plurality of transistors. Clause 10: The electronic circuit of Clause 1, where the controller is configured to increase gate resistance for one or more of the transistors, in response to a temperature difference being greater than zero, to decrease the temperature of one or more of the plurality of transistors. j0041 1 Clause 1: The electronic circuit of Ciausula 10 where the controller is configured to decrease emitter port resistance for one or more of the transistors in response to the temperature difference> er: iuvr than 7v.ro. to decrease the temperature of one or more of the transistor pluritude. Clause 12: The electronic circuit of Clause 1, where the controller is configured to decrease the gate roster for one or more of the plurality of transistors, in response to a smaller temperature difference to increase the temperature. from a? r «n. bad, from the plurality of transistors. Clause 13: The electronic circuit of Clause 12, where the controller is configured to increase the emitter port resistance for one or more of the transistors, in response to the temperature difference being less than zero, to increase the temperature of one. or more of the plurality of transistors. Clause 14; The electronic circuit of Clause L where the plurality of transistors are thermally balanced and unbalanced in current. Clause 15: The electronic circuit of Clause 1. where a portion of the plurality of transistors corresponds to a first inverter and another portion of the plurality of transistors is a single inverter where the first inverter and the second inverter are configured for parallel operation with at least one transistor of the second inverter. where a portion of the plurality of transistors corresponds to a first DC converter pati CC and another portion of the transistor width corresponds to a second eomersot from tt to DC, where the first and second converters from DC to DC "are configured for parallel operation and at least one transistor of the first DC to DC converter ', configured to operate in parallel with at least is a transistor of the second DC to DC converter. HKM ™ Clause 17; An array of two transistors having a temperature, comprising a prime transistor and a shaving transistor configured to operate in parallel; a first temperature sensor and a second temperature sensor, the first temperature sensor thermally coupled to the first transistor to produce a first temperature output signal indicative of a first measured transistor temperature and a second temperature sensor. coupled to the second transistor to produce a second signal! temperature output indicative of a second temperature measured from the second transistor: and a controller for monitoring the first and second temperature outputs and, in response to the first and second temperature outputs, providing controller outputs for varying a first resistance. Rn and a first emitter port resistor R associated with the first transistor and for varying a second port resistor R1; and a second emitter port resistor R, -; associated with the second transistor, where the first gate resistor R1 and the first emitter gate resistor R1 vary the current for the first transistor and the second gate resistor R0 and the second emitter resistor R1. ; vary the current to the second transistor to thermally balance the first and second transistors. 1004¾] Clause 18: The two transistor system of Clause 17, wherein the controller is configured to determine a measured temperature of each of the first and second transistors, based on the first and second measured temperatures of the first and second transistors, and for determining a temperature difference between the average temperature of the first and second transistors and the first and second measured temperatures of the first and second transistors, where the controller outputs are provided on the basis of a temperature difference of each of the first and shaving transistors. • Type] Clause 9 The two-transistors of Clause 17 comprising additionally synchronized foot-ports to provide triggering signals for the first and second transistors. two transistors of Clause 17, where the controller is configured to increase the first and second resistor '· of port R <. . R, .. for the first and second transistors, in response to a temperature difference being greater than zero, to decrease the first and second measured temperatures of the first and second transistors, and where the controller is additionally configured to decrease the first and second transistors. emitter port resistors R, R, r2 for the first and second transistors, in response to the temperature difference being greater than zero, to decrease the first and -mg. naked in m z brings) cdda> d ** r * tetro c ma. <v ** transistors, 10051} Clause 2 :: The system of the Claudio transistors is where the controller is configured to decrease the first and second resistors of ninth R <. paru the first and second transistors. in response to a temperature difference being less than zero. to increase the first and second measured temperatures of the first and second transistors, and where the controller is additionally configured to increase the first and second emitter port resistors R (_; i, Rm: for the first and second transistors, in response to the difference in lower than zero to increase the first and second measured temperatures of the first and second transistors M.I052] Clause 22: A method for prolonging and equalizing the effective life of the plurality of transistors, comprising: operating plurality of transistors in parallel; a temperature measured from each of the plurality of transistors with a temperature sensor; determine an average temperature of a plurality of transistors; determine a temperature difference between the average temperature of the plurality of transistors and the measured temperature of each of a plurality of transistors. transistors, and decay the resistance based on temperature differences to control the temperature measured temperature of each of the plurality of transistors, controlling the current through each of the plurality of transistors, thereby thermally balancing the pluralities of transistors. Clause 23: The method of Clause 22, further comprising providing controller output based on the difference and temperature of each of the plurality of transistors. Clause 24: The method of Clause 22, further comprising increasing the pore resistance for one or more of the transistors, in response to the temperature difference being greater than zero, to decrease the measured temperature of the one or more transistors. . Clause 25: The method of Clause 22, further comprising decreasing the rare emitter port resistance one more than the plurality of transistors in response to the temperance difference being greater than zero. to minimize the measured temperature of one or more of the plurality of transistors. Clause 26: The method of Clause 22, further comprising decreasing the gate resistance for one or more of the transistors, in response to the difference in temperature being less than zero, to increase the measured temperature and one or more of the plurality. of transistors. Clause 27: The method of Clause 22 further comprising increasing the emitter port resistance for one or more of the plurality of transistors in response to the temperature difference being less than zero. to increase the measured temperature of one or more plurality of transistors. The subject matter described above is provided by way of illustration only and should not be construed as limiting. Various modifications and changes may be made to the subject matter described herein, without following the examples of embodiments and applications illustrated and described, and without departing from the true spirit and scope of the present disclosure, which is reported in the following indications.

Claims (10)

1. Electronic circuit «.om vomroie de mumerufira. characterized in that it comprises: a plurality of transistors configured to operate in parallel; a plurality of temperature sensors, each of a plurality of temperature sensors thermally coupled to each of the plurality of transistors, to produce a temperature output signal indicative of a temperature of each of the plurality of transistors; and controller for monitoring each temperature output signal from each of the plurality of temperature sensors, and in response to temperature outputs providing controller outputs for varying a gate resistor R1; and an emitter resistor R (i) associated with each of the plurality of transistors, where each gate resistor Rq and each emitter gate resistor Rui would supply the current to each of the plurality of transistors, respectively, to thermally balance the plurality of transistors. Electronic circuit according to Claim 1, characterized in that it further comprises at least one gate actuator configured to provide a drive signal on one or more of the plurality of transistors. Electronic circuit according to any one of Claims 1 to 2, characterized in that the controller output adjusts a voltage across a resistor R1 (a voltage across a resistor R1) and a voltage across a resistor. resistor R, and a voltage across a resistor Electronic circuit according to any one of claims 1 to 3, characterized in that the controller is configured to increase the gate resistance for one or more of the transistors in response to a temperature difference of greater than zero to lowering the temperature of one or more of the plurality of transistors. Electronic circuit according to claim 4, characterized in that the controller is configured to decrease the emitter port resistance for one or more of the transistors in response to the temperature difference being greater than zero. to decrease the temperature one or more of the plurality of transistors. Electronic circuit according to any one of Claims 1 to 4, characterized in that the fetus has a plurality of transistors that is thermally balanced and unbalanced in current. 7 Two-transistor system with temperature control. characterized in that it comprises: first transistor and second transistor configured to operate in parallel, first temperature sensor and second temperature sensor, the first temperature sensor thermally coupled to the first transistor to produce a first temperature output signal indicative of a first measured temperature of the first transistor and second temperature sensor thermally coupled to the second transistor to produce a second temperature output signal indicative of a second measured temperature of the second transistor; and controller for monitoring the first and second temperature outputs and, in response to the first and second temperature outputs, providing controller outputs for varying a first Koe gate resistor and a first emitter gate resistor R <* associated with the first transistor and for varying a second door resistor R <. 2 and a second emitter gate resistor Rt; i: associated with the second transistor, where the first gate resistor R, and the first emitter gate resin R., vary the color eme for the first transistor and the second gate resistor R e; the second emitter port resistor Rum vary the current to the second transistor to thermally balance the first and second transistors. Method for extending and equalizing the effective life of a plurality of transistors, comprising: operating a plurality of transistors in parallel; riedn ama terrperatum measured from each of the transistors with a temperature sensor; determine an average temperature of the plurality of transistors; determining a temperature difference between the average temperature of the plurality of transistors and the measured temperature of each of the plurality of transistors; and varying the resistance based on temperature differences to control the measured temperature of each of the plurality of transistors, controlling the current through each of the plurality of transistors, thereby thermally balancing the plurality of transistors. 9. Method of agreement v m: _i ram a ::. Κ ma. Further comprising increasing the gate resistance is more than the plurality of transistors in response to the temperature difference being greater than zero to decrease the measured temperature of one or more of the plurality of transistors. The method according to any of these indications is. characterized in that it further comprises decreasing the gate resistance for one or more of the plurality of transistors in response: temperature difference is less than zero to increase the measured temperature of one or more of the plurality of transistors.