BR0114906A - Decodificador turbo eficiente em termos de espaço - Google Patents

Decodificador turbo eficiente em termos de espaço

Info

Publication number
BR0114906A
BR0114906A BR0114906-7A BR0114906A BR0114906A BR 0114906 A BR0114906 A BR 0114906A BR 0114906 A BR0114906 A BR 0114906A BR 0114906 A BR0114906 A BR 0114906A
Authority
BR
Brazil
Prior art keywords
decoder
turbo decoder
mux
mode
turbo
Prior art date
Application number
BR0114906-7A
Other languages
English (en)
Inventor
Inyup Kang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR0114906A publication Critical patent/BR0114906A/pt

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/3905Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957Turbo codes and decoding
    • H03M13/2975Judging correct decoding, e.g. iteration stopping criteria
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957Turbo codes and decoding
    • H03M13/2978Particular arrangement of the component decoders
    • H03M13/2984Particular arrangement of the component decoders using less component decoders than component codes, e.g. multiplexed decoders and scheduling thereof
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6502Reduction of hardware complexity or efficient processing
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6502Reduction of hardware complexity or efficient processing
    • H03M13/6505Memory efficient implementations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6563Implementations using multi-port memories

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Communication Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

"DECODIFICADOR TURBO EFICIENTE EM TERMOS DE ESPAçO". Um decodificador turbo eficiente. O decodificador turbo revelado inclui um primeiro modo de funcionamento, no qual o decodificador turbo usa um primeiro loop funcional. O primeiro loop funcional inclui um banco de memória, um intercalador de leitura, um primeiro multiplexador (MUX), um arquivo de RAM, um decodificador log-MAP, um intercalador de leitura e um segundo MUX. O decodificador turbo revelado inclui também um segundo modo de funcionamento, no qual um segundo loop funcional é usado. O segundo loop funcional inclui o banco de memória, o primeiro MUX, o arquivo de RAM, o decodificador log-MAP e o segundo MUX. O banco de memória é uma memória extrínseca de porta dual. O circuito de decodificador turbo revelado é comutado entre o primeiro modo e o segundo modo.
BR0114906-7A 2000-10-27 2001-10-25 Decodificador turbo eficiente em termos de espaço BR0114906A (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/699,252 US6662331B1 (en) 2000-10-27 2000-10-27 Space-efficient turbo decoder
PCT/US2001/051434 WO2002069503A2 (en) 2000-10-27 2001-10-25 Space-efficient turbo decoder

Publications (1)

Publication Number Publication Date
BR0114906A true BR0114906A (pt) 2004-11-09

Family

ID=24808524

Family Applications (1)

Application Number Title Priority Date Filing Date
BR0114906-7A BR0114906A (pt) 2000-10-27 2001-10-25 Decodificador turbo eficiente em termos de espaço

Country Status (12)

Country Link
US (1) US6662331B1 (pt)
EP (2) EP2040384A1 (pt)
JP (2) JP4028387B2 (pt)
KR (1) KR100899732B1 (pt)
CN (1) CN1295883C (pt)
AU (1) AU2001297548A1 (pt)
BR (1) BR0114906A (pt)
CA (1) CA2427153C (pt)
HK (1) HK1061751A1 (pt)
IL (2) IL155582A0 (pt)
MX (1) MXPA03003665A (pt)
WO (1) WO2002069503A2 (pt)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7333419B2 (en) * 2000-11-30 2008-02-19 Sasken Communication Technologies, Inc. Method to improve performance and reduce complexity of turbo decoder
DE10296698B4 (de) * 2001-04-24 2007-07-12 Intel Corporation, Santa Clara Verfahren und Vorrichtung zum Kodieren und Dekodieren von Daten mit unterschiedlichen Modulationsschemata und Kodierungen und einem ARQ-Protokoll
US6987778B2 (en) 2001-05-22 2006-01-17 Qualcomm Incorporated Enhanced channel interleaving for optimized data throughput
DE60235102D1 (de) * 2001-09-17 2010-03-04 Finlasin Technology Llc Dsp-architektur für drahtlose im basisband arbeitende anwendungen
US7315576B1 (en) * 2002-02-05 2008-01-01 Qualcomm Incorporated System for soft symbol decoding with MIMO log-map detection
FR2839830A1 (fr) * 2002-05-17 2003-11-21 Koninkl Philips Electronics Nv Memoire pour decodeur turbo
KR20040068771A (ko) * 2003-01-27 2004-08-02 삼성전자주식회사 소프트 복조 방법 및 소프트 복조 장치
WO2004102910A1 (en) * 2003-05-14 2004-11-25 Koninklijke Philips Electronics N.V. Iterative channel estimation using pilot signals
KR100630168B1 (ko) * 2004-08-09 2006-09-29 삼성전자주식회사 이동통신 시스템에서 비터비 디코더의 공유 방법 및 장치
US7447984B2 (en) * 2005-04-01 2008-11-04 Broadcom Corporation System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave
EP1826911A1 (de) * 2006-02-28 2007-08-29 Siemens Aktiengesellschaft Codierung und Decodierung mit Trellis-codierter Modulation
JP5009418B2 (ja) * 2008-06-09 2012-08-22 パイオニア株式会社 検査行列の生成方法及び検査行列、並びに復号装置及び復号方法
CN102396158A (zh) * 2009-06-18 2012-03-28 中兴通讯股份有限公司 一种lte中并行turbo译码的方法及装置
US8468432B2 (en) * 2009-07-01 2013-06-18 Silicon Motion, Inc. Coder-decoder and method for encoding and decoding an error correction code
KR101673233B1 (ko) * 2010-05-11 2016-11-17 삼성전자주식회사 트랜잭션 분할 장치 및 방법
US8499226B2 (en) * 2010-06-29 2013-07-30 Lsi Corporation Multi-mode layered decoding
JP5696604B2 (ja) * 2011-06-30 2015-04-08 富士通株式会社 誤り訂正符号の復号装置、誤り訂正符号の復号方法及び基地局装置ならびに移動局装置
JP5500203B2 (ja) * 2012-05-18 2014-05-21 住友電気工業株式会社 軟判定復号装置および軟判定復号プログラム

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1118158B1 (en) * 1998-08-14 2010-07-28 Qualcomm Incorporated Memory architecture for map decoder
US6434203B1 (en) * 1999-02-26 2002-08-13 Qualcomm, Incorporated Memory architecture for map decoder
US6263467B1 (en) * 1998-08-20 2001-07-17 General Electric Company Turbo code decoder with modified systematic symbol transition probabilities
CN100388632C (zh) * 1998-11-05 2008-05-14 高通股份有限公司 高效迭代解码
US6343368B1 (en) * 1998-12-18 2002-01-29 Telefonaktiebolaget Lm Ericsson (Publ) Method and system for fast maximum a posteriori decoding
DE69934606T2 (de) * 1999-02-26 2007-10-04 Fujitsu Ltd., Kawasaki Turbodekoder und verschachtel-/endschachtelapparat
US6732327B1 (en) * 2000-05-05 2004-05-04 Nokia Networks Oy Scaled-feedback turbo decoder
US6392572B1 (en) * 2001-05-11 2002-05-21 Qualcomm Incorporated Buffer architecture for a turbo decoder

Also Published As

Publication number Publication date
EP1354412A2 (en) 2003-10-22
KR20030040560A (ko) 2003-05-22
AU2001297548A1 (en) 2002-09-12
JP2004533140A (ja) 2004-10-28
WO2002069503A2 (en) 2002-09-06
KR100899732B1 (ko) 2009-05-27
CA2427153A1 (en) 2002-09-06
IL155582A0 (en) 2003-11-23
JP4805883B2 (ja) 2011-11-02
JP4028387B2 (ja) 2007-12-26
US6662331B1 (en) 2003-12-09
CA2427153C (en) 2010-03-30
HK1061751A1 (en) 2004-09-30
WO2002069503A3 (en) 2003-08-21
IL155582A (en) 2008-04-13
CN1295883C (zh) 2007-01-17
CN1483246A (zh) 2004-03-17
JP2008022569A (ja) 2008-01-31
MXPA03003665A (es) 2004-05-04
EP2040384A1 (en) 2009-03-25

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