BE792589A - Procede d'obtention de structures semiconductrices par implantation d'ions - Google Patents

Procede d'obtention de structures semiconductrices par implantation d'ions

Info

Publication number
BE792589A
BE792589A BE792589DA BE792589A BE 792589 A BE792589 A BE 792589A BE 792589D A BE792589D A BE 792589DA BE 792589 A BE792589 A BE 792589A
Authority
BE
Belgium
Prior art keywords
implantation
ions
semiconductor structures
obtaining semiconductor
obtaining
Prior art date
Application number
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Publication date
Publication of BE792589A publication Critical patent/BE792589A/fr

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
BE792589D 1971-10-06 Procede d'obtention de structures semiconductrices par implantation d'ions BE792589A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US18689071A 1971-10-06 1971-10-06

Publications (1)

Publication Number Publication Date
BE792589A true BE792589A (fr) 1973-03-30

Family

ID=22686706

Family Applications (1)

Application Number Title Priority Date Filing Date
BE792589D BE792589A (fr) 1971-10-06 Procede d'obtention de structures semiconductrices par implantation d'ions

Country Status (8)

Country Link
US (1) US3726719A (fr)
JP (1) JPS5147566B2 (fr)
BE (1) BE792589A (fr)
CA (1) CA981372A (fr)
DE (1) DE2231891C3 (fr)
FR (1) FR2156545B1 (fr)
GB (1) GB1376526A (fr)
IT (1) IT959917B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6849918B1 (en) * 1965-09-28 2005-02-01 Chou H. Li Miniaturized dielectrically isolated solid state device
US4946800A (en) * 1965-09-28 1990-08-07 Li Chou H Method for making solid-state device utilizing isolation grooves
US3852119A (en) * 1972-11-14 1974-12-03 Texas Instruments Inc Metal-insulator-semiconductor structures having reduced junction capacitance and method of fabrication
US3855009A (en) * 1973-09-20 1974-12-17 Texas Instruments Inc Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers
JPS51128268A (en) * 1975-04-30 1976-11-09 Sony Corp Semiconductor unit
DE2725966A1 (de) * 1977-06-08 1978-12-21 Nat Res Dev Verfahren zum wachsen von kuenstlichen diamanten
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
US4177084A (en) * 1978-06-09 1979-12-04 Hewlett-Packard Company Method for producing a low defect layer of silicon-on-sapphire wafer
DE3067750D1 (en) * 1979-07-23 1984-06-14 Tokyo Shibaura Electric Co Charge storage type semiconductor device
US4391651A (en) * 1981-10-15 1983-07-05 The United States Of America As Represented By The Secretary Of The Navy Method of forming a hyperabrupt interface in a GaAs substrate
FR2575601B1 (fr) * 1984-12-27 1987-01-30 Commissariat Energie Atomique Procede et dispositif de determination de parametres electriques d'une couche semi-conductrice en fonction de la profondeur
JP2724702B2 (ja) * 1985-06-21 1998-03-09 日本テキサス・インスツルメンツ 株式会社 電荷結合型半導体装置の製造方法
JPS61294866A (ja) * 1985-06-21 1986-12-25 Nippon Texas Instr Kk 電荷結合型半導体装置
US5236872A (en) * 1991-03-21 1993-08-17 U.S. Philips Corp. Method of manufacturing a semiconductor device having a semiconductor body with a buried silicide layer
JP2005064033A (ja) * 2003-08-12 2005-03-10 Fujio Masuoka 半導体基板へのイオン注入方法

Also Published As

Publication number Publication date
JPS5147566B2 (fr) 1976-12-15
DE2231891A1 (de) 1973-04-12
CA981372A (en) 1976-01-06
FR2156545B1 (fr) 1975-03-07
FR2156545A1 (fr) 1973-06-01
IT959917B (it) 1973-11-10
DE2231891C3 (de) 1978-04-06
US3726719A (en) 1973-04-10
DE2231891B2 (de) 1977-08-04
GB1376526A (en) 1974-12-04
JPS4846269A (fr) 1973-07-02

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