AU8206998A

AU8206998A - Method for transmitting data securely in the synchronous digital hierarchy

Info

Publication number: AU8206998A
Application number: AU82069/98A
Authority: AU
Inventors: Jurgen Burgmeier; Baldur Stummer
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1997-04-25
Filing date: 1998-04-23
Publication date: 1998-11-24
Also published as: CN1253681A; WO1998049799A3; WO1998049799A2; EP0976213A2

Description

GR 97 P 1516 Foreign Version Description Method for protected data transmission in synchronous transmission systems 5 The invention relates to a method for protected data transmission in synchronous transmission systems, in particular the synchronous digital hierarchy (SDH) and transmission systems (SONET) which use the same 10 frame structures, in which method correction bits are inserted in the overhead of the transmission pulse frame. The use of error-correcting codes has been proposed in order to improve the residual error rate 15 when transmitting data using the synchronous digital hierarchy. However, since, on the other hand, the transmission pulse frames which are used and which have so far also been recommended only by the ITU (International Telecommunication Union) are not 20 intended to be changed, it has been proposed for the required control bytes to be transmitted in the previously unused time slots (bytes) in the STM-1 pulse frame. This pulse frame is illustrated in Figure 5-2 in Recommendation G.708 (03/93) . It has been proposed for 25 13 of 22 possible bytes to be used for error correction. However, there is relatively little relationship between control bytes and data bytes to be protected. Furthermore, a plurality of successive transmission pulse frames would have to be combined in 30 order to carry out more effective error correction, for which purpose larger buffer stores would also be required. The object of the invention is to specify an improved method for protected data transmission for 35 digital transmission systems. This object is achieved by the method specified in claim 1.

GR 97 P 1516 -2 Advantageous developments of the invention are specified in the dependent claims. It is particularly advantageous for the correction to be carried out only in STM-4 pulse 5 frames. A relatively larger number of free bytes are already available for error correction in the overhead of the STM-4 pulse frame. Although the method according to the invention thus cannot be used for STM-1 transmission systems, higher transmission bit rates are 10 used in any case for trunk traffic systems and these use pulse frame formats STM-4, STM-16, ST-64, .... . In systems based on STM-4, the error correction can be retained for groups of in each case four STM-1 signals. This is also necessary in any case in order to make it 15 possible to carry out any correction at all these high data rates. Each STM-4 pulse frame - or corresponding group of four - can be coded and decoded in closed form. It is advantageous to split each STM-4 pulse frame into five coding sections, whose control bytes 20 are inserted in lines 2, 3, 6, 7 and 8 of the overhead. In this case, sufficient time slots are still kept free to accommodate bytes whose use has not yet been defined. This relates in particular to the overhead bytes in the STM-1 signals. ,Each coding sections is 25 protected by eight identical block codes, which respectively comprise the first, the second or the eight bit. This interleaved coding considerably improves the effectiveness against groups of errors. Coding and decoding are carried out in bit-parallel in 30 order to allow a lower processing speed. A BCH code, which is relatively simple to implement, is advantageously used for correction. It is expedient to use (1944, 1922, 2)-BCH codes, which comprise coding sections of 1944 bytes and 35 thus one 5th of the pulse frame, with 22 control bytes being provided per coding section. This code can correct up to two GR 97 P 1516 -3 errors. Specific bytes in the pulse frame, which are not intended to be covered by the correction process, are replaced at the transmitting and receiving ends by a fixed combination, for example logic zeroes. 5 In order to save memory space, it is expedient for the control and data bytes to be associated as closely as possible with one another in time. The length of a code also determines the memory requirement. It should thus be chosen to be as short as 10 possible for a predetermined correction capability. In addition to correction, it is also possible to design the BCH code not only to identify a further error in addition, but also to carry out separate error identification. Both have the advantage that 15 unnecessary correction and thus additional errors are avoided, if it is found that the correction capability has been exceeded. The invention is described in more detail with reference to a preferred exemplary embodiment. 20 Figure 1 shows the overhead of an STM-4 pulse frame, Figure 2 shows the association of the information bits with the coding sections. The STM-4 pulse frame shown in Figure 1 25 comprises 9 lines and 1080 columns. The first 36 columns are reserved for the overhead OH, whose precise breakdown can be found in Figure 5-3 of Recommendation G.708. The upper part of the overhead, denoted by RSOH (regenerator section overhead), comprises the first 30 three lines. The 4th line contains the AU-n pointers, and the following five lines are denoted by MSOH (multiplex section overhead) and contain further bytes which are provided for the transmission of additional information and whose meaning can likewise be found in 35 Recommendation G.708.

GR 97 P 1516 -4 However, this is not significant to the invention. Columns 37 to 1080 are called the payload PL, and are used to transmit wanted data. The entire transmission pulse frame is split 5 into five coding sections, BLOCK 1 to BLOCK 5. Each coding section comprises 1944 bytes, of which 1922 are information bytes, and 22 are control bytes. The coding and decoding are carried out in bit parallel in order to improve the correction capability 10 for groups of errors and owing to the high data rate, that is to say the bytes associated with one coding section are split into eight code blocks BCH-1, BCH-2, ... (Figure 2). One code block BCH-1 comprises, for example, all the first bits of a coding section, 15 including the first bits of the associated control bytes. The next code block BCH-2 comprises all the second bits, etc. Each code can correct two errors in one code block and can be expanded in order to identify one further error. The implementation of the 20 appropriate BCH code presents no problems to a person skilled in the art in this field. As shown in the figure, the control bytes EC-1, EC-2, EC-3, EC-4 and EC-5 are arranged in the 2nd-4th, 6th-8th, 10th-12th, 14th-16th, 18th-20th, 22nd-24th, 25 26th-28th and the 30th columns of the 2nd, 3rd, 6th, 7th and 8th lines in the overhead. If error identification is also provided, then columns 31 and 32 of the lines mentioned above are available for further control bytes K1 and K2, and columns 34 to 36 are also 30 available, if required. The simplest measure to identify errors is to form the parity (for example 01 and 10) over the information bits; if a parity error occurs, even though two corrections GR 97 P 1516 -5 are intended to be carried out in a code block, then it is certain that there is at least one other error. In addition, time slots are still free in the overhead for other functions which have not yet been 5 defined, and, in particular, the lines 1, 4, 5 and 9 in the overhead are not used. The association of the data bytes with the control bits EC-1, EC-2, EC-3, EC-4 and EC-5 is chosen such that this results in a minimal amount of memory 10 (at the transmitting and receiving ends). The 5th coding section BLOCK 5 ends with the overhead which contains the EC-5 control bytes. The following coding section BLOCK 1 then starts, after the overhead, with the payload in the 8th line. 15 There is no intention of correcting one part of the overhead, namely the RSOH part, since its contents may be changed along a path. The code in this part is replaced at the transmitting and receiving ends by a defined bit sequence, for example logic zeroes. A code 20 with a correspondingly reduced scope may consequently also be used. If one excludes the RSOH part, the first column and the columns 5, 9, 13, ... , 31 to 36 from the coding, that is to say a total of 60 information bytes 25 and 12 bits in each code block, then an (1832, 1910) BCH code is adequate. Twelve more clock periods are then also available for processing in each coding section. The method may, of course, be applied to all 30 transmission systems which use the same frame structure.

Claims

1. A method for protected data transmission for the synchronous digital hierarchy (SDH), in which 5 control bytes for error correction are inserted in the overhead (OH) of a transmission pulse frame, characterized in that control bytes (EC-1, ... , EC-5) are inserted in the 2nd, 3rd, 4th, 5th, 6th, 7th and 8th lines of the 10 overhead (OH) of a transmission pulse frame which has the structure of the transport module STM-4, in that the payload (PL) of the transmission pulse frame, the bytes to be protected in the overhead (OH) and the control bytes (FEC-1 to FEC-5 and K1 to K5) are 15 split into five equal coding sections (BLOCK 1, BLOCK 5), in that all the 1st, all the 2nd up to all the 8th bits of each byte in a coding section (BLOCK 1, ... , BLOCK 5), are respectively protected by a respective two 20 error correcting block code (BCH-1, BCH-2, ... , BCH-8) whose control information is inserted in the overhead.

2. The method as claimed in claim 1, characterized in that the control bytes (EC-1) in a coding section 25 (BLOCK 1) are arranged in one line of the overhead (OH).

3. The method as claimed in claim 2, characterized in that the information bytes in the coding sections 30 (BLOCK 1, ... , BLOCK 5) are assigned to the associated control bytes (EC-1, ... , EC-5) such that a minimal amount of memory is required.

4. The method as claimed in one of the preceding claims, 35 characterized GR 97 P 1516 -7 in that the control bytes (EC-1, ... , EC-5) are arranged in the 2nd-4th, 6th-8th, 10th-12th, 14th-16th, 18th-20th, 22nd-24th, 26th-28th and 30 th columns of the overhead.

5 5. The method as claimed in claim 4, characterized in that one coding section (BLOCK 5) ends with the overhead element of the 8th line.

6. The method as claimed in one of the preceding 10 claims, characterized in that further control bytes (K1, ... , K5) are arranged in columns 31 and 32 of the overhead (OH) and, possibly, in columns 34 to 36. 15

7. The method as claimed in one of the preceding claims, characterized in that a BCH code is provided as the block code.

8. The method as claimed in claim 7, 20 characterized in that the BCH code comprises 1944 bits, of which 1922 are data bits, and can correct two errors.

9. The method as claimed in claim 8, characterized 25 in that a BCH code which has been expanded in order to identify three errors, or corresponding error identification is used.

10. The method as claimed in claim 7, characterized 30 in that the BCH code comprises 1932 bits, of which 1908 are data bits.

11. The method as claimed in one of the preceding claims, characterized GR 97 P 1516 -8 in that those bits in the overhead (OH) which are not provided for correction are replaced by predetermined bit sequences at the transmitting and receiving ends for the purpose of error correction. 5

12. The method as claimed in one of the preceding claims, characterized in that even when transmission pulse frames which contain more than four STM-1 pulse frames are 10 transmitted, the error correction is carried out within groups which comprise four STM-1 pulse frames.

13. The method as claimed in claim 12, characterized in that, in the overhead for a column which has been 15 left free or has already been filled with other information, in each case three columns in the lines 2, 3, 6, 7 and 8 are filled with control bytes.