AU773996B2 - Sound switching device - Google Patents
Sound switching device Download PDFInfo
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- AU773996B2 AU773996B2 AU47789/00A AU4778900A AU773996B2 AU 773996 B2 AU773996 B2 AU 773996B2 AU 47789/00 A AU47789/00 A AU 47789/00A AU 4778900 A AU4778900 A AU 4778900A AU 773996 B2 AU773996 B2 AU 773996B2
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- 238000005070 sampling Methods 0.000 claims description 139
- 238000006243 chemical reaction Methods 0.000 claims description 77
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
- G10L19/16—Vocoder architecture
- G10L19/18—Vocoders using multiple modes
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- G—PHYSICS
- G10—MUSICAL INSTRUMENTS; ACOUSTICS
- G10L—SPEECH ANALYSIS TECHNIQUES OR SPEECH SYNTHESIS; SPEECH RECOGNITION; SPEECH OR VOICE PROCESSING TECHNIQUES; SPEECH OR AUDIO CODING OR DECODING
- G10L19/00—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis
- G10L19/04—Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis using predictive techniques
- G10L19/08—Determination or coding of the excitation function; Determination or coding of the long-term prediction parameters
- G10L19/12—Determination or coding of the excitation function; Determination or coding of the long-term prediction parameters the excitation function being a code excitation, e.g. in code excited linear prediction [CELP] vocoders
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- Engineering & Computer Science (AREA)
- Computational Linguistics (AREA)
- Signal Processing (AREA)
- Health & Medical Sciences (AREA)
- Audiology, Speech & Language Pathology (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Multimedia (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Analogue/Digital Conversion (AREA)
Description
Specification Speech Switching Apparatus Technical Field The present invention relates to a speech encoding/decoding apparatus and, more particularly, to a speech switching apparatus for switching one of a plurality of speech signals.
Background Art Conventionally, speech is transmitted on a transmission path on which the bit rate changes by using an encoding method of adjusting the quality of a reconstructed speech signal by adapting an encoding bit rate to the transmission path bit rate by increasing/decreasing the bandwidth of the speech signal in accordance with the transmission path bit rate. The present inventor has already proposed a speech encoding/decoding apparatus in Japanese Patent Laid-Open No. 9-202475, as a speech encoding apparatus for generating N 1 signals by changing the sampling frequency of an input speech signal, in hierarchically encoding the speech signal, and simultaneously multiplexing N-level indexes representing linear predictive coefficients, pitches, multipath signals, and gains which are obtained by sequentially encoding the input speech signal and the signals obtained by changing the sampling frequency in increasing order of sampling 1
-I
frequency, and a speech decoding apparatus for hierarchically changing the sampling frequency of a reconstructed signal in accordance with the bit rate at which decoding is performed. In this apparatus, a first CELP (Code Excited Linear Prediction) encoding circuit for receiving the signal obtained by down-sampling an input signal using a down-sampling circuit outputs an encoded output to a second CELP encoding circuit, the second CELP encoding circuit encodes the input signal on the basis of the encoded output from the first CELP encoding circuit, a multiplexer outputs the encoded outputs from the first and second CELP encoding circuits in the form of a bit stream, a demultiplexer outputs the encoded output obtained by the first CELP encoding circuit from the bit stream to a first CELP decoding circuit when a control signal has a low bit rate, and extracts part of the output obtained by the first CELP encoding circuit and the output obtained by the second CELP encoding circuit from the bit stream, when the control signal has a high bit rate, to output them to a second CELP decoding circuit so as to output them through a switching circuit.
On the decoding side, the bandwidth of a reconstructed speech signal, the sampling frequency of a decoded speech signal, changes in accordance with the bit rate at the time of reception.
When a user is to hear a sampled speech signal, a 2 1, ;1 sampling frequency must be set for conversion processing from a digital signal to an analog signal. In this case, in order to switch and reconstruct speech signals having different sampling frequencies, sampling frequencies must be set/changed. During this sampling frequency setting/changing processing, interruptions tend to occur in reconstructed speech.
The operation of a conventional speech switching apparatus will be described with reference to Fig. 7. The speech switching apparatus receives two types of speech signals (first and second digital speech signals) sampled with two different sampling frequencies 8 kHz and 16 kHz), together with a control signal, and switching and reconstructing the first and second speech signals in accordance with the control signal.
In this case, the control signal is a signal for giving an instruction to reconstruct a specific one of the two types of speech signals.
A switching circuit 103 receives first and second speech signals and control signal, and switches and outputs the two types of speech signals to a D/A conversion circuit 112 at the switching timing designated by the control signal.
The D/A conversion circuit 112 sets the sampling frequency of the speech signal designated by the control signal, converts the input digital signal into an analog signal, and outputs it.
3 -4- In the above conventional speech switching apparatus, in switching and reconstructing speech signals having different sampling frequencies, the sampling frequency in the D/A conversion circuit must be set/changed. During the setting/changing processing, interruptions occur in the reconstructed speech.
A need thus exists to provide a speech switching apparatus which can reduce strange sounds produced when a plurality of different speech signals are reconstructed/switched.
Disclosure of Invention According to a first aspect of the invention, there is provided a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, comprising at least one sampling frequency conversion circuit for converting a sampling frequency of at least one of the 15 plurality of input signals, a delay adjustment circuit for adjusting a phase of the input signal of the plurality of input signals, whose sampling frequency is converted by the sampling frequency [R:\LIBOO]6389.doc:avc conversion circuit and a phase of the remaining input signal, and outputting the signals, and a switching circuit for selecting one of a plurality of output signals from the delay adjustment circuit in accordance with the control signal.
In this case, the delay adjustment circuit may make an adjustment to match the phase of the signal whose sampling frequency is converted to the phase of the remaining input signal.
The switching circuit may switch outputs at a timing set in consideration of a delay time in the delay adjustment circuit with respect to a switching timing designated by the control signal.
According to a second aspect of the present invention, there is provided a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, comprising a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency, a delay adjustment circuit for adjusting phases between output signals from the plurality of sampling frequency conversion circuits and outputting the signals, and a [R:\LIBOO]6389.doc:avc -6switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit in accordance with the control signal.
In this case, the delay adjustment circuit may make an adjustment to match the phase of the signal whose sampling frequency is converted to the phase of the remaining input signal.
In addition, the switching circuit may switch outputs at a timing set in consideration of a delay time in the delay adjustment circuit with respect to a switching timing designated by the control signal.
According to a further aspect of the present invention, there is provided a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, comprising at least one sampling frequency conversion circuit for converting a sampling frequency of at least one 15 of the plurality of input signals, a delay adjustment circuit for adjusting a phase of the input signal of the plurality of input signals, whose sampling frequency is converted by o: the sampling frequency conversion circuit and a phase of the remaining input signal, and outputting the signals, an addition circuit [R\.LIBOO]6389.doc:avc -7for selecting and weighting two signals from a plurality of output signals from the delay adjustment circuit in accordance with the control signal, and a switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit and an output signal from the addition circuit in accordance with the control signal.
In this case, the switching circuit may switch a signal before switching of output signals from the delay adjustment circuit to an output signal from the addition circuit at a timing set in consideration of a delay time in the delay adjustment circuit from a switching timing designated by the control signal, outputs the output signal from the addition circuit for a predetermined interval, and then output he signal after switching.
lO According to a further aspect of the present invention, there is provided a speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the i: plurality of input signals in accordance with the control signal, comprising a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency, -'a.i [R:\L1BOO6389.doc:avc a delay adjustment circuit for adjusting phases between output signals from the plurality of sampling frequency conversion circuits and outputting the signals, an addition circuit for selecting and weighting two signals from a plurality of output signals from the delay adjustment circuit in accordance with the control signal, and a switching circuit for selecting one signal from a plurality of output signals from the delay adjustment circuit and an output signal from the addition circuit in accordance with the control signal.
In this case, the switching circuit may switch a signal before switching of output signals from the delay adjustment circuit to an output signal from the addition circuit at a timing set in consideration of a delay time in the delay adjustment circuit from a switching timing designated by the control signal, output the output signal from the addition circuit for a predetermined interval, and then output the signal after switching.
In addition, the above speech switching apparatus may further comprise a speech decoding circuit for decoding a plurality of signals sampled from one bit stream with different sampling frequencies, and outputting the signals as the plurality of input signals to the sampling frequency conversion circuit or the delay adjustment circuit; and one signal is selected from a plurality of output decoded signals from the 8 speech decoding circuit in accordance with a bit rate at the time of reception and the control signal and output.
The above speech switching apparatus may further comprise a bit stream switching circuit for receiving bit streams obtained by multiplexing a plurality of bit streams in which a plurality of types of signals having different sampling frequencies, and switching/outputting the bit streams to a plurality of output terminals in accordance with types of bit streams, and a plurality of speech decoding circuits for decoding the respective bit streams output from the bit stream switching circuit, and outputting the bit streams as the plurality of input signals to the sampling frequency conversion circuit or the delay adjustment circuit, and one signal may be selected from output decoded signals from the plurality of speech decoding circuits in accordance with the control signal and output.
Brief Description of Drawings Fig. 1 is a view showing the arrangement of the first embodiment of the present invention; Fig. 2 is a view showing the arrangement of the second embodiment of the present invention; Fig. 3 is a view showing the arrangement of the third embodiment of the present invention; Fig. 4 is a view showing the arrangement of the fourth embodiment of the present invention; Fig. 5 is a view showing the arrangement of 9 the fifth embodiment of the present invention; Fig. 6 is a view showing the arrangement of the sixth embodiment of the present invention; and Fig. 7 is a view showing an example of the arrangement of a conventional speech switching apparatus.
Best Mode of Carrying Out the Invention The mode of carrying out the present invention will be described below. When digital speech signals having different sampling frequencies are to be reconstructed/switched, in order to eliminate interruptions in reconstructed speech, a plurality of digital speech signals having different sampling frequencies are converted into signals having the same sampling frequency, and the resultant phases are adjusted, •thereby reconstructing the signals.
o More specifically, the arrangement described herein includes a sampling frequency C.0 conversion circuit (1 in Fig. 1) for converting the sampling frequencies of digital speech 15i signals and a delay adjustment circuit (2 in Fig. 1) for adjusting a phase shift caused by sampling frequency conversion between a plurality of digital speech signals.
To eliminate discontinuity caused between samples when digital speech signals having the same sampling frequency and different signal bandwidths are continuously reconstructed, the digital speech signals C.
CC
C.
[R\LIBOO]6389doc:avc 11 before and after switching are weighted/added for a predetermined interval first, and then are switched/reconstructed. More specifically, the present arrangement includes a sampling frequency conversion circuit (1 in Fig. a delay adjustment circuit (2 in Fig.
an addition circuit (6 in Fig. 3) for weighting/adding output signals from the delay adjustment circuit for a predetermined interval, and a switching circuit (7 in Fig. 3) for switching output signals from the addition circuit in accordance with a control signal after outputting an output signal from the addition circuit for the interval.
The sampling frequency conversion circuit and delay adjustment circuit make digital signals before and after switching have the same sampling frequency and phase.
This reduces the tendency to cause interruptions in reconstructed speech without requiring sampling frequency setting in a D/A circuit.
The addition circuit weights/adds digital signals before and after switching to reduce discontinuity between the final sample of a speech signal before switching and the and the first sample in the interval as compared with a case where no weighting/adding 15 operation is performed. The switching circuit performs switching after an output signal from 0** S *00*
S
5* *0 [RA:LIBOO]6389.doc:avc -12the addition circuit is output for a predetermined interval. This reduces discontinuity between samples at the start and end of the interval, and hence reduces the tendency to produce strange sounds in reconstructed speech.
To describe the above mode in more detail, the embodiments of the present invention will be described with reference to the accompanying drawings.
Fig. 1 is a block diagram showing the arrangement of the first embodiment of the present invention. Referring to Fig. 1, in the first arrangement, two types of speech signals (first and second speech signals) having different sampling frequencies 8 kHz and 16 kHz) and a control signal for instructing to reconstruct one of the two types of speech signals are input, and the speech signals are switched and reconstructed in accordance with the control signal.
A sampling frequency conversion circuit 1 performs sampling frequency conversion to match the sampling frequency of the first speech signal to the sampling frequency of the second speech signal converts the sampling frequency from 8 kHz to 16 kHz), and outputs the resultant signal to a delay adjustment circuit 2. In this case, the sampling frequency conversion circuit 1 performs frequency conversion by using a frequencyo multiplying or frequency-dividing 0 o V, [RALIBOO]6389.doc:avc circuit or performing interpolation or decimation processing. This frequency conversion is performed by using a known circuit. For its operation, refer to, for example, P.P. Vaidyanathan, "Multirate Systems and Filter Banks", Section 4. 1. 1 (Figure 4.1-8).
Owing to the processing performed by the sampling frequency conversion circuit i, the output signal undergoes a phase delay with respect to the input signal. Let D be the delay time in this case.
The delay adjustment circuit 2 outputs the signal obtained by delaying the input second speech signal by the delay time D using a delay circuit (not shown) and the output signal from the sampling frequency conversion circuit 1 to a switching circuit 3. As the delay circuit, an arbitrary circuit such as an inverter array or delay line is used.
The switching circuit 3 receives the first speech signal having undergone sampling frequency conversion and the second delay signal having undergone delay adjustment from the delay adjustment circuit 2, switches the two types of speech signals, in consideration of the delay time D, in accordance with the control signal, and outputs the resultant signal to a D/A conversion circuit 4.
The D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it. The analog signal is provided for a user 13- -14through a speaker, headphone, or the like.
Fig. 2 is a bock diagram showing a second arrangement. The second arrangement additionally has a sampling frequency circuit 5 for performing sampling frequency conversion of a second speech signal, as compared with the first arrangement. A sampling frequency conversion circuit 1 converts the sampling frequency of a first speech signal into a predetermined sampling frequency, and outputs the resultant signal to a delay adjustment circuit 2. Likewise, the sampling frequency conversion circuit converts the sampling frequency of the second speech signal into a predetermined sampling frequency, and outputs the resultant signal to the delay adjustment circuit 2. Let Dl be the delay time produced in the sampling frequency conversion circuit 1, and D2 be the delay time produced in the sampling frequency conversion circuit The delay adjustment circuit 2 performs delay adjustment to set the first and second speech signals having undergone sampling frequency conversion in phase, and outputs the resultant signals to a switching circuit 3.
For delay adjustment, letting D be one of the delay times Dl and D2 which is longer than the other, the two signals are delayed by the same time, the g *o [R:\LIBOO]6389.doc:avc delay time D, using a delay circuit (not shown).
The switching circuit 3 receives the first and second speech signals having undergone sampling frequency conversion and delay adjustment from the delay adjustment circuit 2, switches the two types of speech signals, in consideration of the delay time D, in accordance with the control signal, and outputs the resultant signal to a D/A conversion circuit 4.
The D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it. The analog signal is provided for a user through a speaker, headphone, or the like.
In this arrangement, for example, when the sampling frequencies of the first and second speech signals are 8 kHz and 12 kHz, respectively, the sampling frequencies of the first and second speech signals are converted into 24 kHz. This makes it possible to further reduce the processing amount of sampling frequency conversion as compared with the first embodiment in which only the sampling frequency of the first speech signal is converted into 12 kHz.
Fig. 3 is a block diagram showing a third arrangement. Referring to Fig. 3, the third o arrangement further includes an addition circuit 6 as compared with the first arrangement.
•In addition, the operation of a switching circuit 7 differs o.
a..
[R:LIBOO]6389.doc:avc from that in the first arrangement.
A sampling frequency conversion circuit 1 performs sampling frequency conversion to match the sampling frequency of a first speech signal to the sampling frequency of a second speech signal, and outputs the resultant signal to a delay adjustment circuit 2. Let the delay time produced in the sampling frequency conversion circuit 1 be D. The delay adjustment circuit 2 outputs to the addition circuit 6 the signal obtained by delaying the input second speech signal by the delay time D and the output signal from the sampling frequency conversion circuit 1.
The addition circuit 6 weights/adds the first speech signal having undergone sampling frequency conversion and the second speech signal having undergone delay adjustment, and outputs the resultant signal to the switching circuit 7.
For example, in weighting/adding operation, if signals before and after switching are given by Sl(n), S2(n), n 0, T-l then, an output signal S3(n) from the addition circuit is given by S3(n) ~n 0, T- (1) 25 where T is a sample count which represents intervals at which output signals from the addition circuit are used and is determined for each sampling frequency of an 16 -17input speech signal.
In addition, as signals before and after switching, either the first speech signal having undergone sampling frequency conversion or the second speech signal having undergone delay adjustment is assigned.
The switching circuit 7 receives the first speech signal having undergone sampling frequency conversion, the second speech signal having undergone delay adjustment, the output signal from the addition circuit 6, and a control signal, and switches the signal to be output from a signal S1 before switching to the output signal S3 from the addition circuit 6 at a timing set, in consideration of the delay time D, on the basis of the io switching timing designated by the control signal. The switching circuit 7 then outputs the signal S1 after switching to a D/A conversion circuit after outputting the signal S3 for a predetermined interval.
A D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it. The analog signal is provided for a user through a speaker, headphone, or the like.
Fig. 4 is a bock diagram showing a fourth arrangement. Referring to Fig. 4, the fourth arrangement further includes an addition circuit 6 as compared with the second arrangement. In .o *o *o ooo•1 [RALIBOOJ6389.doc:avc -18addition, the operation of a switching circuit 7 differs from that in the second arrangement.
In the fourth arrangement of the present invention, the operations of the addition circuit 6 and switching circuit 7 are the same as those described in the third arrangement.
A sampling frequency conversion circuit 1 converts the sampling frequency of a first speech signal into a predetermined sampling frequency 24 kHz), and outputs the resultant signal to a delay adjustment circuit 2. Likewise, a sampling frequency conversion circuit 5 converts the sampling frequency of a second speech signal into a predetermined sampling frequency, and outputs the resultant signal to the delay adjustment circuit 2. Let D1 be the delay time produced in the sampling frequency conversion circuit 1, and D2 be the delay time produced in the sampling frequency conversion circuit 5. The delay adjustment circuit 2 performs delay adjustment to set the first and second speech signals having undergone sampling frequency conversion in phase, and outputs the resultant signals to the addition circuit 6 and switching circuit 7.
Is For example, in delay adjustment, letting D be one of the delay times D1 and D2 which is •longer than the other, the two signals are delayed by the delay time D.
V. The addition circuit 6 weights/adds the first and second speech signals having undergone sampling 0*00 go o o* [R:\LIBOO]6389.doc: avc -19frequency conversion and delay adjustment, and outputs the resultant signal to the switching circuit 7.
For example, in weighting/adding operation, equation is used. In this case, as signals S1 and S2 before and after switching, one of the first and second speech signals having undergone sampling frequency conversion and delay adjustment is assigned.
The switching circuit 7 receives the first and second speech signals having undergone sampling frequency conversion and delay adjustment, the output signal from the addition circuit 6, and a control signal, and switches the signal to be output from the signal S1 before switching to an output signal S3 from the addition circuit 5 at a timing set, in consideration of the delay time D, on the basis of the switching timing designated by the control signal. The switching circuit 7 then outputs the signal S1 (n) after switching to a D/A conversion circuit after the signal S3 is output for a predetermined interval.
A D/A conversion circuit 4 converts the input digital speech signal into an analog signal and outputs it. The analog signal is provided for a user through a speaker, headphone, or the like.
Fig. 5 is a block diagram showing a fifth arrangement of a speech switching ~apparatus, which is a combination of a speech decoding circuit 8 and the third V [RA:LIBOO]6389.doc:avc arrangement. Referring to Fig. 5, in the fifth arrangement, the bandwidth-hierarchized speech decoding circuit 8 outputs as first and second digital speech signals digital speech signals obtained by decoding an input bit stream to a sampling frequency conversion circuit 1 and delay circuit 2.
The bandwidth-hierarchized speech decoding circuit 8 outputs, to an addition circuit 6 and switching circuit 7, a control signal for instructing which one of two types of speech signals is to be reconstructed.
In this case, the bit stream is constituted by a fundamental portion indispensable to decoding of compressed speech signal information and an expansion portion for improving the quality of the speech signal by expanding the bandwidth.
When, therefore, the bandwidth-hierarchized speech decoding circuit 8 receives only a fundamental portion, it decodes the portion into a speech signal with a narrow bandwidth a digital signal having a sampling frequency of 8 kHz), and outputs it to the sampling frequency conversion circuit 1.
When this circuit also receives an expansion portion, it decodes the signal into a speech signal with a winder bandwidth a digital signal having a sampling frequency 1 of 16 kHz), and outputs it to the •o *•go• *ooo o•* *o [R:\LIBOO]6389.doc:avc -21delay adjustment circuit 2.
For the decoding operation of the bandwidth-hierarchized speech decoding circuit 8, refer to, for example, Japanese Patent Laid-Open No. 11-30997.
When the bandwidth-hierarchized speech decoding circuit 8 receives the expansion portion of a bit stream as well as the fundamental portion, the circuit can simultaneously obtain a plurality of decoded signals, a decoded signal obtained by using only the fundamental portion and a signal obtained by using both the fundamental portion and the expansion portion.
Assume that in this arrangement, a decoded signal using only the fundamental portion of a bit stream is always obtained and output to the delay adjustment circuit 2.
The operations of the sampling frequency conversion circuit 1, delay adjustment circuit 2, addition circuit 6, switching circuit 7, and D/A conversion circuit 4 are the same as those in the second arrangement, and hence a description thereof will be omitted.
Fig. 6 is a block diagram showing a sixth arrangement of a speech switching apparatus, which is a combination of a plurality of speech decoding circuits and the first arrangement described above. Referring to Fig. 6, in the sixth arrangement,
S
o S S S*o ae [R:\LIBOO]6389.doc:avc -22a bit stream switching circuit 11 receives a bit stream obtained by multiplexing a plurality of bit streams as compressed signals having different sampling frequencies, and outputs the input bit stream to a first speech decoding circuit 9 or second speech decoding circuit depending on the type of the received bit stream.
In this case, as a method of multiplexing bit streams, a method of simultaneously multiplexing a plurality of bit streams or a method of switching and multiplexing them may be used. In the former method, two types of speech signals are simultaneously decoded from two types of bit streams. In the latter method, a speech signal is decoded from one of the bit streams. Assume that in this arrangement, a bit stream obtained by switching/multiplexing a plurality of bit streams is input.
The bit stream switching circuit 11 outputs, to a switching circuit 3, a control signal for instructing which one of the two types of speech signals is to be reconstructed.
The first speech decoding circuit 9 outputs a speech signal a digital signal having a sampling frequency of 8 kHz) obtained by decoding a bit stream having a lower bit rate 8 kbit/s) than in the second speech decoding circuit 10 as a first digital speech signal to a sampling frequency conversion circuit 1.
:0. 0.
S S
S
•5 o S S [R:\LIBOO]6389.doc:avc -23- The second speech decoding circuit 10 outputs a speech signal a digital signal having a sampling frequency of 16 kHz) obtained by decoding a bit stream having a higher bit rate 16 kbit/s) than in the first speech decoding circuit 9 as a second digital speech signal to a delay adjustment circuit 2.
In this case, for the first speech decoding circuit 9 and second speech decoding circuit 10, refer to, for example, Japanese Patent Laid-Open No. 10-207496.
The operations of the sampling frequency conversion circuit 1, delay adjustment circuit 2, switching circuit 3, and D/A conversion circuit 4 are the same as those in the first arrangement, and a description thereof will be omitted.
Fig. 5 shows a combination of the bandwidth-hierarchized speech decoding circuit and the third arrangement. Fig. 6 shows a combination of the plurality of speech decoding circuits and the first arrangement. Obviously, however, the above arrangements may be arbitrarily combined with each other.
In the third and fourth arrangements, since the addition circuit simultaneously requires a plurality of signals, when the first and second speech signals are switched, the "two signals must overlap each other.
In the third and fourth arrangements each combined with the speech decoding S• circuit, therefore, *0 0:oo o o• [R:\LIBOO]6389.doc:avc -24the apparatus must be combined with a bandwidth-hierarchized speech decoding circuit.
Alternatively, if a plurality of speech decoding circuits are used, an input bit stream must be the one obtained by simultaneously multiplexing a plurality of bit streams.
Each arrangement exemplifies the case where two type of input speech signals are processed. An apparatus designed to process three or more types of input speech signals can be realized by adding necessary numbers of sampling frequency conversion circuits and input/output lines to be connected thereto.
As has been described above, strange sounds that are produced when a plurality of different speech signals are reconstructed and switched can be reduced.
0o This is because, matching the sampling frequencies and phases of signals before and after switching of a plurality of speech signals obviates the necessity to change the sampling frequency settings.
In addition, by weighting/adding speech signals before and after switching for a predetermined interval, discontinuity between samples at the start and end of the interval can be reduced.
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Claims (14)
1. A speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, the speech switching apparatus comprising: at least one sampling frequency conversion circuit for converting a sampling frequency of at least one of the plurality of input signals; a delay adjustment circuit for adjusting a phase of the input signal, of the plurality of input signals whose sampling frequency is converted by said sampling frequency conversion circuit and a phase of the remaining input signal, and outputting the signals; and a switching circuit for selecting one of a plurality of output signals from said delay adjustment circuit in accordance with the control signal.
2. A speech switching apparatus according to claim 1, wherein said delay adjustment ooocircuit makes an adjustment to match the phase of the signal whose sampling frequency is •converted to the phase of the remaining input signal.
3. A speech switching apparatus according *o [R:IBOO]6389.doc:avc -26- to claim 1, wherein said switching circuit switches outputs at a timing set in consideration of a delay time in said delay adjustment circuit with respect to a switching timing designated by the control signal.
4. A speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, the speech switching apparatus comprising: a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency; a delay adjustment circuit for adjusting phases between output signals from said plurality of sampling frequency conversion circuits and outputting the signals; and a switching circuit for selecting one signal from a plurality of output signals from said delay adjustment circuit in accordance with the control signal.
5. A speech switching apparatus according to claim 4, wherein said delay adjustment ~circuit makes an adjustment to match the phase of the signal whose sampling frequency is *g* •converted to the phase of the remaining input signal. 0o *0 o* oo oooo *o •*go* *go *o [R:\LIB0]6389.doc:avc -27-
6. A speech switching apparatus according to claim 4, wherein said switching circuit switches outputs at a timing set in consideration of a delay time in said delay adjustment circuit with respect to a switching timing designated by the control signal.
7. A speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, the speech switching apparatus comprising: at least one sampling frequency conversion circuit for converting a sampling frequency of at least one of the plurality of input signals; a delay adjustment circuit for adjusting a phase of the input signal, of the plurality of input signals whose sampling frequency is converted by said sampling frequency conversion circuit and a phase of the remaining input signal, and outputting the signals; S"an addition circuit for selecting and weighting two signals from a plurality of output signals from said delay adjustment circuit in accordance with the control signal; and a switching circuit for selecting one signal from a plurality of output signals from •said delay S:. S°° [R:\LIBOO]6389.doc: avc -28- adjustment circuit and an output signal from said addition circuit in accordance with the control signal.
8. A speech switching apparatus according to claim 7, wherein said switching circuit switches a signal before switching of output signals from said delay adjustment circuit to an output signal from said addition circuit at a timing set in consideration of a delay time in said delay adjustment circuit from a switching timing designated by the control signal, outputs the output signal from said addition circuit for a predetermined interval, and then outputs the signal after switching.
9. A speech switching apparatus for receiving a plurality of input signal sampled with a plurality of different sampling frequencies and a control signal for designating a signal of the plurality of input signals which is to be reconstructed, and selecting and outputting one of the plurality of input signals in accordance with the control signal, the speech switching apparatus comprising: a plurality of sampling frequency conversion circuits for converting sampling frequencies of the plurality of input signals to a predetermined frequency; a delay adjustment circuit for adjusting phases between output signals from said plurality of sampling frequency conversion circuits and outputting the signals; 9* [R:\LIBOO]6389.doc:avc -29- an addition circuit for selecting and weighting two signals from a plurality of output signals from said delay adjustment circuit in accordance with the control signal; and a switching circuit for selecting one signal from a plurality of output signals from said delay adjustment circuit and an output signal from said addition circuit in accordance with the control signal.
A speech switching apparatus according to claim 9, wherein said switching circuit switches a signal before switching of output signals from said delay adjustment circuit to an output signal from said addition circuit at a timing set in consideration of a delay time in said delay adjustment circuit from a switching timing designated by the control signal, outputs the output signal from said addition circuit for a predetermined interval, and then outputs the signal after switching.
11. A switching apparatus according to claim 1, wherein said apparatus further comprises a speech decoding circuit for decoding a plurality of signals sampled from one bit stream with different sampling frequencies, and outputting the signals as the plurality of input signals to said sampling frequency conversion circuit or said delay adjustment circuit; and one signal is selected from a plurality of 00 0000 .00. *0 0 [R:-LIBOO]6389.doc:avc output decoded signals from said speech decoding circuit in accordance with a bit rate at the time of reception and the control signal and output.
12. A switching apparatus according to claim 4, wherein said apparatus further comprises a speech decoding circuit for decoding a plurality of signals sampled from one bit stream with different sampling frequencies, and outputting the signals as the plurality of input signals to said plurality of sampling frequency conversion circuits; and one signal is selected from a plurality of output decoded signals from said speech decoding circuit in accordance with a bit rate at the time of reception and the control signal and output.
13. A speech switching apparatus according to claim 1, wherein said apparatus further comprises a bit stream switching circuit for receiving bit streams obtained by multiplexing a plurality of bit streams in which a plurality of types of signals having different sampling frequencies, and switching/outputting the bit streams to a plurality of output terminals in accordance with types of bit streams, and o plurality of speech decoding circuits for decoding the respective bit streams output f shu from said bit stream switching circuit, and outputting the bit streams ooo *o *o [R LIBOO]6389.doc:avc -31- as the plurality of input signals to said sampling frequency conversion circuit or said delay adjustment circuit, and one signal is selected from output decoded signals from said plurality of speech decoding circuits in accordance with the control signal and output.
14. A speech switching apparatus according to claim 1, wherein said apparatus further comprises a bit stream switching circuit for receiving bit streams obtained by multiplexing a plurality of bit streams in which a plurality of types of signals having different sampling frequencies, and switching/outputting the bit streams to a plurality of output terminals in accordance with types of bit streams, and a plurality of speech decoding circuits for decoding the respective bit streams output from said bit stream switching circuit, and outputting the bit streams as the plurality of input signals to said plurality of sampling frequency conversion circuits, and one signal is selected from output decoded signals from said plurality of speech decoding circuits in accordance with the control signal and output. A speech switching apparatus substantially as described herein with reference to .any one of the embodiments as illustrated in Figs. 1 6. DATED this Eighteenth Day of March, 2004 NEC Corporation *eee Patent Attorneys for the Applicant SPRUSON FERGUSON [R:\LIB0O]6389.doc:avc
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11-164665 | 1999-06-11 | ||
| JP11164665A JP2000352999A (en) | 1999-06-11 | 1999-06-11 | Audio switching device |
| PCT/JP2000/003230 WO2000077775A1 (en) | 1999-06-11 | 2000-05-19 | Sound switching device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU4778900A AU4778900A (en) | 2001-01-02 |
| AU773996B2 true AU773996B2 (en) | 2004-06-10 |
Family
ID=15797504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU47789/00A Ceased AU773996B2 (en) | 1999-06-11 | 2000-05-19 | Sound switching device |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1204095A4 (en) |
| JP (1) | JP2000352999A (en) |
| AU (1) | AU773996B2 (en) |
| CA (1) | CA2376816A1 (en) |
| WO (1) | WO2000077775A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000352999A (en) * | 1999-06-11 | 2000-12-19 | Nec Corp | Audio switching device |
| JP4733939B2 (en) | 2004-01-08 | 2011-07-27 | パナソニック株式会社 | Signal decoding apparatus and signal decoding method |
| EP1814106B1 (en) | 2005-01-14 | 2009-09-16 | Panasonic Corporation | Audio switching device and audio switching method |
| EP1898397B1 (en) | 2005-06-29 | 2009-10-21 | Panasonic Corporation | Scalable decoder and disappeared data interpolating method |
| JP4560015B2 (en) * | 2005-07-29 | 2010-10-13 | パナソニック株式会社 | Decryption device |
| US7742913B2 (en) * | 2005-10-24 | 2010-06-22 | Lg Electronics Inc. | Removing time delays in signal paths |
| JP2008244775A (en) * | 2007-03-27 | 2008-10-09 | Rohm Co Ltd | Audio circuit, and electronic apparatus having the same |
| ES2530957T3 (en) * | 2010-10-06 | 2015-03-09 | Fraunhofer Ges Forschung | Apparatus and method for processing an audio signal and for providing greater temporal granularity for a combined unified voice and audio codec (USAC) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077775A1 (en) * | 1999-06-11 | 2000-12-21 | Nec Corporation | Sound switching device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2592810B2 (en) * | 1986-09-30 | 1997-03-19 | 株式会社東芝 | Sample rate conversion circuit |
| JP2600237B2 (en) * | 1987-12-29 | 1997-04-16 | ソニー株式会社 | Sampling frequency conversion circuit |
| JPH0675586A (en) * | 1992-07-08 | 1994-03-18 | Seikosha Co Ltd | Acoustic signal generating circuit |
| JPH0758709A (en) * | 1993-08-09 | 1995-03-03 | Canon Inc | Sound communication equipment |
| JP3134817B2 (en) * | 1997-07-11 | 2001-02-13 | 日本電気株式会社 | Audio encoding / decoding device |
-
1999
- 1999-06-11 JP JP11164665A patent/JP2000352999A/en active Pending
-
2000
- 2000-05-19 AU AU47789/00A patent/AU773996B2/en not_active Ceased
- 2000-05-19 CA CA002376816A patent/CA2376816A1/en not_active Abandoned
- 2000-05-19 EP EP00929812A patent/EP1204095A4/en not_active Withdrawn
- 2000-05-19 WO PCT/JP2000/003230 patent/WO2000077775A1/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000077775A1 (en) * | 1999-06-11 | 2000-12-21 | Nec Corporation | Sound switching device |
| CA2376816A1 (en) * | 1999-06-11 | 2000-12-21 | Nec Corporation | Speech switching apparatus |
| EP1204095A1 (en) * | 1999-06-11 | 2002-05-08 | NEC Corporation | Sound switching device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000352999A (en) | 2000-12-19 |
| AU4778900A (en) | 2001-01-02 |
| EP1204095A4 (en) | 2005-08-17 |
| EP1204095A1 (en) | 2002-05-08 |
| CA2376816A1 (en) | 2000-12-21 |
| WO2000077775A1 (en) | 2000-12-21 |
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