JPH0675586A - Acoustic signal generating circuit - Google Patents

Abstract

PURPOSE:To simply reproduce plural acoustic data which are sampled at different sampling frequencies, with a good tone quality. CONSTITUTION:Any one of the plural acoustic data sampled at different sampling frequencies from a ROM 1 and the corresponding control data are read by a control circuit 2. The dividing ratio of a variable frequency divider 6 is changed by the instruction from a selecting circuit 5 in accordance with the control data, read clock pulses are made to the same frequency of the sampling frequencies of the respective acoustic sampling frequencies and thus, a correct reproduction is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an acoustic signal generating circuit.

[0002]

2. Description of the Related Art For example, there is an alarm timepiece that stores a plurality of types of audio signals and selectively reads out one of them as an alarm sound. The voice signals include human voices, bird voices, bell sounds, etc., which are sampled and converted into digital acoustic data,
It is stored in ROM.

[0003]

The acoustic signal generating circuit as described above is read by the internal clock of the timepiece, but the clock pulse is fixed at a single frequency. Therefore, there is a problem that the audio data sampled at a frequency different from the audio data reading clock pulse cannot be correctly reproduced.

An object of the present invention is to easily reproduce a plurality of audio data sampled at different sampling frequencies with good sound quality.

[0005]

According to the present invention, a plurality of acoustic data sampled at different sampling frequencies from a storage circuit and control data corresponding to the acoustic data are read out and are changed by an instruction from an instruction circuit according to the control data. By changing the frequency division ratio of the frequency divider, correct reproduction is performed by setting the read clock pulse to the frequency corresponding to the sampling frequency of each acoustic data,
To achieve the above objectives.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, 1 is a ROM as a memory circuit
In addition to storing a plurality of types of acoustic data such as melody, onomatopoeia, and voice, control data for instructing the frequency of each read clock pulse is provided with the start address of each acoustic data and the desired number of data (for example, 128). ) Remember each. That is, the control data is stored for each desired number of data so that, for example, even in the case of one kind of melody, even if the sampling frequency changes in the middle, it is possible to handle it. A frequency corresponding to the sampling frequency of each acoustic data is designated as the read clock pulse. Reference numeral 2 is a control circuit including a CPU, a RAM, and a ROM. Reference numerals 3 and 4 are a counter and an address designating circuit, respectively, each of which has a reset terminal RES and an address set signal input terminal ADS. Reference numeral 5 is a selection circuit which constitutes an instruction circuit, receives control data and acoustic data, and the control data is an output signal SOU as an instruction signal.
The sound data is output from T and the acoustic data is output from the output terminal DOUT. Reference numeral 6 denotes a variable frequency divider, which includes an SEL which is an instruction signal input terminal, and switches the frequency division ratio according to the instruction signal. 7
Is an oscillator circuit, which supplies a clock pulse to the variable frequency divider. Reference numeral 8 is a D / A converter, and 9 is a speaker, which converts acoustic data into voice.

Next, the operation will be described with reference to the flowcharts of FIGS. 1 and 2. First, the variable frequency divider 6 and the counter 3 are reset by a reset signal from the control circuit (step a). The start address of specific sound data is set in the addressing circuit 4 by the address setting signal from the control circuit (step b). The sound data to be reproduced is selected by operating a selection switch (not shown), for example. The clock pulse from the oscillator circuit 7 is input to the variable frequency divider 6 and output (step c). When the first output pulse is input to the ROM 1, control data corresponding to the acoustic data whose head address is set before DOUT is output (step d). The control data is input to the selection circuit 5, held there, and output from SOUT as an instruction signal (step e). The instruction signal is input to the SEL terminal of the variable frequency divider, and the variable frequency divider changes the frequency division ratio accordingly (step f). Thereby, the frequency of the read clock pulse is set to be equal to the sampling frequency of the acoustic data. When the output pulse of the variable frequency divider 6 having a different frequency division ratio is input to the ROM 1, the data in the ROM 1 is output from DOUT (step g). The data is input to the selection circuit 5 to identify control data and acoustic data (step h). If it is acoustic data, it is output to the D / A converter 8 (step i). And D / A
After being D / A converted by the converter 8 (step j), it is output as voice from the speaker (step k). In this example, since the control data is stored for each desired number of acoustic data, when the control data is read, the operation of changing the frequency division ratio of the variable frequency divider 6 according to the control data is performed. This makes it possible to handle even one type of melody even if the sampling frequency changes midway.

The acoustic data is reproduced as described above,
In (step l), it is judged whether or not the reproduction is ended. If the reproduction is not ended, the operation following (step g) is repeated, and if the reproduction is ended, the operation is ended (END).

[0009]

According to the present invention, a plurality of sound data sampled at different sampling frequencies can be reproduced by a read clock pulse having a frequency corresponding to each sampling frequency, and a sound of good sound quality can be reproduced with a simple structure. can do.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG.

[Explanation of symbols]

 1 memory circuit 2 control circuit 5 indicator circuit 6 variable frequency divider

Claims (1)

[Claims] 1. A storage circuit for storing a plurality of types of acoustic data sampled at different sampling frequencies and control data indicating sampling frequencies of the respective acoustic data, and control for selectively reading desired acoustic data from the storage circuit. A circuit, and an instruction circuit for instructing the frequency of the read clock pulse by the control data corresponding to the acoustic data read from the storage circuit,
An audio signal generation circuit comprising: a variable frequency divider that changes the frequency of a read clock pulse according to an instruction from the instruction circuit.