AU7594600A - Integrated high voltage capacitive coupling circuit using bonded and trenched isolated wafer technology - Google Patents

Integrated high voltage capacitive coupling circuit using bonded and trenched isolated wafer technology

Info

Publication number
AU7594600A
AU7594600A AU75946/00A AU7594600A AU7594600A AU 7594600 A AU7594600 A AU 7594600A AU 75946/00 A AU75946/00 A AU 75946/00A AU 7594600 A AU7594600 A AU 7594600A AU 7594600 A AU7594600 A AU 7594600A
Authority
AU
Australia
Prior art keywords
trenched
bonded
high voltage
capacitive coupling
coupling circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU75946/00A
Inventor
Michael J. Gambuzza
Nestore Polce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IXYS Integrated Circuits Division Inc
Original Assignee
CP Clare and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CP Clare and Co filed Critical CP Clare and Co
Publication of AU7594600A publication Critical patent/AU7594600A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
AU75946/00A 1999-09-23 2000-09-20 Integrated high voltage capacitive coupling circuit using bonded and trenched isolated wafer technology Abandoned AU7594600A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US40448199A 1999-09-23 1999-09-23
US09404481 1999-09-23
PCT/US2000/025747 WO2001022493A1 (en) 1999-09-23 2000-09-20 Integrated high voltage capacitive coupling circuit using bonded and trenched isolated wafer technology

Publications (1)

Publication Number Publication Date
AU7594600A true AU7594600A (en) 2001-04-24

Family

ID=23599780

Family Applications (1)

Application Number Title Priority Date Filing Date
AU75946/00A Abandoned AU7594600A (en) 1999-09-23 2000-09-20 Integrated high voltage capacitive coupling circuit using bonded and trenched isolated wafer technology

Country Status (2)

Country Link
AU (1) AU7594600A (en)
WO (1) WO2001022493A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368144B2 (en) 2006-12-18 2013-02-05 Infineon Technologies Ag Isolated multigate FET circuit blocks with different ground potentials

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3344598B2 (en) * 1993-11-25 2002-11-11 株式会社デンソー Semiconductor nonvolatile memory device
JP3180599B2 (en) * 1995-01-24 2001-06-25 日本電気株式会社 Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
WO2001022493A1 (en) 2001-03-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase