AU679838B2

AU679838B2 - Energy saving device in a portable communication terminal

Info

Publication number: AU679838B2
Application number: AU16501/95A
Authority: AU
Inventors: Patrice Beaudou; Christophe Nussli
Original assignee: Alcatel Mobile Communication France SA
Current assignee: Alcatel CIT SA
Priority date: 1994-04-19
Filing date: 1995-04-18
Publication date: 1997-07-10
Anticipated expiration: 2015-04-18
Also published as: JPH07303076A; CA2147227A1; AU1650195A; NZ270946A; FR2718860B1; FI951777A; EP0678804A1; FR2718860A1; FI951777A0

Description

AUSTRALIA

Patents Act COMPLETE SPECIFICATION

(ORIGINAL)

Class Int. Class Application Number: Lodged: Complete Specification Lodged: Accepted: Published: Priority Related Art: Name ofApplicant: Name of Applicant: o so Societe Anonyme dite Alcatel Mobile Communication France Actual Inventor(s): Christophe Nussli Patrice Beaudou Address for Service:

D

e PHILLIPS ORMONDE FITZPATRICK Patent and Trade Mark Attorneys 367 Collins Street Melbourne 3000 AUSTRALIA Invention Title: ENERGY SAVING DEVICE IN A PORTABLE COMMUNICATION TERMINAL Our Ref 407089 POF Code: 1501/230687 The following statement is a full description of this invention, including the best method of performing it known to applicant(s): -1- _I a ENERGY SAVING DEVICE IN A PORTABLE COMMUNICATION TERMINAL BACKGROUND OF THE INVENTION Field of the invention The present invention is generally concerned with conserving energy in portable communication terminals and in particular a device for conserving energy by inhibiting selection of external memories of a portable communication terminal.

Portable communication terminals such as GSM mobile telephones are battery powered.

The proportion of time for which a portable terminal is busy communicating with another terminal is very small. For this reason, to conserve energy and maximize battery life, the circuits of the terminal are 15 usually not active when the terminal is not communicating (although they continue to be supplied with power).

Description of the prior art The prior art already includes many systems for conserving the energy supplied by the battery. For example, European patent EP-A-0 255 048 describes a portable telephone including a device enabling it to determine whether or not it is in the network service area and to disconnect the battery if it is outside the ooeo service area.

In PCT patent application WO 93.25955, a portable terminal includes a master processor responsible for control and surveillance functions and a microprocessor responsible for data processing operations. An event necessitating data processing activates the microprocessor which executes the necessary operations and is immediately de-activated by the master processor to conserve energy when it is not actively involved in data processing.

At present, so-called "static" CMOS microprocessors microprocessors which are able to withstand an I I interruption in the clock signal) have a dedicated "power down" instruction which inhibits the clock input and therefore stops all activity in the microchip. As the crystal supplying the clock signal is usually connected to the microprocessor, inhibiting the clock input obviously disables the output and the clock signal is turned off. The system, still supplied with power by its battery (usually at 5 Volts) is in a maximal economy mode, in some cases consuming less than 50 pA (the sum of the leakage current of the CMOS devices), a value much lower than the consumption when active which can be as much as 50 mA. As already mentioned, the microprocessor is in "power down" mode most of the time in the case of a portable telephone.

15 The microprocessor looks for the power down instruction in external memory, either RAM or ROM. As the instruction shuts down the system, it is the last instruction that the system executes before powering down. However, this means that the memory which contains the power down instruction remains selected because, after executing this instruction, it is not possible to execute another instruction to deactivate the memory.

Obviously this latter instruction could not be executed *before the power down instruction as this would make the memory unavailable for executing the power down instruction. A memory with the chip select line activated continues to consume a few mA, which is evidently lower than when active but is nevertheless undesirable in the case of a battery powered terminal.

Furthermore, even if it were possible to deactivate memory selection, it would be impossible to select the memory again on leaving the "power down" mode, usually on an interrupt, as it is not possible to execute the instructions which are in the memory that has to be selected.

For this reason the main object of the invention is to provide a device for conserving energy by inhibiting the chip select line of memories containing the instructions after the microprocessor has been powered down.

SUMMARY OF THE INVENTION The invention consists in a device for conserving energy in a portable communication terminal including a microprocessor and at least one instruction memory external to the microprocessor which is powered down when the terminal is not communicating with another terminal, said device being characterized in that it includes: control means having an input and a control output, said input being connected to a read memory S" 15 output from said microprocessor which delivers a periodic signal, and switching means having two inputs and an output connected to a chip select input of said memory, a first input of which is connected to a chip select output of the microprocessor and the second input of which is connected to said control output of the control means, said switching means supplying a deactivation signal at its output when the signal at said read memory output of •said microprocessor ceases to be periodic when said microprocessor is powered down, so that said memory is no longer activated even though the chip select line remains active.

The aims, objects and features of the present invention will emerge more clearly from the following description given with reference to the drawings, BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a first embodiment of the invention.

Figure 2 shows the timing diagrams of the -in signals present in the device shown in figure 1.

Figure 3 is a block diagram of a second embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to figure 1, the microprocessor 10 has an output line RDB carrying the signal for reading memory such as a ROM 12 containing instructions of a program.

This signal RDB is a periodic signal shown in the first diagram in figure 2.

The signal RDB is applied to the read input OEB of the ROM 12 and to the device of the invention via a capacitor C 1 14 of approximately 1 nF. The capacitor C 1 is connected to the input of a diode D 1 16 the output of Swhich is connected to the gate of a field effect transistor 18. The output of the diode 16 is connected 15 by the series-connected resistors R 1 20 and R 2 22 to the source of the transistor 18 the drain of which is connected to a fixed voltage of +5 V via a resistor

R

3 24. The point of interconnection between the resistors 20 and 22 is connected to ground via a capacitor C 2 26.

The source of the transistor is connected to the chip select line CS 1 from the microprocessor 10 and its drain is connected to the chip select input CSB of the memory 12. In the absence of the device of the invention the line CS 1 would be connected directly to the chip select input CSB of the memory. There are, of course, as many memory chip select lines CS 1

CS

2 etc as there are memories to be selected, whether ROM or RAM, and the same number of circuits identical to that of figure 1.

When the microprocessor 10 is active, i.e. when the signal RDB is a periodic pulsed signal as shown in figure 2, the capacitor 14 offers only a negligible impedance to the signal. Also, on each pulse, the diode 16 conducts and the capacitor C 2 26 charges with a time constant t

I

R

1

C

2 If R 1 has a low value (for example 1 Kohm), the time constant is much less than the period of the periodic signal RDB, i.e. the capacitor charges very quickly. On the other hand, if the resistor R 2 22 has a large value (for example 1 Mohm) so that the time constant t 2

R

2

C

2 is much greater than the period of the signal RDB the capacitor C 2 will not have time to discharge between two pulses of said signal at the output

CS

1 of the microprocessor if the latter is 0 V.

Thus the output of the diode 16 connected to the resistor 20 remains "high" (at a potential of 5 This potential is applied to the gate of the transistor 18.

Consequently, the transistor 18 is turned on provided that its source is at the 0 V potential by virtue of being connected to the line CS 1 which is "low" S 15 A memory is selected by applying a low level (0 V) to its chip select input CS, as shown in figure 2.

Because the transistor 18 is turned on the current .flowing between the drain and the source causes a voltage drop in the resistor R 3 24. The drain connected to the chip select input CSB of the memory therefore remains low (0 V) as shown in figure 2.

When the microprocessor is powered down, its memory S. chip select line CS 1 goes "low", as shown in figure 2.

Becau3e RDB has a constant value (0 V in this example) the diode 16 ceases to conduct and its output remains at V. Despite the high time constant t 2

R

2

C

2 the capacitor discharges into the terminal CS 1 in a time tD.

When the capacitor 26 has discharged beyond a certain point, the gate voltage of the transistor 18, which tracks the charge on the capacitors 26, falls below the threshold which turns off the transistor 18.

Consequently, no current flows in the resistor R 3 24 and the drain connected to CSB goes to 5 V, as shown in the third diagram in figure 2.

Thus when the microprocessor 10 is powered down the I chip select input CSB goes to the high (deactivation) level after a short time-delay tD and the ROM consumes no further energy.

When the microprocessor is "awakened" the signal RDB is again a periodic signal, the effect of which is to turn on the transistor 18 and therefore to apply a low (activation) level to the chip select input CSB at the end of a time-delay t C corresponding to the time constant t I of the circuit R 1

C

2 Although the signal RDB is shown low when the microprocessor is powered down, the converse is feasible with the signal RDB held at 5 V when the microprocessor .is powered down. This does not change the behavior of .the signal CSB since the capacitor C 1 prevents the flow 15 of current in the diode D 1 16. Consequently, and as previously, the signal CSB goes to the high (deactivation) level.

The embodiment of the invention shown in figures 1 and 2 is suitable if the system includes a plurality of ROM and or RAM containing instructions. This applies in particular when the software run by the microprocessor is responsible for pagination, i.e. management of the .physical addressing of the memories (requiring activation •of the chip select signal CS 1

CS

2 etc).

However, there is a special case in which the system includes only one ROM. This embodiment of the invention is shown in figure 3.

The essential difference compared to the embodiment of the invention shown in figure 1 is that the source of the FET 18 is connected to the output RDB of the microprocessor. As previously, when the signal RDB stabilizes at 0 V or at 5 V, the transistor 18 is turned off because either the capacitor C 2 26 discharges towards the 0 V potential at the output RDB in which case the gate of the transistor goes to the 0 V poi.,intial after a time-delay tD, or the source of the transistor is at 5 V, i.e. at the same potential as its gate. Consequently, in both cases the chip select input CSB of the memory stabilizes at the 5 V potential corresponding to deactivation of the ROM 12.

In the embodiment of the invention shown in figure 3 the capacitor C 1 14 is not necessary. In the embodiment of the invention of figure 1 the signal RDB stabilizes at +5 V when the microprocessor is powered down and the capacitor C 1 was required to prevent the signal RDB maintaining the gate of the transistor 18 at +5 V. In the figure 3 embodiment this is not needed because the transistor is turned off when the signal RDB is stable at +5 V because its source is also at +5 V.

0* 4 *re *e eto *o *o*

Claims

4. Device according to claim 1 in a portable S: 2 communication terminal including only one instruction 3 memory and wherein said first input of said switching 4 means is connected to said read memory output of said microprocessor. 1 5. GSM mobile telephone terminal including a device 2 for conserving energy in a portable communication 3 terminal including a microprocessor and at least one 4 instruction memory external to said microprocessor which is powered down when said terminal is not communicating 6 with another terminal, said device being characterized in 7 that it includes: 8 control means having an input and a control 9 output, said input being connected to a read memory output from said microprocessor which delivers a periodic 11 signal, and 12 switching means having two inputs and an output 13 connected to a chip select input of said memory, a first 14 input of which is connected to a chip select output of said microprocessor and the second input of which is 16 connected to said control output of said cointr-ol means, 17 said switching means supplying a deactivation signal at 18 its output when the signal at said read nmemory output of 19 said microprocessor ceases to be periodic when said microprocessor is powered down, so that said memory is no 21 longer activated even though said chip select line 22 remains active. 1 6. Terminal according to claim 5 wherein said 2 switching means comprise a field effect transistor a gate 3 of which is connected to said control output of said 4 control means, a source of which is counected to said 5 chip select line of said memory and an output of which S6 is connected firstly to said chip select input of said 7 memory and secondly to a high potential via a resistor so 8 that said transistor is turned on and its drain is at a 9 low potential when said signal at said read memory output i0O of said microprocessor is a periodic signal indicating 11 that said microprocessor is active and so that said 12 transistor is turned off and its drain is at a high 13 potential when said signal at said read memory output of 14 said microprocessor stabilizes at a fixed value 15 indicating that said microprocessor is powered down. 1 7. Terminal according to claim 5 wherein said 2 control means include: 3 a first capacitor connected to said read memory 4 output of said microprocessor, a diode connected to n output of said capacitor, 6 a first resistor and a second resistor connected in 7 series between an output of said diode and said source of 8 said field effect transistor, said second resistor having 9 a much higher value than said first resistor, and a second capacitor connected between ground and a 11 point of interconnection of said first and second I I, I I 11 12 resistors so that said second capacitor charges quickly 13 on each rising edge of said signal when the latter is 14 periodic and discharges slowly when said signal ceases to be periodic because said microprocessor is powered down. 1 8. Terminal according to claim 5 including only one 2 instruction memory and wherein said first input of said 3 switching means is connected to said read memory output 4 of said microprocessor. DATED: 13th April, 1995 PHILLIPS ORMONDE FITZPATRICK Attorneys for: SOCIETE ANONYME DITE ALCATEL MOBILE COMMUNICATION FRANCE 6 *oo* 0. U. w6 6 *q ~1 12 ABSTRACT OF THE DISCLOSURE A device for conserving energy in a portable communication terminal includes a microprocessor and at least one instruction memory external to the microprocessor which is powered down when the terminal is not communicating with another terminal. T!Le device includes a control unit having an input and a control output, the input being connected to a read memory output of the microprocessor which delivers a periodic signal. A switching unit has two inputs and an output connected to the chip select input of the memory. Its first input is connected to the chip select output of the microprocessor and its second input is connected to the control output of the control unit. The switching unit S 15 supplies a deactivation signal at its output when the .signal delivered by the read memory output of the microprocessor ceases to be periodic when the microprocessor is powered down, so that the memory is no longer activated even though the chip select line remains 20 active. Se **o I-