AU654627B2

AU654627B2 - PLL frequency synthesizer capable of changing an output frequency at a high speed

Info

Publication number: AU654627B2
Application number: AU44367/93A
Authority: AU
Inventors: Hidehiko Norimatsu
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1990-10-22
Filing date: 1993-07-30
Publication date: 1994-11-10
Anticipated expiration: 2011-10-21
Also published as: AU4436793A; JPH04157816A; AU654628B2; AU4436893A; JP2994021B2

Description

PLL FREQUENCY SYNTHESIZER CAPABLE OF CHANGING AN OUTPUT FREQUENCY AT A HIGH SPEED This application is a divisional of application No. 86021/91 in the name of NEC Corporation.

Background of the Invention: This invention relates to a frequency synthesizer with a phase-locked loop (PLL). Such a frequency synthesizer is called a PLL frequency synthesizer.

As well known in the art, the PLL frequency synthesizer comprises a reference signal generator, a voltage controlled oscillator, a */ariable frequency divider, a phase-frequency comparator, and a control voltage supplying circuit. The reference signal generator generates a reference signal with a reference frequency. Responsive to a control voltage signal, the voltage controlled oscillator generates a voltage controlled signal having a controllable oscillating frequency. The PLL frequency synthesizer produces the voltage controlled signal as an output signal. Therefore, the output signal has an output frequency equal to the controllable oscillating frequency. The *o:o *oo o o*oo *o *o *oo o *oo °°o *oooo *o* BFD/31 4 output signal is supplied to the variable frequency divider. The variable frequency divider is also supplied with a designated dividing number D which defines the output frequency, where D represents a positive integer.

The variable frequency divider frequency divides the output signal on the basis of the designated dividing number D to produce a divided signal. In other words, the variable frequency divider is for frequency dividing the output signal by a factor l/D. The phase-frequency comparator is supplied with the reference signal and the divided signal. The phase-frequency comparator detects a phase-frequency difference between the reference signal and the divided signal to produce a phase-frequency difference signal indicative of the phase-frequency difference. In other words, the phase-frequency difference signal indicates one of lag and lead phases S which the divided signal has in comparison with the reference signal. Responsive to the phase-frequency difference signal, the control voltage supplying circuit supplies the control voltage signal to the voltage controlled oscillator.

More specifically, the control voltage supplying circuit comprises a current flow control *oo* circuit and a loop filter. Responsive to the phase-frequency difference signal, the current flow control circuit controls flow-in and flow-out of current supplied therefrom/to to produce a current flow control signal. The current flow control signal indicates the flow-out of the current when the phase-frequency difference signal indicates the lag phase. The current flow control signal indicates the flow-in of the current when the phase-frequency difference signal indicates the lead phase. Supplied with the current flow control signal, the loop filter filters the current flow control signal into a filtered signal as the control voltage signal. More particularly, the loop filter comprises a filter capacitor which is selectively charged and discharged when the current flow control signal indicates the flow-out and the flow-in of the current, respectively.

In a conventional PLL frequency synthesizer, changing of the output frequency is carried out by changing step by step the designated dividing number D.

STherefore, the PLL frequency synthesizer has a variable o,,o delay amount on changing the output frequency. As a e, result, a frequency error of the output frequency occurs in the PLL frequency synthesizer on changing the output frequency. Accordingly, the conventional PLL frequency synthesizer is defective in that it is impossible to •coo change the output frequency at a high speed.

Summary of the Invention: It is therefore an object of the present invention to provide a PLL frequency synthesizer which is capable of changing an output frequency at a high speed.

Other objects of this invention will become clear as the description proceeds.

Accordingly the invention discloses, a frequency syntnesiser comprising: a reference signal generator for generating a referen_e signal with a reference frequency; a voltage controlled oscillator responsive to a control voltage signal for generating an output signal having an output frequency; a variable frequency divider supplied with said output signal and responsive to a designated dividing number defining said output frequency for frequency dividing said output signal on the basis of said designated dividing number to produce a divided signal; a phase-frequency comparator supplied with said reference signal and said divided signal for detecting a phase-frequency difference between said reference signal and said divided signal to produce a phase-frequency difference signal indicative of one of lag and lead phases which said divided signal has in comparison with said reference signal, said phase-frequency difference signal comprising lag and lead phase signals which indicate the lag and the lead phases, respectively; a current flow control circuit responsive to said phase-frequency difference signal for controlling flow-in and flow-out of current supplied therefrom/to to produce a current flow control signal, said current flow control circuit consisting of a p-channel S• MOSFET and an n-channel MOSFET each of which has a gate terminal, a drain terminal, and a source terminal and which are joined at the drain terminals thereof, the gate terminal of said p-channel MOSFET being supplied with said lag phase signal, the gate terminal of said n-channel MOSFET being supplied with said lead phase signal, said p-channel MOSFET being put into an ON state in response to said lag phase signal, said n-channel MOSFET being put into an ON state in response to said lead phase signal; •a loop filter supplied with said current flow control signal for filtering said current flow control signal into a filtered signal as said control voltage signal; and a current controlling circuit responsive to a current command for controlling said current supplied from/to said current flow control circuit, said current command comprising charge-up and discharge indication signals, said current controlling circuit comprising a charge-up control circuit and a discharge control circuit, said charge-up control circuit being supplied with said charge-up indication signal and being connected to the source terminal of said p-channel MOSFET, said discharge control circuit being supplied with said discharge indication signal and being connected to the source terminal of said n-channel MOSFET, whereby said charge-up control circuit carries out, in response to said charge-up indication signal, charge-up of said loop filter through said p-channel MOSFET when said p-channel MOSFET is put into the ON state while said discharge control circuit carries out, in response to said discharge indication signal, discharge of said loop filter through said n-channel MOSFET when said n-channel MOSFET is put into the ON state.

Brief Description of the Drawings: Fig. 1 is a block diagram of a conventional PLL frequency synthesiser; Fig. 2 is a block diagram of a PLL frequency synthesiser according to a first embodiment of the instant invention; Fig. 3 is a block diagram of a pulse removing circuit for use in the PLL frequency synthesiser illustrated in Fig. 2; Figs. 4(a) through collectively show a time chart for use in describing operation of the pulse removing circuit illustrated in Fig. 3; *o.

a.

a ao ooo ofo *o L ln:\libkl00065:HRW Fig. 5 is a block diagram of a PLL frequency synthesizer according to a second embodiment of the instant invention; Fig. 6 is a block diagram of a charge pump circuit for use in the PLL frequency synthesizer illustrated in Fig. Fig. 7 is a block diagram of a charge-up control circuit of a current controlling circuit for use in the PLL frequency synthesizer illustrated in Fig. Figs. 8(a) through collectively show a time chart for use in describing operation of the charge-up control circuit illustrated in Fig. 7; Fig. 9 is a block diagram of a PLL frequency synthesizer according to a third embodiment of the instant invention; Fig. 10 shows a time chart for use in go describing operation of a charge pump circuit of the PLL frequency synthesizer illustrated in Fig. 9; ~Fig. 11 is a block diagram of a PLL frequency synthesizer according to a fourth embodiment of the instant invention; Fig. 12 shows a time chart for use in describing operation of the PLL frequency synthesizer S illustrated in Figs. 1 and 11; Fig. 13 is a block diagram of a PLL frequency synthesizer according to a fifth embodiment of the instant invention; and Fig. 14 shows a block diagram of a PLL frequency synthesizer which modifies the PLL frequency synthesizer illustrated in Fig. 12.

Description of the Preferred Embodiments: Referring to Fig. 1, a conventional PLL frequency synthesizer will be described at first in order to facilitate an understanding of the present invention.

The PLL frequency synthesizer comprises a referencL signal generator 21, a voltage controlled oscillator 22, a variable frequency divider 23, a phase-frequency comparator 24, a charge pump circuit and a loop filter 26.

The reference signal generator 21 generates a ~reference signal with a reference frequency. The voltage 15 controlled oscillator 22 is supplied with a control 0 voltage signal in the manner which will become clear as e the description proceeds. Responsive to the control voltage signal, the voltage controlled oscillator 22 generates a voltage controlled signal having a controllable oscillating frequency. The PLL frequency synthesizer produces the voltage controlled signal as an output signal. Therefore, the output signal has an output frequency equal to the controllable oscillating frequency.

The output signal is supplied to the vaTiable frequency divider 23. The variable frequency divider 23 is also supplied with a designated dividing number D which defines the output frequency, where D represents a positive integer. The variable frequency divider 23 frequency divides the output signal on the basis of the designated dividing number D to produce a divided signal.

In other words, the variable frequency divider 23 is for frequency dividing the output signal by a factor l/D.

The phase-frequency comparator 24 is supplied with the reference signal and the divided signal. The phase-frequency comparator 24 detects a phase-frequency difference between the reference signal and the divided signal to produce a phase-frequency difference signal indicative of the phase-frequency difference. In other words, the phase-frequency difference signal indicates one of lag and lead phases which the divided signal has in comparison with the reference signal.

15 The phase-frequency difference signal is supplied with the charge pump circuit 25. The charge pump circuit 25 acts as a current flow control circuit oeo.

which is for controlling flow-in and flow-out of current supplied therefrom/to to produce a current flow control signal. The current flow control signal indicates the flow-out of the current when the phase-frequency difference signal indicates the lag phase. The current flow control signal indicates the flow-in of the current Swhen the phase-frequency difference signal indicates the lead phase. The current flow control signal is supplied with the loop filter 26. The loop filter filters the current flow control signal into a filtered signal as the control voltage signal, More particularly, the loop I I 8 filter 2' comprises a filter capacitor (not shown) which is selectively charged and discharged when the current flow control signal indicates the flow-out and the flow-in of the current, respectively. At any rate, a combination of the charge pump circuit 25 and the loop filter 26 serves as a control voltage supplying circuit for supplying the control voltage signal to the voltage controlled oscillator in response to the phase-frequency difference signal.

As apparent from the above description, the PLL frequency synthesizer produces the output signal having the output frequency which is equal to D times as large as the reference frequency of the reference signal. It is therefore possible to change the output frequency by *fl.

15 changing the designated dividing number D. In the conventional PLL frequency synthesizer, changing of the o output frequency is carried out by changing step by step i the designated dividing number D. As a result, the *9*4 conventional PLL frequency synthesizer is defective in 2. 0 that it is impossible to change the output frequency at a a high speed, as mentioned in the preamble of the instant specification.

C.P

Referring to Fig. 2, the description will proceed to a PLL frequency synthesizer according to a first embodiment of this invention. The PLL frequency synthesizer is similar in structure and operation to the conventional PLL frequency synthesizer illustrated in Fig. 1 except that the PLL frequency synthesizer further comprises first and second pulse removing circuits 31 and 32.

The first pulse removing circuit 31 is connected between the reference signal generator 21 and the phase-frequency comparator 24. The second pulse removing circuit 32 is connected between the variable frequency divider 23 and the phase-frequency comparator 24.

The first pulse removing circuit 31 is supplied with the reference signal from the reference signal generator 21 and first removing data Al indicative of a first pulse number. Responsive to the first removing data Al, the first pulse removing circuit 31 removes pulses from the reference signal that are equal in number 15 to the first pulse number for a first predetermined cycle S to produce a first pulse removed signal. Instead of the reference signal, the first pulse removed signal is supplied to the phase-frequency comparator 24.

:*ooo.

The second pulse removing circuit 32 is supplied with the divided signal from the variable frequency divider 23 and second removing data A2 indicative of a second pulse number. The second pulse removing circuit 32 removes pulses from the divided signal that are equal in.number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Instead of the divided signal, the second pulse removed signal is supplied to the phase-frequency comparator 24.

Therefore, the phase-frequency comparator 24 detects a phase-frequency difference between the first and the second pulse removed signals to produce a phase-frequency difference signal indicative of the phase-frequency difference.

Turning to Fig. 3, the first pulse removing circuit 31 comprises a first inverter 311, a first counter 312, and a first AND gate 313. The first inverter 311 is supplied with the reference signal from the reference signal generator 21 (Fig. 2) as a first input pulse signal. The first inverter 311 inverts the first input pulse signal to produce a first inverted pulse signal. The first inverter 311 is connected to the first counter 312 which is supplied with the first pulse removing data. The first counter 312 counts up a first count in synchronism with the first inverted pulse 0* signal. The first counter 312 produces a first time-up signal when the first count increases up to the first *pulse number. The first time-up signal is supplied to the first AND gate 313 which is supplied with the first input pulse signal. Responsive to the first input pulse signal and the first time-up signal, the first AND gate 313 produces a first AND'ed signal as the first pulse removed signal.

Similarly, the second pulse removing circuit 32 comprises a second inverter 321, a second counter 322, and a second AND gate 323. The second inverter 321 is supplied with the divided signal from the variable 11 frequency divider 23 (Fig. 2) as a second input pulse signal. The second inverter 321 inverts the second input pulse signal to produce a second inverted pulse signal.

The second inverter 321 is connected to the second counter 322 which is supplied with the second pulse removing data. The second counter 322 counts up a second count in synchronism with the second inverted pulse signal. The second counter 322 produces a secr,,.d time-up signal when the second count increases up to the second pulse number. The second time-up signal is supplied to the second AND gate 323 which is supplied with the second input pulse signal. Responsive to the second input pulse signal and the second time-up signal, the second AND gate 323 produces a second AND'ed signal as the second pulse e ee eeoe 15 removed signal.

Turning to Figs. 4(a) through description will be made as regards operation of the first pulse removing circuit 31. The first input pulse signal is depicted along Fig. The first input pulse signal is inverted by the first inverter 311 into the first S" inverted pulse signal as shown in Fig. The first egO e inverter 311 has an inverting delay time denoted to dl.

It will be assumed that the first counter 312 is supplied with the first pulse removing data indicative of the first pulse number equal to four. In this event, the first counter 312 counts up the first count at a leading edge of each pulse in the first inverted pulse signal. The first counter 312 produces the first time-up 12 signal of a logical level when the first count increases up to the first pulse number, namely, four, as shown in Fig. The first counter 312 is reset to produce the first time-up signal of a logical level in response to another leading edge of the next succeeding pulse of the first inverted pulse signal. The first counter 312 has a counting delay time denoted to d2. Under the circumstances, the first AND gate 313 produces the first AND'ed signal as the first pulse removed signal as shown in Fig. That is, the first AND gate 313 produces the first pulse removed signal having pulses which is one-fifth as large as those of the first input pulse signal. In other words, the first pulse removing circuit 31 removes four pulses from the 15 reference signal for the first predetermined cycle which has five pulses. The first AND gate 313 has a gate delay time denoted to d3.

If the first pulse removing data indicates the first pulse number equal to zero, the first counter 312 continuously produces the first time-up signal with the logical level. In this event, the first AND gate 313 produces the first pulse removed signal to which the first input pulse signal is delayed for the gate delay time t3 by the first AND gate 313 as shown in Fig. 4(e).

Operation of the second pulse removing circuit 32 is similar to that of the first pulse removing circuit 31 and the description thereof is therefore omitted.

Referring to Fig. 5, the description will Y I 1 -13proceed to a PLL frequency synthesiser according to a second embodiment of this invention. The PLL frequency synthesiser is similar in structure and operation to the conventional PLL frequency synthesiser illustrated in Fig. 1 except that the PLL frequency synthesiser further comprises a current controlling circuit The current controlling circuit 35 is connected to the charge pump circuit and is supplied with a current command C. Responsive to the current command C, the current controlling circuit 35 controls the current for the charge pump circuit 25. More specifically, the current command C is present while the output fr6quency is changed.

The current controlling circuit 35 controls the current so as to increase the current when the current command C is present and then to gradually decrease the current after the current command C becomes absent. A little more in detail, the current controlling circuit 35 comprises a charge-up control circuit and a discharge control circuit. The current command C comprises charge-up and discharge indication signals. The chargeup and discharge indication signals of the current command are present one at a time while the output frequency is changed. In a manner which will later become clear, the charge-up control circuit controls charge-up of the loop filter in response to the chargeo-up indication signal while the discharge control circuit controls discharge of the loop o° :filter in response to the discharge indication signal.

V'2 Turning to Fig. 6, the charge pump circuit 25 comprises a complementary- 20 symmetry metal-oxide-semiconductor field-effect transistor (CMOSFET) which consists of a p-channel MOSFET 36 and an n-channel MOSFET 37. Each of the MOSFETs 36 and 37 has a gate terminal, a drain terminal, and a source terminal. The p-channel and the n-channel MOSFETs 36 and 37 are joined at their drain terminals which are connected to the loop filter 26 (Fig. The p-channel MOSFET 36 has the source terminal o (n:\llbk0005:HRW 14 which is connected to the charge-up control circuit of the current controlling circuit 35. The n-channel MOSFET 37 has the source terminal which is connected to the discharge control circuit of the current controlling circuit 35. Both of the p-channel and the n-channel MOSFETs 36 and 37 have the gate terminals which are connected to the phase-frequency comparator 24 (Fig. More particularly, the phase-frequency difference signal comprises lag and lead phase signals which indicate the lag and the lead phases, respectively. The lag phase signal is supplied to the gate terminal of the p-channel MOSFET 36. The lead phase signal is supplied to the gate terminal of the n-channel MOSFET 37.

Supplied with the lag phase signal, the 15 p-chanrel MOSFET 36 is put into an ON state, thereby the current flows from the charge-up control circuit to the loop filter 26 through the p-channel MOSFET 36. Supplied with the lead phase signal, the n-channel MOSFET 37 is put into an ON state, thereby the current flows from the loop filter 26 to the discharge control circuit through the n-channel MOSFET 37.

Turning to Fig. 7, the charge-up control circuit of the current controlling circuit 36 comprises a switching element 41, an operational amplifier 42, an n-channel MOSFET 43, first and second p-channel MOSFETs 44 and 45, first through third resistors 46, 47, and 48, and a capacitor 49. The operational amplifier 42 has an inverting input terminal, a noninverting input terminal,

I

and an amplifier output terminal.

The switching element 41 has a control input terminal supplied with the charge-up indication signal of the current command C. The switching element 41 is supplied with a positive source voltage +VDD. The switching element 41 is connected to the noninverting input terminal of the operational amplifier 42. When the charge-up indication signal of the current command C is present or has a logic one value, the switching element 41 turns on, thereby the positive source voltage +VDD is supplied to the noninverting input terminal of the operational amplifier 42. The inverting input terminal of the operational amplifier 42 is an end of the first resistor 46 which has another end grounded. The noninverting input terminal of the operational amplifier 42 is connected to an end of the second resistor 47 which has another end grounded. The second resistor 47 is connected to the capacitor 49 in parallel. The noninverting input terminal of the operational amplifier 42 is also connected to an end of the third resistor 48 which has another end supplied with the positive source voltage +VDD. The amplifier output terminal of the operational amplifier 42 is connected to the gate terminal of the n-channel MOSFET 43 which has the source terminal connected to the inverting input terminal of the operational amplifier 42.

The n-channel MOSFET 43 has the drain terminal which is connected to the drain terminal of the first p-channel MOSFET 44. The drain terminal of the n-channel 20 MOSFET 43 is also connected to the gate terminals of the first and the second pchannel MOSFETs 44 and 45. Both of the first and the second p-channel MOSFETs 44 and 45 have the source terminals which are supplied with the positive source voltage +VDD. The second p-channel MOSFET 45 has the drain terminal which is connected to the source terminal of the p-channel MOSFET 36 (Fig. Therefore, a 25 combination of the first and the second p-channel MOSFETs 44 and 45 composes a current Miller circuit. The second p-channel MOSFET 45 has a gate width which is N times as large as that of the first p-channel MOSFET 44, where N represents a predetermined number. When a first drain current D 1 flows through the n-channel MOSFET 43, through the second p-channel MOSFET 45 flows a second drain current

D

2 which is N times as large as the first drain current D 1 /~i In:\llbkl00065:HRW p Turning to Figs. 8(a) through description will be made as regards operation of the charge-up control circuit of the current controlling circuit 36 illustrated in Fig. 7. It will be assumed that the first through the third resistors 46 to 48 have first through third resistance values, respectively, which are denoted to R 46

R

47 and R 48 The third resistance value R 4 8 is larger than the second resistance value R47. Figs. 8(a) through show the current command C (the charge-up indication signal), and the first and the second drain currents D 1 and D 2 respectively.

When the charge-up indication signal of the current comnmand C is present or becomes the logic one value at a time instant to, the switching element 41 turns on.

Therefore, the capacitor 49 is charged up to a voltage of VDD. Through the n-channel MOSFET 43 flows the first drain current D 1 which has a current value of VDD/R46- Therefore, through the second p-channel MOSFET 45 flows the second drain current

D

2 which has a current value of N x VDD/R46.

When the charge-up indication signal of the current command C becomes 1i absent or the logic zero value at a time instant tl, the switching element 41 turns off.

Therefore, the capacitor 49 is exponentially discharged up to a voltage of R 47

/(R

47

R

48 x VDD. As a result, the first drain current D 1 exponentially decreases up to a current value of (R 47

/(R

47 R48)) x VDD/R46. Accordingly, the second drain current

D

2 exponentially decreases up to a current value of N x (R 47

/(R

47

R

48 x VDD/R46.

20 At any rate, the charge-up control circuit of the current controlling circuit carries out, in response to the charge-up indication signal of the current command C, charge-up of the loop filter through the p-channel MOSFET in the charge pump circuit when the pchannel MOSFET is put into the ON state.

The discharge control circuit of the current controlling circuit 35 is similar in structure and operation to the charge-up control circuit illustrated in Fig. 7 except that the n-channel MOSFET 43 is replaced with a p-channel MOSFET, the p-channel MOSFETs 44 and 45 are replaced with n-channel MOSFETs, the positive source voltage +VDD and the ground are exchanged with each other, and the discharge control circuit is supplied with the discharge indication signal of the current command C in place of the charge-up indication signal. In operation which is similar to that of the charge-up control circuit, the discharge control circuit carries out, in response to the fw~; In:\llbk)00065:HRW -17discharge indication signal of the current command, discharge of the loop filter through the n-channel MOSFET in the charge pump circuit. As a result, the charge-up and the discharge of the loop filter are independently controlled by the charge-up control circuit and the discharge control circuit, respectively.

Referring to Fig. 9, the description will proceed to a PLL frequency synthesiser according to a third embodiment of this invention. The PLL frequency synthesiser is similar in structure and operation to the conventional PLL frequency synthesiser illustrated in e* *o In:\libkj00065:HRW 18 Fig. 1 except that the charge pump circuit is modified from that illustrated in Fig. 1 as will later become clear. The charge pump circuit is therefore depicted at The illustrated charge pump circuit comprises a control circuit 51, a constant current circuit 52, an integrating circuit 53, and a sample and hold circuit 54.

The control circuit 51 is connected to the phase-frequency comparator 24. Responsive to the phase-frequency difference signal, the control circuit 51 produces first through third control signals. The first ee*o through the third control signals are supplied to the constant current circuit 52, the integrating circuit 53, oloo 15 and the sample and hold circuit 54, respectively.

:....Responsive to the first control signal, the constant current circuit 52 produces a constant current.

The constant current is supplied to the integrating circuit 53. The integrating circuit 53 has an initial *see 20 voltage. The integrating circuit 53 integrates the oe constant current to an integrated voltage. The integrating circuit 53 is reset from the integrated voltage to the initial voltage in response to the second control signal. The integrated voltage is supplied to the sample and hold circuit 54. Responsive to the third control signal, the sample and hold circuit 44 samples the integrated voltage to hold a sampled voltage as a held signal. The sample and hold circuit 44 supplies the 19 held signal to the loop filter 26 as the current flow control signal.

Referring to Fig. 10 in addition to Fig. 9, description will be made as regards operation of the charge pump circuit 25a. In Fig. 10, the lag phase signal, the constant current, the integrated voltage, and the held signal are depicted along first through fourth lines.

As shown in the first line in Fig. 10, the lag phase signal is supplied from the phase-frequency comparator 24 to the control circuit 51 during a first time duration between a first time instant t I and a second time instant t 2 Under the circumstances, the 9 9e control circuit 51 produces the first control signal oooo 15 during a second time duration between the first time instant t 1 and a third time instant t 3 Responsive to the first control signal, the constant current circuit 52 produces the constant current during the second time see* duration as shown in the second line in Fig. Therefore, the integrating circuit 53 integrates the S constant current to the integrated voltage during the second time duration as shown in the third line in Fig.

After the third time instant t 3 the integrating circuit 53 keeps the integrated voltage. At a fourth time instant t 4 the control circuit 51 produces the third control signal. Responsive to the third control signal, the sample and hold circuit 44 samples the integrated voltage to hold a sampled voltage as a held signal at a fifth time instant t 5 The held signal is supplied to the loop filter 26 as the current flow control signal. At a sixth time instant t 6 the control circuit 51 produces the second control signal.

Responsive to the second control signal, the integrating circuit 53 is reset from the integrated voltage to the initial voltage. Therefore, the charge pump circuit increases a level of the current flow control signal in response to the lag phase signal. In the similar operation, the charge pump circuit 25a decreases the level of the current flow control signal in response to the lead phase signal.

It is understood that it is possible to set a desired value to a gain of the charge pump circuit 25a by ee n 15 changing the ratio of the first time duration to the second time duration.

':Referring to Fig. 11, the description will proceed to a PLL frequency synthesizer according to a 9.

fourth embodiment of this invention. The PLL frequency 20 synthesizer is similar in structure and operation to the ooe co ~conventional PLL frequency synthesizer illustrated in O 0 Fig. 1 except that the PLL frequency synthesizer further comprises a control circuit The control circuit 60 is connected between the phase-frequency comparator 24 and the charge pump circuit The control circuit 60 is supplied with a control enable signal CE. Responsive to the control enable signal CE, the control circuit 60 acts as a modifying arrangement for modifying the phase-frequency difference signal into a modified signal. Instead of the phase-frequency difference signal, the modified signal is supplied to the charge pump circuit 25. Therefore, the charge pump circuit 25 controls, in response to the modified signal, flow-in and flow-out of the current supplied therefrom/to to produce the current flow control signal. A little more in detail, tha control circuit is operable in one of a first mode and a second mode. At first, the first mode will be described. The second mode will be described later in the following.

In the first mode, the control enable signal CE is present while the output frequency is changed. The phase-frequency difference signal comprises a pulse 15 sequence having pulses for a predetermined cycle that are equal in number to a controllable number. When the control enable signal CE is present, the control circuit gradually decreases the controllable number until at last a predetermined final number. The predetermined e final number is, for example, one sixty-fourths as large as the controllable number before being decreased.

Fig. 12 shows transient responses of the output frequency in the conventional PLL frequency synthesizer (Fig. 1) and the PLL frequency synthesizer according to the fourth embodiment. In Fig. 12, a transient response for the conventional PLL frequency synthesizer is depicted at a solid line. Another transient response for the PLL frequency synthesizer accor3ing to the fourth embodiment is depicted at a dotted line. As apparent from Fig. 12, it is possible to raise up the transient response by decreasing the controllable number.

In the second mode, the control enable signal CE is present in a steady state of the PLL frequency synthesizer. The phase-frequency difference signal comprises a pulse sequence having pulses each of which has a controllable pulse width. The control circuit narrows the controllable pulse width when the control enable signal CE is present. It is possible to improve unstableness in the PLL frequency synthesizer.

~Referring to Fig. 13, the description will proceed to a PLL frequency synthesizer according to a fifth embodiment of this invention. The PLL frequency synthesizer is similar in structure and operation to the conventional PLL frequency synthesizer except that the PLL frequency synthesizer further comprises a switch a reset circuit 66, a control circuit 70, and a digital-analog converter 71.

eooe The control circuit 70 is supplied with the designated dividing number D, the divided signal, the *O08** phase-frequency difference signal. On changing the output frequency, the control circuit 70 produces first and second control signals. The control circuit 70 also produces voltage data on changing the output frequency.

The voltage data represents a control voltage which is defined by the designated dividing number D on the basis of the phase-frequency difference signal. The control I I circuit 70 determines the voltage data by carrying out binary search on the phase-frequency difference signal.

The switch 65 is inserted between the loop filter 26 and the voltage controlled oscillator 22. The switch 65 is supplied with the first control signal. The switch 65 switches off in response to the first control signal.

The loop filter 26 comprises first and second resistors 261 and 262 and a filter capacitor 263. The first resistor 261 has one end connected to the charge pump circuit 25 and has another end connected to the switch 65 and to one end of the second resistor. The second resistor 262 has another end connected to one end of the filter capacitor 263 which has another end eeoc 15 grounded.

The digital-analog converter 71 is supplied with the voltage data from the control circuit 70. The digital-analog converter 71 is activated only when the output frequency is changed. The digital-analog converter 71 converts the voltage data into the control voltage. The control voltage is supplied to the voltage controlled oscillator 22 and the filter capacitor 263 of the loop filter 26.

Responsive to the second control signal, the charge pump circuit 25 is unactivated or put into a high impedance state.

The reset circuit 66 is inserted between the reference signal generator 29 and the phase-frequency

II~

comparator 24. On the basis of the divided signal, the control circuit 70 controls the reset circuit 66 so as to make the reset circuit 66 produce a reset signal which has a phase equal to that of the divided signal. The reset signal is supplied to the phase-frequency comparator 24 instead of the reference signal.

In the PLL frequency synthesizer illustrated in Fig. 13, the digital-analog converter 71 supplies the control voltage to both of the voltage controlled oscillator 22 and the filter capacitor 263 of the loop filter 26. The digital-analog converter 71 may be modified into first and second digital-analog converters 71 and 72 as shown in Fig. 14. Under the circumstances, 9

S

the first digital-analog converter 71 supplies the 15 control voltage to the voltage controlled oscillator 22.

The second digital-analog converter 72 supplies the control voltage to the filter capacitor 263 of the loop filter 26.

.5 *tow 4 I

Claims

1. A frequency synthesiser comprising: a reference signal generator for generating a reference signal with a reference frequency; a voltage controlled oscillator responsive to a control voltage signal for generating an output signal having an output frequency; a variable frequency divider supplied with said output signal and responsive to a designated dividing number defining said output frequency for frequency dividing said output signal on the basis of said designated dividing number to produce a divided 1 o signal; a phase-frequency comparator supplied with said reference signal and said divided signal for detecting a phase-frequency difference between said reference signal and said divided signal to produce a phase-frequency difference signal indicative of one of lag and lead phases which said divided signal has in comparison with said reference signal, said phase-frequency difference signal comprising lag and lead phase signals which indicate the lag and the lead phases, respectively; a current flow control circuit responsive to said phase-frequency difference signal for controlling flow-in and flow-out of current supplied therefrom/to to produce a current flow control signal, said current flow control circuit consisting of a p-channel 20 MOSFET and an n-channel MOSFET each of which has a gate terminal, a drain terminal, and a source terminal and which are joined at the drain terminals thereof, the gate terminal of said p-channel MOSFET being supplied with said lag phase signal, the gate terminal of said n-channel MOSFET being supplied with said lead phase signal, said p-channel MOSFET being put into an ON state in response to said lag phase S 25 signal, said n-channel MOSFET being put into an ON state in response to said lead phase signal; a loop filter supplied with said current flow control signal for filtering said current flow control signal into a filtered signal as said control voltage signal; and a current controlling circuit responsive to a current command for controlling said current supplied from/to said current flow control circuit, said current command comprising charge-up and discharge indication signals, said current controlling circuit comprising a charge-up control circuit and a discharge control circuit, said charge-up control circuit being supplied with said charge-up indication signal and being connected to the source terminal of said p-channel MOSFET, said discharge control circuit being supplied with said discharge indication signal and being connected to the source terminal of said n-channel MOSFET, whereby said charge-up control circuit carries out, in response to said charge-up indication signal, charge-up of said loop filter through said p-channel MOSFET when said p-channel MOSFET is put into the ON state while said discharge control circuit carries out, in response to said discharge In:\llbk100065:HRW -26- indication signal, discharge of said loop filter through said n-channel MOSFET when said n-channel MOSFET is put into the ON state.

2. A frequency synthesiser as claimed in claim 1, the charge-up and discharge indication signals of said current command being present one at a time while said output frequency is changed, wherein said charge-up control circuit of said current controlling circuit controls said current so as to increase said current when the charge- up indication signal of said current command is present and then to gradually decrease said current after the charge-up indication signal of said current coinmand becomes absent, said discharge control circuit of said current controlling circuit controls said current so as to increase said current when the discharge indication signal of said current command is present and then to gradually decrease said current after the discharge indication signal of said current command becomes absent.

3. A frequency synthesiser as claimed in claim 2, wherein said charge-up control circuit of said current controlling circuit comprises: a primary operational amplifier having a primary inverting input terminal, a primary noninverting input terminal, and a primary amplifier output terminal, the I"..primary inverting input terminal being grounded via a first primary register, the primary noninverting input terminal being grounded via a second primary resistor and a primary capacitor which are connected with each other in parallel, the primary noninverting input terminal being supplied with a positive source voltage via a third primary resistor; a primary switching element, supplied with the charge-up indication signal of said the current command and the positive source voltage and connected to the primary noninverting input terminal of said primary operational amplifier, for turning on when the charge-up indication signal of the current command is present to supply the positive source voltage to the primary noninverting input terminal of said first operational e amplifier; i a primary n-channel MOSFET having a primary gate terminal connected to the .i primary amplifier output terminal and a primary source terminal connected to the primary inverting input terminal of said primary operational amplifier; and a primary current Miller circuit connected to a primary drain terminal of said primary n-channel MOSFET, the source terminal of said p-channel MOSFET in said current flow control circuit and supplied with the positive source voltage; and wherein said discharge control circuit of said current controlling circuit comprises: a secondary operational amplifier having a secondary inverting input terminal, a secondary non-inverting input terminal, and a secondary amplifier output terminal, the secondary inverting input terminal being supplied with the positive source voltage Bvia a first secondary register, the secondary noninverting input terminal being supplied In:\Iibk00lO65:HRW L r witi: the positive source voltage via a second secondary resistor and a secondary capacitor which are connected with each other in parallel, the secondary noninverting input terminal being grounded via a third secondary resistor; a secondary switching element, supplied with the discharge indication signal of the current command and ground voltage and connected to the secondary noninverting input terminal of said secondary operational amplifier, for turning on when the discharge indication sigr 1. of said the current command is present to supply the ground voltage to the secondary noninverting input terminal of said secondary operational amplifier; a secondary p-channel MOSFET having a secondary gate terminal connected to the secondary amplifier output terminal and a secondary source terminal connected to the secondary inverting input terminal of said secondary operational amplifier; and a secondary current Miller circuit connected to a secondary drain terminal of said secondary p-channel MOSFET, the source terminal of said n-channel MOSFET in said current flow control circuit and supplied with the ground voltage. DATED this Ninth Day of August 1994 NEC Corporation 9**aa* 20 Patent Attorneys for the Applicant SPRUSON FERGUSON t o A *"i (n:\libk]00065:HRW PLL Frequency Synthesizer Capable of Changing an Output Frequency at a High Speed ABSTRACT A frequency synthesizer comprises, a first pulse removing circuit (31) connected between a reference signal generator (21) and a phase-frequency comparator A second pulse removing circuit (32) is connected between a variable frequency divider (23) and the phase-frequency comparator Responsive to first removing data, indicative of a first pulse number, the first pulse removing circuit (31) removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Responsive to second removing data, indicative of a second pulse number, the second pulse removinc circuit (32) removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. Responsive to a current command, a current controlling circuit (35) may control current supplied from/to a charge pump circuit connected with the phase-frequency comparator A switch (65) may be inserted between the loop filter (26) and the voltage controlled oscillator Nhen the switch switches oft, a D/A converter (71,72) supplies a control voltage to the voltage controlled oscillator (22) and a filter capacitor (263) of the loop filter The charge pump circuit (25) may comprise a control circuit a constant current circuit an integrating circuit and a sample and hold circuit (54). .0 (Figure 2) *9 (Figure 2) BFD/314K