GB2293063A

GB2293063A - Phase lock loop circuits

Info

Publication number: GB2293063A
Application number: GB9518537A
Authority: GB
Inventors: Erkki Rantakari
Original assignee: Nokia Telecommunications Oy
Current assignee: Nokia Oyj
Priority date: 1994-09-09
Filing date: 1995-09-11
Publication date: 1996-03-13
Anticipated expiration: 2015-09-11
Also published as: DE19534516A1; FI97093B; GB9518537D0; FI944181A; FI97093C; FI944181A0; GB2293063B

Description

1 Fast locking phase-locked loop 2293063 This invention relates to a

phase-locked loop circuit comprising a loop filter the cut-off frequency or time constant of which may be changed.

A typical phase lock loop (PLL) generally comprises a voltage- controlled oscillator, a phase detector and a low-pass filter. A reference signal is applied to a first input of the phase detector, and the feedback output signal of the oscillator, providing also an output signal for the loop, is applied to a second input of the phase detector.

The phase detector detects a phase difference between the input signals and generates an output signal which is proportional to the phase difference, and applied to a low-pass filter which functions as a loop filter. Its output voltage, in turn, provides the control voltage for the voltage-controlled oscillator. When the loop is in balance, the phase of an output frequency signal is locked onto the phase of a reference frequency signal. In several applications, such as frequency synthesizers, a feedback path is equipped with a loop divider the division ratio of which may be changed by means of programming. Thus, the frequency of the output signal is divided prior to applying the signal to the phase detector, which enables forming frequencies that are considerably higher than the reference frequency, yet locked onto it.

The phase lock must be constructed so as to maintain its balance and prevent the output signal from modulating despite rapid fluctuation, such as jitter, occurring in either of the input signals, and, on the other hand, to enable a minimal signal acquisition time when the output frequency is changed. Great demands are thus made on the loop filter, the demands being inconsistent with each other. When the loop is locked, the 2 is cut-off frequency of the filter must be low so that the noise of the input signal is not resulted in modulation at the output. A narrow bandwidth of the filter is, however, a disadvantage during the change while locking onto a new frequency e.g. when the division ratio of the divider is changed. To enable a short signal acquisition time, it is previously known to arrange, in a way or another, the cut-off frequency of the loop filter to be high during the change. It is possible to use two parallel loop filters and switch, by means of a controlled change- over switch, the filter with a broad bandwidth into a loop filter for the time of the change, and the filter with a narrow bandwidth once the loop has achieved its balance. The filter may also be completely bypassed for the time of the change. An arrangement is also possible by means of which the resistance of a filter, normally of an RC low-pass filter is reduced by means of switching resistors for the time of the change. It is also previously known to use charge pumps to accelerate charging or discharging of the capacitor of the filter.

In U.S. Patent 5272452, a filter comprises two parallel filters, the first filter comprising successive RC-circuits and the second filter comprising only one RC-circuit having a common capacitor with the last RCcircuit of the first filter. By means of a switch, either of the filters is chosen as the loop filter. Japanese Patents 61-60670 and 1- 332362 disclose a few solutions in which the value of the resistor of the loop filter is changed. In the former, the first resistor of an active filter is chosen by means of a switch, whereas in the latter, one resistor of a passive filter is bypassed with a transistor switch. The drawback of solutions of this kind in which only one parameter is changed is that locking cannot be accelerated suffi- 3 ciently when the phase lock has a very narrow bandwidth. In addition, a switch transistor in a state of saturation causes noise to the control voltage of the VCO, as well as switching transients.

A solution employing charge pumps is disclosed in U.S. Patent 4546330. In the solution, a low-pass filter comprises a capacitor and a plurality of resistors connected in series. In addition, pump circuits, which are the same in number as said resistors, are connected to the filter. By choosing one pump circuit at a time to be used, the cut-off frequency of the filter may be set stepwise. The principle is shown in Figure 1. A filter comprises two similar pump circuits Pl and P2. A pump circuit comprises AND- and AND-NOT gates, diodes Dl and D2, and resistors Rl and R2 as shown in Figure 1. Signals Up and Down supplied by the phase detector are provided as input signals, as well as signal FAST, which is applied inverted to pump circuit P1. The phase detector used herein is one that gives signal Up or Down depending on whether the pulse of the reference signal leads or lags behind the feedback signal. Signal FAST is high when the filter is desired to have a broad bandwidth. The filter actually comprises the resistors of the pump circuits and resistors R5 and R6, and a capacitor C. The operation is briefly as follows: let us assume that signal FAST is high (the filter has a broad bandwidth), and similarly, signal Up is high. It can be easily found that the state of the gates is such that pump circuit Pl is in an inoperative state and has no effect on coupling. Pump circuit P2 is active, and the resistive part of the filter is composed of the series connection of resistor R3 or R4 of pump circuit P2, depending on the state of signals Up and Down, and of resistor R6. Correspondingly, when signal FAST is low, pump circuit P1 is activated and P2 is in an inop- 4 erative state. The resistive part of the filter is now composed of the series connection of resistor R3 or R4 of pump circuit Pl, depending on the state of signals Up and Down, and of resistors R5 and R6. The drawback, however, is rather a complicated implementation.

Solutions in which the filter is completely bypassed during the change are disclosed in German Offenlegungsschrift 2951283 and Japanese Patent 2265865. In the former, the resistor of a simple RC filter is bypassed with a transistor switch in a state of change, whereas in the latter, a f ilter or a part of it is bypassed by means of a switch. Bypassing a f ilter during the change means that a phase lock changes into a phase lock of the second degree. This is disadvantageous since the jitter coming from the phase detector has a direct access to the control voltage of the VCO. This causes the phenomenon that when the loop filter is re-switched to a narrow bandwidth, the output frequency of the lock may deviate a great deal of the correct frequency, which may even prolong the total locking time.

Claims

The object of this invention is a fast locking phase lock with no external

control, having none of the above described drawbacks despite the fact that characteristics of the loop filter are changed. The phase lock is characterized in what is claimed in claim 1.

In the phase lock of the invention, the length of the pulse of the signal obtained from the phase detector is monitored in the monitoring circuit. If the length is greater or smaller than the set value, the monitoring circuit interprets that the phase lock is in an unlocked state, i.e. the output frequency has not yet locked onto the frequency of the input signal, and provides the first logical signal corresponding to the information. The monitoring circuit forms a window and examines whether the output of the phase lock is within the window i. e. whether the lock is locked. When the value is between the set values, i.e. the output is within the window, the monitoring circuit interprets that the phase lock is locked, and generates a second logical signal corresponding to it. The logical signals are delayed for a certain delay-time in a delay means, the output of which is the control signal of the filter. The delay means is resettable, i.e. at certain intervals it examines the state of the input signal, and maintains the state of the output unchanged in case the input signal has not changed within this interval. Changes in the input signal during the delay-time thus do not have any effect on the state of the output. The delay means may thus practically be a monostable multivibrator or a resettable chain of counters.

Let us assume that the first logical signal is provided as an input (= the lock is unlocked). The control signal of the filter obtained from the delay means thus maintains the bandwidth of the filter broad. After the delay-time it is examined whether the input signal of the delay means has changed. If it has not changed, the control signal is still maintained unchanged. If, however, the input signal has changed to another signal, i. e. the length of the pulse of the output of the phase detector has reached the window of the monitoring circuit, the control signal of the filter is changed, and switches the filter to a narrow bandwidth. Delay is an essential part of the monitoring circuit for locking, as the hysteresis caused by the delay prevents the filter from changing its state too easily, thus the filter is switched to a narrow bandwidth only when one is sure that locking has taken place.

Furthermore, the filter is characterized in that when its bandwidth is changed, the capacitance value is also changed. Changing the value of the 6 capacitor enables a great difference between the broad and the narrow bandwidth of the f ilter, which enables implementing a phase lock having a very narrow bandwidth. Furthermore, the capacitor is arranged in the way that when switching the filter to a narrow bandwidth, no switching transient is caused. In addition, the coupling comprises at least two switches. The use of two switches enables optimizing both attenuation and bandwidth independently.

The invention will be described more detailed by means of the attached figures, in which Figure 1 shows a prior art phase locked loop, Figure 2 shows the principle of the phase locked loop of the invention, Figure 3 shows a loop f ilter coupling in principle, in accordance with the phase lock of the invention, and Figure 4 is a monitoring circuit for locking, implemented with counters.

Figure 2 is a block diagram of the phase lock of the invention. Pulses obtained from a phase detector 21 and going to a loop f ilter 22 are monitored in a monitoring circuit 23 for locking. The circuit observes whether the length of the pulse fits the set window or not. If the length of the pulse is greater or smaller than the set value, the circuit 23 controls the loop circuit to have a broad bandwidth, and maintains it as such until locking takes place. When the monitoring circuit for locking detects that locking has taken place, it provides the filter with a control signal, and the filter is switched to a narrow bandwidth.

Figure 3 showing principles of coupling illustrates a filter of an analogue phase lock. At the input In of the filter, there is a signal Pha provided by a XOR-type phase detector. The phase detector of said type 7 provides a pulse when the pulses of the input signal and the output signal of the phase lock loop are in a different state. The output voltage Out of the filter is the regulating voltage of a voltage controlled oscillator VCO. The monitoring circuit for locking comprises comparators OP1 and OP2, the outputs of which are connected as inputs of an OR gate. There is a constant voltage obtained from a voltage divider Rl, R2, R3 at the second input of both comparators, i.e. constant voltage V1 at the input of comparator OP1 and constant voltage V2 at the input of comparator OP2. There is the voltage V, of a filter capacitor Cl at the second input of the comparators. Since voltage V, depends on the length of the pulse provided by the phase detector, this voltage may be compared with voltages V1 and V2. When the voltage V, of the capacitor exceeds the upper set voltage V1, the state of the output of comparator OP1 switches to logical "1", and correspondingly, when the voltage of the capacitor is lower than the lower set voltage, the state of the output of comparator OP2 switches to logical "V'. This is the first logical signal. When the voltage of the capacitor is between the set voltages, logical "0" is provided as an output of both comparators. This is the second logical signal. This means that if the input signal Pha is longer or shorter than the set signal, the first logical signal, such as a positive pulse is provided by OR gate, said signal reporting that the phase lock is not locked onto the reference frequency, and the second signal is obtained after the locking has taken place.

A logical signal provides an input for a resettable delay means 21, which examines, at certain intervals, the state of the input. If the input equals to the first logical signal, i.e. it is positive, the delay means sets its output, which provides the control signal 8 for the filter Cntrl, to state "0". In this state, the control signal is termed the first control signal, and it maintains the bandwidth of the filter broad. Again, the delay means examines the state of its input at certain intervals. If it still equals to the first logical signal, Cntrl will remain in state "0", but if the input has switched into the second logical signal which indicates locking of the phase lock, the control signal Cntrl of the filter will switch to state "1". In this state, the control signal is termed the second control signal. A suitable delay-time is e.g. 2 s, in which case oscillation between the lock-in state and the unlocked state can not be perceived in the control signal.

The control signal Cntrl controls switches S1 and S2 so that when the signal is in state "0", which means as described above, that the lock is unlocked, the switches are in the upper position and correspondingly, when the control signal Cntrl is in state "1" (the lock is locked), the switches are in the lower position. Depending on the position of the switches, the filter either has a narrow or a broad bandwidth. A filter with a narrow bandwidth comprises components R4, R5, Cl, R7, C3, C2 and OP4. A filter with a broad bandwidth comprises components R4, Cl, R5, R6, C2 and OP4.

Let us assume now that the phase lock is setting onto a new frequency since e.g. the division ratio of the loop divider has been changed. Thus, the monitoring circuit for locking detects that voltage Vc is not within the window V1... V2. The output of OR device is high, and the output signal of the delay means Cntrl is low, and switches S1 and S2 are in the upper position, which means that the loop filter has a broad bandwidth and comprises the successive RC-circuit (an integrator) R4, Cl, an amplifier OP4 coupled as an integrator the feedback path of which comprises a resistor R6 and a 9 capacitor C2, and a resistor R5 connecting the integrators. As switch S2 is in the upper position, the large capacitor C3 has no ef f ect on the operation of the filter, but, its voltage is proportional to the voltage of capacitor C2, since the voltage of C2 is at the input of the amplifier OP3 coupled as a buffer. The output of the buffer is proportional to the input voltage, yet separated from it.

When the monitoring circuit for locking has detected that locking has taken place, the monitoring circuit provides a second control signal, i.e. the control signal Cntrl rises up, and switches Sl and S2 turn to their lower position. In that case, the filter coupling comprises an RC loop (an integrator) R4, Cl, an amplifier OP4 coupled as an integrator the feedback path of which comprises a resistor R7 and capacitors C2 and C3 connected in parallel, and a resistor R5 connecting the integrators. A difference with the narrow bandwidth mode is, first of all, that the resistance value of the feedback path has changed, and secondly, that capacitor C3 has been connected in parallel with capacitor C2 via switch S2. Since capacitor C3 is charged to the voltage value of C2 in the broad bandwidth mode, no additional transient is caused after the loop has been locked when the filter is switched to a narrow bandwidth.

In this coupling, the RC-feedback path of the operation amplifier OP4, the feedback path also determining the time constant is, depending on the mode, either R6, C2 or R7, C2 and C3. Thus, by changing the value of both the resistor and the capacitor, both the bandwidth of the loop and the value of the attenuation coefficient may be changed, and the speed of the locking may thus be optimized. Therefore, the switches are necessary. For example, if switch Sl were omitted from the coupling, and the coupling comprised one resistor only, or if resistors R6 and R7 were of an equal size, the attenuation coefficient of the filter would be so small in a broad bandwidth mode that no locking would take place. Now, instead, the proportion of R6 and R7 is chosen to be about a decade, in which case a smaller resistor R6 is chosen with switch S1 to enable rapid locking. Simultaneously, a small value is set as a capacitance (C2) by means of switch S2, which also accelerates locking. In a narrow bandwidth mode, in turn, a larger resistor R7 and a large capacitor, i.e. a parallel connection of C2 and C3 are chosen, C3 being charged to the value of C2 in advance to avoid transient.

Unlike with prior art filters, the value of the capacitor also changes in accordance with the locking state. Therefore, there may be a great difference between the broad and the narrow bandwidth mode, and it is possible to implement a phase lock with a very narrow bandwidth. The bandwidth may be e.g. 0. 7 Hz when the loop is in lock-in state, and 10 Hz during locking.

The monitoring circuit for locking of the invention may be implemented both digitally and analogically. If the application environment is digital and includes e.g. programmable logic circuits, a digital monitoring circuit for locking is advantageous. In that case, instead of comparators, counters in accordance with Figure 4 are used. In this example, the locking frequency of the loop is assumed to be 16 kHz. The counters are timed with 512-kHz clock pulses. If either of the counters reaches the count of nine, the input "1" is provided for a digitally implemented delay circuit, as a result of which the output is let to state "0" for two seconds. After this time, it is checked if the state of the input has changed.

The monitoring circuit for locking, as well as the actual filter may be implemented in a variety of 11 ways, as the attached claims set no limits to the prac- tical implementation of the invention.

12 Claims A phase locked loop comprising:

a phase detector, the inputs of which are provided by an input signal of the loop and a signal proportional to the output signal, and the output signal of which is a signal proportional to the phase difference of the input signals, voltage controlled oscillator, loop filter coupled to the phase detector the voltage obtained from which is a control voltage of the voltage controlled oscillator and the bandwidth of which is changed by means of a control signal of the loop filter, characterised by further comprising:

a monitoring circuit for locking, coupled operationally to the output of the phase detector, comprising means for comparing the pulse of the output signal of the phase detector with the reference window, and means for forming a second control signal for switching the loop filter to a narrow bandwidth when said pulse fits the reference window, and for forming a first control signal for switching the loop filter to a broad bandwidth when said pulse is at least partly outside the reference window.
2. A phase locked loop as claimed in claim 1, characterised in that the means for comparing the pulse of the output signal of the phase detector with the reference window comprises:

a first reference means, which compares the output signal of the phase detector with a first reference value, a second reference means, which compares the output signal of the phase detector with a second reference value, and 13 a logical element coupled to the output of the reference means to give a first logical signal when the output signal of the phase detector is between the first and the second reference value, and in other cases a second logical signal.
3. A phase locked loop as claimed in claim 2, characterised in that the first reference means is a first analog operation amplifier coupled as a comparator the reference value of which is the first voltage, and the second reference means is a second analog operation amplifier coupled as a comparator the reference value of which is the second voltage.
4. A phase locked loop as claimed in claim 2, characterised in that the first reference means is a first digital n counter, to the reset input of which the output signal of the phase detector is transmitted, and the second reference means is a second digital n counter to the reset input of which the inverted output signal of the phase detector is applied, and that both the first and the second reference value are used as the value n to which the counter counts the clock pulses applied to them and if either of the counters reaches the count of n, the logical element will give the first logical signal.
5. A phase locked loop as claimed in claim 2, characterised in that the logical element is an UNCONDITIONAL OR gate,
6. A phase locked loop as claimed in claim 1 or 2, characterised in that the means for forming the first and the second control signal of the loop filter comprise a delay means coupled to the ourput of the logical element, the state of the output changing to the state of the input at regular intervals.

14 -
7. A phase locked loop as claimed in claim 1, characterised in that resistance value of at least one resistive part of the loop filter and the capacitance value of at least one capacitive part are chosen by means of switches controlled by the control voltage.
8. A phase locked loop as claimed in claim 7, characterised in that the resistance value is chosen by coupling one of the two resistors to be a resistive part by means of a first switch, and the capacitance value is chosen by coupling, by means of a second switch, a second capacitor to parallel with the first capacitor that is a permanent part of the filter, or by decoupling the second capacitor from the first capacitor.
9. A phase locked loop as claimed in claim 8, characterised in that when the capacitor is decoupled from the capacitive part, it is charged to the voltage of the first capacitor via a buffer amplifier and the second switch.
10. A phase locked loop as claimed in claim 7, characterised in that said resistive part and said capacitive part are in a feedback path of an active filter.
11. A phase locked loop, substantially as hereinbefore described with reference to the accompanying drawings.