FI97093C - Quick-setting phase lock - Google Patents

Description

97093

This invention relates to a phase-locked circuit in which the cut-off frequency or time constant of a loop filter can be changed.

In its basic form, a typical phase locked loop (PLL) circuit includes a voltage controlled oscillator, a phase comparator and a low pass filter. A reference signal is applied to the first input of the phase comparator and the output signal of the oscillator, which is also the output signal of the circuit, is fed back to the second input.

The phase comparator detects the phase difference between the input signals and outputs an output signal proportional to the phase difference, which is applied to a sub-pass filter acting as a loop filter. Its output voltage is in turn the control voltage of a voltage-controlled oscillator. When the loop is balanced, the phase of the output frequency signal is locked to the phase of the reference frequency signal. Many applications, such as frequency synthesizers, have a loop divider in the feedback branch, the division number of which can be changed programmatically. In this case, the frequency of the output signal is divided before being applied to the phase comparator, whereby frequencies significantly higher than the reference frequency but locked to it can be formed.

The phase lock must be such that, first, it maintains its equilibrium state and that the output signal is not modulated despite the rapid variation such as phase noise contained in either input signal and that the settling time when changing the output frequency is as short as possible. The loop filter is thus subject to high requirements which are, moreover, contradictory. When the loop is locked, the cut-off frequency of the filter must be low so that the noise of the input signal does not appear as modulation at the output. However, the narrowband of the filter is 2 97093 a disadvantage during the change mode when locking to a new frequency, e.g. when changing the divider of the divider. In order to keep the settling time in the change mode short, it is known to arrange the loop filter to be large in one way or another during the change mode. Two parallel loop filters can be used, of which the controllable toggle switch switches the wideband filter to the loop filter during the transition mode and the narrowband filter as soon as the loop equilibrium is reached. The filter can also be completely bypassed during the change mode. An arrangement can also be made to reduce the resistance of the filter, usually an RC low-pass filter, using switchable resistors for the duration of the changeover state. It is also known to use charge pumps to speed up the charging or discharging of the filter condensate.

In U.S. Patent No. 5,272,452, the filter consists of two parallel filters, the first comprising successive RC members and the second only one RC member having a capacitor common to the capacitor of the last 20 RC members of the first branch. The switch selects either filter as the loop filter. JP patent applications 61-60670 and 1-332362 disclose some solutions in which the value of the resistance of the loop filter is changed. In the former, the first resistor of the active filter is switched by a switch, while in the latter, one resistor of the passive filter is bypassed by a transistor switch. The disadvantage of this type of solution, which changes only one parameter, is that a sufficiently high locking acceleration is not achieved when the phase lock is very narrowband. In addition, the switching transistor in the saturation state causes noise in the control voltage of the VC0 as well as the switching trans- tents.

One solution using charge pumps is disclosed in U.S. Patent 4,546,330. A low pass filter comprises a capacitor and a plurality of resistors connected in series.

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In addition, as many pump circuits as there are said resistors are connected to the filtered one. By selecting one of the pump circuits at a time, the cut-off frequency of the filter can be made step-by-step. The principle is shown in Figure 1. The filter has two similar pump circuits P1 and P2. The pump circuit comprises JA and JAEI gates, diodes D1 and D2 and resistors R1 and R2 as shown in the figure. The input signals are the signals Up and Down from the phase comparator and the signal FAST, which is applied in-10 compared to the pump circuit P1. Here, the phase comparator is one that outputs the signal Up or Down depending on whether the pulse of the reference signal occurs before or after the feedback output signal. The FAST signal is high when the filter is desired to be wideband. The filter 15 actually comprises the resistors of the pump circuits as well as the resistors R5, R6 and the capacitor C. The operation is briefly as follows: it is assumed that FAST is high (the filter is wideband) and likewise Up is high. It is easy to see that the state of the gates is such that the pump circuit P1 is in an inoperative state and does not affect the connection. The pump circuit P2 is active and the resistance part of the filter is formed by the pump circuit P2 depending on the state of the signals of the resistor R3 or R4 and the series connection of the resistor R6. Correspondingly, when the signal FAST is low, the pump circuit • P1 becomes active and P2 is in an inoperative state. The resistance part of the filter now consists of the resistor R3 or R4 of the pump circuit P1, depending on the state of the Up and Down signals and the series connection of the resistors R5 and R6. The disadvantage, however, is the rather complicated implementation.

-. 30 Solutions in which the filter is completely bypassed during the rest of the processing mode are described in DE-A-2951283 and JP-Application 2-265865. In the former, the resistance of the simple RC filter is bypassed in the change mode by the transistor switch, while in the latter, the filter or part of it 35 is bypassed by the switch. Bypassing the filter during change mode 4 97093 means that the phase lock changes in degree from first degree to phase lock. This is detrimental because the phase noise from the phase comparator reaches the control voltage of the VCO directly. This is due to the fact that when the loop filter is converted to a narrowband again, the output frequency of the lock can be much lateral to the correct frequency, whereby the total locking time can even be extended.

The present invention provides a fast-acting phase lock without external control which does not have the above-mentioned disadvantages despite changing the characteristics of the loop filter. The phase lock is characterized by what is stated in claim 1.

In the phase lock of the invention, the length of the pulse of the signal received from the phase detector is monitored in the monitoring circuit. If it exceeds or falls below the set value, the monitoring circuit interprets the phase lock to be in the unlocked state, i.e. the output frequency is not yet locked to the frequency of the input signal and the first logic 20 signal corresponding to the information. The monitoring circuit forms, as it were, a window and examines whether the output of the phase lock in the window, i.e. the lock is locked. When the value is between the setpoints, i.e. the output is in the window, interprets the monitoring circuit as the phase lock is locked and gives a corresponding second logic signal. The logic signals are delayed in a delay element of a certain delay time, the output of which is a filter control signal. The delay element must be reset, i.e. such that after a certain time it examines the state of the input signal and keeps the state of the output unchanged if the input signal has not changed after this time. Thus, changes in the input signal during the delay time do not affect the state of the output. This delay element can thus in practice be a monostable multivibrator or a resettable counter chain.

Assume that the input is the first logical sig-35 signal (= no interlock). The filter control signal from the delay element then holds the filter wideband. After the delay time, it is examined whether the input signal of the delay element has changed. If it has not changed, the control signal is still unchanged. But if the input signal 5 has changed to another signal i.e., the length of the output pulse of the phase detector has entered the window of the monitoring circuit, the filter control signal changes and the filter becomes narrowband. The delay is an important part of the interlock monitoring circuit, as the hysteresis it causes prevents the filter 10 from changing its state too sensitively, so that the narrowband switching only takes place when it is certain that the interlock has taken place.

The filter is further characterized in that when its bandwidth is changed, the capacitance value also changes. 15 Changing the value of the capacitor makes it possible that the difference between the wide and narrow band of the filter can be very large, whereby a very narrow band phase lock can be realized in practice. Furthermore, the capacitor arrangement is such that no switching transient is generated when switching to narrowband 20. Second, the connection includes at least two switches. The use of two switches makes it possible to optimize both attenuation and bandwidth independently.

The invention will be described in more detail with the aid of the accompanying schematic figures, in which Figure 1 shows a known connection of a phase lock loop filter, Figure 2 shows the phase lock principle of the invention, Figure 3 shows the principle connection of a phase lock loop filter according to the invention and Figure 4

Figure 2 shows the phase lock of the invention in a block diagram. The pulses from the phase detector 21 to the loop filter 22 35 are monitored in the interlock monitoring circuit 6 97093 23. It follows whether or not the length of the pulse matches the set window. If the pulse length is greater than or less than the set value, the circuit 23 controls the loop filter to be wideband and keeps it as such until the lu-5 change occurs. When the interlock monitoring circuit detects that an interlock has occurred, it provides a control signal to the filter, causing the filter to become narrowband.

The principle circuit according to Figure 3 shows an analog phase lock filter. At the input of the filter In 10, the signal Pha from the XOR-type phase comparator acts. A phase comparator of said type outputs a pulse when the pulses of the input signal of the phase locked loop and the output signal are in a different state. The output voltage Out of the filter is the volume of the voltage-controlled oscillator VCO controllers-15. The interlock monitoring circuit comprises comparators OPI and OP2, the outputs of which are connected as inputs to the OR gate. The second input of each comparator is affected by the constant voltage obtained from the voltage divider R1, R2, R3, i.e. the constant voltage VI at the input of the comparator OPI and the constant voltage V2 at the input of the comparator 20 OP2. The second input of the comparators is affected by the voltage Vc of the filter capacitor C1. Since the voltage Vc depends on the length of the pulse coming from the phase comparator, this voltage can be compared with the voltages V1 and V2. When the capacitor voltage Vc exceeds the upper setting voltage VI, the output of the comparator OPI changes its state to a logic "1", and when the capacitor voltage falls below the lower setting voltage, the output of the comparator 0P2 changes its state to a logic "1". This is the first logical signal. With a capacitor-30 rin voltage between the setting voltages, the output of both comparators is logical “0.” This is another logical signal. This means that if the input signal Pha is longer or shorter than set, a first logic signal is obtained from the OR gate, such as a positive pulse indicating that the phase lock is not locked to the incoming frequency and a second logic signal is obtained after locking.

The logic signal is the input of a resettable delay element 21, which always examines after a certain time, which is the state of the input. If the input is the first logic signal, i.e. positive, then the delay element sets its output, which is the filter control signal Cntrl, to "0". In this mode, the control signal is called the first control signal and it keeps the filter wideband. Again, after a certain period of time, the delay body examines the state of its input. If it is still the first logic signal, Cntrl remains in the "0" state, but if the input has changed to the second logic signal, which means that the phase lock is locked, the filter control signal Cntrl ti-15 changes to "1". In this mode, the control signal is called the second control signal. A suitable delay time is, for example, 2 s, in which case the oscillation between the locked and unlocked state is not shown in the control signal.

The control signal Cntrl controls the switches S1 and S2 so that when the signal is in the state "0", which means that the lock is not locked as described above, the switches are in the up position and respectively when the control signal Cntrl is in the state "1" (lock is locked) Depending on the position of the switches, the filter is either narrowband or wideband.The narrowband filter consists of components R4, R5, Cl, R7, C3, C2 and 0P4.The wideband filter comprises components R4, Cl, R5, R6, C2 and 0P4.

Suppose now that the phase lock is about to settle. 30 to a new frequency, e.g. the division number of the loop divider has been changed. In this case, the interlock monitoring circuit detects that the voltage Vc is not in the window VI ... V2. The output of the OR member is high and the output signal Cntr1 of the delay member is low, with the switches S1 and S2 in their upper position, whereby the loop filter is wideband and comprises a amplifier OP4 connected in series with the RC link (integrator) R4, C1. whose feedback branch consists of a resistor R6 and a capacitor C2 and a resistor R5 connecting the integrators. Since the switch S2 5 is in the up position, the operation of the filter is not affected in any way by the large capacitor C3, but its voltage follows the voltage of the capacitor C2 because the voltage of C2 acts as an input to the amplifier OP3 connected as a buffer. The output voltage of the buffer follows the input voltage but 10 are separated from it.

When the interlock monitoring circuit has detected that the interlock has taken place, the monitoring circuit gives a second control signal, i.e. the control signal Cntrl rises, whereby the switches S1 and S2 turn to their lower position. In this case, the filter connection 15 comprises an RC link (integrator) R4, C1, an amplifier OP4 connected as an integrator, the feedback branch of which consists of a resistor R7 and capacitors C2 and C3 connected in parallel and a resistor R5 connecting the integrators. The difference with the narrowband state 20 is thus, firstly, that the resistance value of the feedback branch has changed and, secondly, that the capacitor C3 is connected via the switch S2 in parallel with the capacitor C2. Since the capacitor C3 in the wideband mode is charged to the voltage value of C2, when the filter 25 becomes narrowband, no additional transient is generated after the loop is locked.

In this connection, the RC feedback branch of the operational amplifier OP4, which also determines the zero time constant of the filter, is either R6, C2 or R7, C2 11 30 C3, depending on the mode. Thus, by changing the value of both the resistor and the capacitor, both the loop bandwidth and the value of the attenuation factor can be changed, and thus the locking speed can be optimized. This is why switches are necessary. For example, if the switch S1 were not and there was only one resistor 35 or the resistors R6 and R7 were the same size, the attenuation coefficient of the filter would be so small in a wide band that no locking would occur at all. Instead, the ratio of R6 to R7 is now chosen to be about a decade, with the switch S1 selecting a lower resistor R6, with which the locking takes place rapidly. Similarly, switch S2 sets the capacitance to a small value (C2), which also speeds up the locking. As a narrowband, on the other hand, a higher resistance R7 and a large capacitance are selected as the resistance value, i.e. the parallel connection of C2 and C3, where C3 is already 10 times pre-allocated to the value of C2 to prevent transient.

In contrast to prior art filters, the value of the capacitor also changes according to the lock condition. Therefore, the difference between wide and narrow band can be large and a very narrow band phase lock can be realized in practice. The winter width of the Kais-15 when the loop is locked can be e.g. 0.7 Hz and during locking 10 Hz.

The interlock monitoring circuit according to the invention can be implemented both digitally and analogously. If the application environment is digital, including e.g. program-compliant logic circuits, a digital interlock monitoring circuit is preferred. In this case, the counters according to Figure 4 are used instead of comparators. In this example, the loop lock frequency is assumed to be 16 kHz. The counters are clocked with 512 kHz clock pulses. If either of the 25 counters reaches the number nine, the digitally implemented delay circuit DELAY receives input "1", as a result of which the output is counted to state "0" for two seconds. After this time, it is considered whether the status of the input has changed.

The locking monitoring circuit as well as the filter 30 itself can be implemented in many different ways, as the appended claims do not place limitations on the practical implementation of the invention.

Claims (10)

A phase loop comprising: a phase comparator whose inputs have a loop input signal and a signal proportional to the loop output signal, and whose output signal is a signal proportional to the phase difference of the input signals; a voltage controlled oscillator; the phase comparator coupled loop filter, wherein the voltage obtained from the loop filter is the voltage controlled oscillator's control voltage and the bandwidth bandwidth is changed by the loop filter's control signal, characterized in that it further comprises: a control circuit for read, which control circuit coupled to the phase comparator output and comprising means for comparing the phase comparator output pulse with a reference window and means for generating a second control signal which narrows the loop filter, said pulse fitting in the reference window and for forming a first control signal, broadband, d & said puis is etm instone partially outside the reference window. Phase-read loop according to claim 1, characterized in that the means for comparing the phase of the phase comparator output with the reference window comprise a first comparator (OPI; 41) which compares the phase comparator output (Phase) with a first reference value (VI ), a second comparator (OP2, 42) comparing the phase comparator output (Phase) with a second reference value (V2) and a logic element (33; 43) coupled to the output of the comparators, which provides a first logic signal where the output of the phase comparator is between the first and second reference values and in other cases a second logical signal. 14 97093 A phase-read loop according to claim 2, characterized in that the first comparator means is a first analog operational amplifier (OPI) coupled to act as a comparator and whose reference value 5 is the first voltage (VI), and the second comparator. -the device is a second analog operation amplifier (OP2), which is coupled to act as a comparator and whose reference value is the second voltage (V2). 4. A phase-read loop according to claim 2, characterized in that the first comparator means is a first digital n counter (41), in which the zeroing input is fed a phase comparator's output (Phase), and the second comparator is a second digital n counter. (42), in which the reset input of a phase comparator output 15 (Phase) is inverted and both the first and second reference values are the value n, to which the calculator counts the clock pulses passed to them, and if neither of the counters when the value n, the logic means gives the first logical signal. Phase phase loop according to claim 2, characterized in that the logic means (33; 43) is an OR gate. A phase-locked loop according to claim 1 or 2, characterized in that the means for forming the first and second control signals of the loop filter comprise a delay means (34; 44) coupled to the output of the logic means and whose output state is transformed into an input state at constant intervals. . 7. Phase loop according to claim 1, characterized in that the resistance value of at least one resistive part of the loop filter and the capacitance value of at least one capacitive part are selected by switch (SI, S2), which is controlled by the control voltage (Cntrl). . 8. Phase-read loop according to claim 7, characterized in that the resistance value is selected by inserting it into the line. 97093 second of the two resistors (R6 or R7) are connected to a resistive part of the first switch (SI) and the capacitance value is selected by a first capacitor (C2) which continuously belongs to the filter or a second capacitor 5 (C3). ), which is detached from the filter, is connected in parallel with the second switch (S2). 9. Phase phase loop according to claim 8, characterized in that dk the second capacitor (C3) is loosely coupled from the capacitive part, it is charged to the voltage of the first capacitor (C2) via a buffer amplifier (OP3) and the second switch, (S2). A phase-read loop according to claim 7, characterized in that said resistive part and capacitive part are in the feedback filter of the active filter. m 4 4