AU649747B2 - A telecommunications data accessing device - Google Patents

Description

Regulation 3.2 AUSTRALIAAf Patents Act 195244 COMPLETE SPECIFICATION FOR A STANDARD PATENT

(ORIGINAL)

0O 6 0 as a a) 0 *0 as v ietoiafAf &RAt, Er'61-Or"&} uv'O lC Robert WYLIE, Marinus Johanes Joseph VALK, Howard FEGENT, and Barry Trevor DINGLE Actual Inventors: 0 0 Address for Service: DAVIES COLLISON CAVE, Patent Attorneys, 1 Little Collins Street, Meibc~re 3000, Victoria, AUSTRALIA Invention Title: A Telecommunications Data Accessing Device Details of Associated Provii ional Application No: PK3638/90 The following statement is a full description of this invention, including the best method of performing it known to us: 1- -2- A TELECOMMUNICATIONS DATA ACCESSING-DEVICE The preF-at invention relates to a data accessing device. The device is particularly, but not exclusively, useful for accessing timeslots or data channels of ISDN (Integrated Services Digital Network) Primary Rate transmissions.

Analog telephone exchanges are presently being replaced in most major industrialised countries by digital exchanges to form and expand domestic ISDNs.

S 15 Eventually exchanges will be developed to cater for broadband-ISDN traffic such as HDTV. Communications standards have been developed for data transmission between the digital exchanges and between the exchanges and customer terminals.

Both ISDN Primary Rate Access and Common Channel Signalling data, which include protocol, signalling and message information, is transmitted in frames of 32 encoded bytes or octets. The bytes each constitute a numbered slot, or data channel, of a respective frame. The rate of transmission is 2Mbit/s for most countries but in the U.S. most exchanges operate at a rate of 1.5Mbit/s. For 2Mbit/s transmissions, each timeslot provides a 64kbit/s data channel.

•00.0 25 With the expansion of the digital networks, there exists a pressing need to be able to provide equipment which enables network operators to monitor transmissions on links to ensure transmission protocols are being maintained and exchange equipment is not malfunctioning. This requires operators to be able to access data channels of interest. It would also be advantageous to be able to simulate transmission protocols and connect to links in order to monitor the performance of and communicate with exchange equipment and telecommunications terminals coupled to an exchange.

911 129,dbwspc.037,tlccm.aus,2 -3- Network protocol analysers are presently available which can perform the above functions. They are an on site unit which needs to be transportel and connected to links of an exchange to be monitored. Operations using an analyser are performed at the site of connection and to perform operations on another link of another exchange, the analyser needs to be disconnected and moved to the other exchange. The situation could be improved by providing analysers for all of the links of interest so only the users would need to move from site to site, however, the analysers are extremely expensive.

In accordance with the present invention there is provided a telecommunications data accessing device including: means for connecting the device to a digital link of a telecommunications network, said digital link transmitting telecommunications data in a plurality of data channels; means for accessing a predetermined data channel received on said link; and means for transmitting data on said channel to a remote analysis centre; said device being able to access and transmit said data without affecting a telecommunications terminal connected to said link.

S 20 Preferably said device includes means for receiving data from said remote centre and means for placing the received data on said link for transmission.

Preferably said connecting means is adapted to connect said device to a plurality of links of said network, and said accessing, placing, receiving and 25 transmitting means are adapted to operate on said links simultaneously, said device including multiplexing means for multiplexing and demultiplexing data received by said device from said links and said remote centre.

Preferably said links are 2Mbit/s links and said predetermiAed data channel is o: 30 a 64kbit/s channel.

940324,p:opcr\dbw,88281.91,3 -4- The present invention further provides a telecommunications link access system comprising: at least one telecommunications data accessing device as claimed in any one of the preceding claims; and said remote centre including: at least one complementary telecommunications data receiving device connected to said accessing device by a remote link, and which unpacks data received from said accessing device.

Preferred embodiments of the present invention are hereinafter described, by way of example only, with reference to the accompanying drawings, wherein: Figure 1 is a block diagram of a preferred embodiment of a telecommunications data accessing device according to the present invention; Figure 2 is a schematic diagram illustrating signals used in a ST-Bus system; 15 Figure 3 is a diagram illustrating data flow within the device of Figure 1; SFigure 4 is a block diagram of a MAS card of the device in monitor mode; S. Figure 5 is a block diagram of a MAS card of the device in simulate mode; Figure 6 is a block diagram of a hybrid chip of the device; Figure 7 is a block diagram of a switch chip of the device; Figure 8 is a circuit diagram of a MAS card of the device; Figure 9 is a block diagram of a CCE card of the device; .0 Figure 10 is a circuit diagram of the CCE card; Figure 11 is a block diagram of a TLC card of the device; Figure 12 is a block diagram of a phase locked-loop chip of the TLC card; S 25 Figure 13 is a circuit diagram of the TLC card; Figure 14 is a flow diagram of an operating routine of the TLC card; Figure 15 is a circuit diagram of a NIM card of another embodiment of the device; Figure 16 is a block diagram illustrating connection of the device to an analysis centre; Figure 17 is a block diagi im of a DEA card of another embodiment of the device; and 911129,dbwspe.037,tdcco.aus,4 Figure 18 is a circuit diagram of the DEA card.

A Timeslot Exchanger and Monitor (TEM) 2, as shown in Figure 1, includes five monitor and simulate (MAS) cards 4, a channel compressor and expander (CCE) card 6 and a TEM logic controller (TLC) card 8. The MAS cards 4 are each adapted for connection to a 2Mbit/s telecommunications link 10, which includes a transmit stream 12 and a receive stream 14. The streams 12 and 14 are transmitted on respective telecommunications lines. For each link 10 which can be connected to the TEM 2, the TEM 2 includes a transmit exchange port 16, a receive exchange port 18, a transmit line port 20 and a receive line port 22. The number of links 10 to which the TEM 2 can be connected depends on the number of MAS cards 4 included in the TEM 2. The MAS cards 4 may also be substituted by an alternative Non-Intrusive Monitor (NIM) card described hereinafter. The TEM 2 illustrated in Figure 1 can be connected to five 2Mbit/s links 10. The TEM 2 can also be connected to other types of links, such as 1.5Mbit/s links, by making appropriate alterations to the configuration of the internal circuitry of the TEM 2.

The MAS cards 4 are able to operate in one of two modes, a monitor mode, as illustrated for card 4a or a simulate mode as illustrated for card 4e. In monitor mode, the MAS card 4a accesses a predetermined timeslot of each frame received on the transmit and receive streams, without interrupting the streams 12 and 14 and outputs the timeslots to the CCE card 6. In simulate mode, the MAS card 4e interrupts the link 10 but communicates with the equipment connected on the exchange or line side of the link 10 if the link 10 had not been interrupted.

Predetermined timeslots in each frame received from the exchange or line side are sent to the CCE card 6 and, in return, timeslots are provided from the CCE card 6 for transmission to the exchange or line equipment. The MAS card 4e is illustrated communicating with the equipment on the exchange side of the TEM 2.

The CCE card 6 is connected to all the MAS cards 4 and a remote 2Mbit/s link 24 via remote link transmit and receive ports 26 and 28 of the TEM 2. The CCE card 6 essentially acts as a multiplexer/demultiplexer which copies timeslots received from 911129,dbwspc037,1clecom.aus4 -6the cards 4 into available data transmission timeslots for transmission on the link 24 to a remote analysis centre. The remote analysis centre also provides timeslots on the link 24 for separation by the CCE card 6 and output to MAS cards in simulate mode.

The remote analysis centre includes at least one network protocol analyser which is able to analyse the information accessed by the TEM 2 and provide appropriate information to enable the TEM 2 to simulate terminal or exchange equipment.

The TLC card 8 provides control signals to the MAS cards 4 and the CCE card 6 and is able to reconfigure the cards 4 and 6 as desired. The TLC card 8 operates in response to commands received from the remote analysis centre by a control link 30. The TLC 8 communicates with the processing equipment of the remote analysis centre via an RS232 serial port 32 of the TEM 2 which is connected to a modem (not shown). The modem is, in turn, connected to the control link 30, which is a standard telecommunications link.

S. A number of TEMs 2 may be installed at a digital exchange and conrnected to *the outgoing links 10 of the exchange, as illustrated in Figure 1. The TEMs 2 can remain connected to the digital exchanges and will not affect terminal equipment connected to the exchanges, unless the remote centre wishes to interrupt a link.

Equipment at the remote analysis centre can monitor and simulate protocols on links connected to the TEMs 2, as desired, without personnel having to be transported between exchanges and without connections having to be made or altered at the exchanges.

25 The communications standard which is employed for exchange links using SISDN Primary Rate Access or Common Channel Signalling is G703 or G704 which has been established by the telecommunications standards body CCITT. The 2Mbit/s version of the G703 and G704 standards is known as CEPT and the 1.5Mbi'/s version of the standard is known as T1. The TEM 2 described hereinafter has been developed for CEPT links but can be easily adapted for T1 links.

The cards 4, 6 and 8 of the TEM 2 include semiconductor chips manufactured 911 VA9,dbwspc.037,tc1ccOm.aus,6 -7by the Mitel Corporation and which communicate with one other using an ST-Bus (Trade Mark) system. The system, as shown in Figure 2, involves the use of a three wire bus, one for frame signals 34, one for a 2.048 MHz clock signal 36 and one for data 38. The data 38 is transmitted as a frame of 32 bytes every 125ps, i.e. at a rate of 8kHz. The bytes form 64Kbit/s channels or 32 timeslots 40. The channels 40 each include 8 bits which represent an encoded signal, the most significant bit being received first and the less significant bit being received last.

Data is transmitted on CEPT links in exactly the same manner as that for the format described above for the ST-Bus except the order of the bits in each channel is reversed, the least significant bit being received first and the most significant bit being received last. In CEPT frames on an ISDN access, timeslot zero is principally reserved for framing information and timeslot 16 is reserved for signalling. The remaining timeslots or channels are available for user information transmission by S**a 15 terminal equipment. For this reason, timeslot zero and timeslot 16 are not normally S* referred to as channels but in this specification the term channel is used as an equivalent to the term timeslot. The term data is used in the present specification as encompassing all forms of transmissible telecommunications data, such as protocol, signalling, error checking and message data.

The TEM 2 may be configured, as illustrated in Figure 3, so the first four MAS cards 4a, 4b, 4c and 4d operate in monitor mode to access and provide to the CCE 6 timeslot 16 of frames in the transmit and receive streams 12 and 14 connected thereto. The cards 4a to 4d use timeslot 1 and timeslot 17 of ST-Bus frames to ,tooo%* transmit the data received on timeslot 16 of the transmit and receive streams 12 and 14, respectively, to the CCE 6. The signalling information accessed is labelled A for the transmit stream 12 and B for the receive stream 14 of the MAS card 4a in Figure 3. Similarly the signalling information accessed for cards 4b, 4c and 4d is respectively labelled C, D, E, F, G and H. The card 4e which is in simulate mode accesses the signalling information labelled I from the transmit stream 12 only. The CCE card 6 packs the information received from the cards 4 into one CEPT frame 42 which is outputted on the remote link 24. The transmit stream signalling information 911129,dbwspe.037jccm.mJaus,7 -8received is placed in timeslots 1 to 5 and the receive stream signalling information received is placed in timeslots 17 to 20, as shown in Figure 3. Signalling information is received on the link 24 in a timeslot labelled J for unpacking by the CCE card 6 and transmission to the fifth MAS card 4e.

A MAS card 4, as shown in Figures 4 and 5, includes two similar hybrid circuits 44 and 46 and a switch circuit 48. A first hybrid circuit 44 is provided for the transmit stream 12 and a second hybrid circuit 46 is provided for the receive stream 14 of a link 10. The first hybrid circuit 44 includes an exchange transmit input 50, which is coupled to the port 16 and a line transmit output 52 which is coupled to the port 20 of the TEM 2. Similarly, the second hybrid circuit 46 includes a line receive input 54 which is coupled to the port 22 and an exchange receive output 56 which is coupled to the port 18 of the TEM 2. The hybrid circuits 44 and 46 are based on a Mitel MH89790 hybrid. The circuits 44 and 46 convert the frames received on the inputs 50 and 54 from the CEPT format to the ST-Bus format and output the frames to the switch circuit 48. In the monitor mode, as illustrated in Figure 4, the circuits 44 and 46 are placed in an "analog loopback" mode so the frames received on the inputs 50 and 54 are passed effectively without alteration to the -outputs 52 and 56. This series connection of the hybrid circuits 44 and 46 to a link 10 enables the link to be monitored in a substantially non-intrusive manner. The intrusion required is minimised by use of the circuits 44 and 46.

S

In the simulate mode, as shown in Figure 5, the link 10 is interrupted and only the frames received on one of the inputs 50 and 54 is of interest. To simulate an 25 exchange connected to a terminal via the link 1C Jata from the exchange transmit •O input 50 is converted and sent by the first hybrid circuit 44 to the switch circuit 48.

Data is also provided by the switch circuit 48 for conversion to the CEPT format and transmission on the exchange receive output 56 by the second hybrid circuit 46.

The switch circuit 48 has a first hybrid input 58 and output 60 and a second hybrid input 62 and output 64. The switch circuit 48 also includes a TEM databus output 66 and input 68. The switch circuit 48 is based on a Mitel MT8980 digital 911129,dbwspc.37,jceomus,,8 -9crosspoint switch which can perform a number of switching functions as determined by connection information stored therein. In monitor mode, as shown in Figure 4, the switch circuit 48 extracts timeslots of interest from the frames received on the inputs 58 and 62 and places them in a single frame for transmission on the output 66. In simulate mode, as shown in Figure 5, the switch circuit 48 copies a timeslot of interest from frames received on the first hybrid input 58, sends the slots in ST-Bus frames to the TEM databus and places the timeslots received from the bus in the correct slot of a frame for output on the second hybrid output 64 and eventual transmission on the exchange receive output 56.

A Mitel MH98790 hybrid 70, as shown in Figure 6, includes a CEPT link input 72 and output 74 for receiving and sending line signals via appropriate line transformers. The frames received on the input 72 pass via a bipolar line receiver 76 to a CEPT link interface 78 of the hybrid 70. The interface 78 detects an incoming frame and attempts to achieve frame alignment by examining timeslot zero of the received frame to determine whether it includes a predetermined bit pattern indicative of a CEPT frame alignment signal. The interface 78 then waits for 31 bytes to pass S* and examines the next byte to determine whether it includes a predetermined pattern O indicative of a CEPT non-frame alignment signal. Consecutive CEPT frames are distinguished by the alternating predetermined bit patterns provided by the frame and non-frame alinment signals included in timeslot zero. Once the interface 78 has determined reception of two CEPT frames the interface 78 then attempts to verify proper frame alignment by examining the next four frames received. On obtaining frame alignment, alignment status flags are set in internal registers of the interface 78.

25 The frame synchronisation information is passed to an ST-Bus control interface of the hybrid 70 which is able to place appropriate data signals on an ST-Bus 82.

.The hybrid 70 includes a clock extractor 81 which is able to extract, from received frames, and output an 8kHz clock signal on a clock output 84 which can be used for synchronisation of the cards 4, 6 and 8 and the ST-Bus 82, as described hereinafter.

CEPT frames received by the link interface 78 are converted to the ST-Bus format, placed in a two frame elastic buffer 86 and outputted on the bus 82 by an ST-Bus data interface 88 of the hybrid 70. The buffer 86 allows for differences in phase 911129,dbwspeM7jelccom.aus,9 10 between the data of the received CEPT frames and the ST-Bus clock 36.

The hybrid 70 essentially performs the reverse process for frames to be sent from the ST-Bus 82 out onto a link from the link output 74. The CEPT interface 78 inserts the appropriate CEPT frame and non-frame alignment signals in the first byte of each frame. A CRC-4 error checking bit sequence is also incorporated in the first byte of the frames. Once the interface 78 has converted the ST-Bus frames to the CEPT format, the frames are placed on the output 74 by a bipolar line transmitter A Mitel MT8980 crosspoint switch chip 92, as shown in Figure 7, includes an input serial to parallel converter 94 which is able to receive up to eight ST-Bus framed data streams on respective ST-Bus data lines 83. The received streams are converted to a parallel format and stored in a data memory 96. The chip 92 further includes a connection memory 98, an output multiplexer 100 and an output parallel 15 to serial converter 102 which is able to output up to eight ST-Bus framed data pa streams on respective ST-Bus data lines 83. The chip 92 includes a microprocessor control interface 104 for accessing the units of the chip 92 and adjusting the

*S

configuration of the chip 92. An ST-Bus timing circuit 106 is also provided. The **switch chip 92 is able to rearrange and extract timeslots of received frames in the output multiplexer 100, as desired, based on information stored in the connection memory 98 and output the adjusted frames via the output converter 102. The state of t.o* the connection memory 98 can be adjusted by information entering via a microprocessor control interface 104. In a relatively simple mode, the connection memory 98 provides a map of the timeslot order in each of the eight streams to be outputted by the output converter 102. The memory 98 contains pointers to an input stream and the timeslot number which should be output at a given time in an output stream. In an alternative mode, a timeslot contained in a memory location of the data memory 96 is selected by the output multiplexer 100 and sent directly to an outgoing stream at a predetermined time. Control signals for the output multiplexer 100 are stored in the connection memory 98. The switch chip 92 enables switching, extraction and rearrangement of data channels of received frames according to the connection information stored in the connection memory 98.

911129,dbwspc.37,tdcomrnus,10 11 The first hybrid circuit 44, as shown in Figure 8, includes a hybrid chip 70 and line transformer circuits 108 and 110 for the exchange transmit input 50 and the line transmit output 52, respectively, to enable connection to the link input 72 and the output 74 of the chip 70. The first hybrid circuit 44 has an ST-Bus data stream output 112 which is connected to the first hybrid input 58 of the switch circuit 48 and a ST-Bus data stream input 114 which is connected to the first hybrid output 60 of the switch circuit 48. The 8kHz clock signal extracted by the chip 70 of the first hybrid circuit 44 is provided on a clock output 116. An LED 118 of the first circuit 44 is illuminated by a control output when the first circuit 44 achieves frame alignment of incoming CEPT streams. Similarly, the second hybrid circuit 46 includes a hybrid 70 having line transformer circuits 120 and 122 connected respectively to its link input 72 and its link output 74 to enable connection to the line receive input 54 and the exchange receive output 56. An ST-Bus output 124 is connected to the receive hybrid input 62 of the switch circuit 48 and an ST-Bus data stream input 126 is connected to a receive hybrid output 64 of the switch circuit 48. The extracted 8kHz clock signal is provided on a clock output 128 and lines 116 and 128 are inputted to a NAND gate which provides a MAS card extracted clock output 130. An LED 132 of the second hybrid circuit 46 is illuminated by a control output of the hybrid 70 when frame alignment is achieved for CEPT streams received on the line input 54. The CEPT link interfaces 78 of the hybrids 70 are controlled in response to the state of control inputs 134 received from the switch circuit 48. The inputs 134 enable the complete function of the hybrid circuits 44 and 46 to be controlled. The status of the CEPT link interfaces 78 of the hybrids 70 are placed on a status output 113 and are sent to status inputs 135 of the switch circuit 48.

The switch circuit 48 includes a crosspoint switch chip 92 which pro des the inputs 135 58 and 62 and the outputs 60 and 64 for the hybrid circuits 44 and 46.

4 0 The circuit 48 includes address lines 136 and data lines 138 for the microprocessor control interface 104 of the chip 92. The chip 92 also provides the TEM databus output 66 and the TEM databus inputs 68 for ST-Bus framed data streams.

The CCE card 6 of the TEM 2, as shown in Figure 9, includes a switch circuit 911 1Q,dbwspc.03 Iltc,"Mm~au, I 12- 140 based on the MT8980 crosspoint switch chip 92 and a remote link interface 142 based on the MH89790 hybrid 70. The switch circuit 40 has five ST-Bus stream inputs 144 which respectively receive the frames placed on the outputs 66 of the five MAS cards 4 via the TEM bus 146. The circuit 140 also has five ST-Bus stream outputs 148 which are able to provide frames to the switch inputs 68 of the five MAS cards 4, respectively. Timeslots of interest included in frames received simultaneously by the sw.:ch circuit 140 are multiplexed into single frames and placed on a transmit line 150 from the switch circuit 140 to the remote link interface 142. The interface 142 converts the ST-Bus stream received on the line 150 to the CEPT format and places the stream on the remote link 24 via a remote link output 152 of the interface 142. Data is received from the remote link 24 on a remote link input 154 of the interface 142 and the received frames are converted to the ST-Bus format and sent to the switch circuit 140 by a receive line 156 connected between the interface 142 and the switch circuit 140. The switch circuit effectively demultiplexes the frames o 15 received on the line 156 and places timeslots of the received frames on the outputs 148 in ST-Bus frames, according to t:e connection state of switch circuit 140 at the time of receipt of the frames.

The CEPT link interface 78 of the remote interface 142, in contrast to the interfaces 78 of the MAS cards 4, is permanently enabled to generate and check for correct CRC-4 error checking bit sequences in timeslot zero of the frames which it receives. It is also set into maintenance mode so as to apply rmore severe tests on frames before correct synchronisation of the remitte link 24 Is reported as being achieved. The occurrence of CRC-4 errors is accumulated in an 8 bit register of the 25 interface 142 which is reset every second. This enables the error rate on the remote link 24 to be monitored. These features of the interface 142 provide stringent criteria for performance of the link 24 and enable rapid detection of any loss of link Stransmission quaL:l.

d The link interface 142, as shown in Figure 10, includes line transformer circuits 160 and 162 for respectively connecting the hybrid input and output 72 and 74 to the remote link input and output 154 and 152. An 8kHz clock output is 911129,dbwspe.037tdccom.aus,12 13 extrac'tcd from frames handled by the interface 142 and is provided on a clock outpu t 164. The interface 142 includes an LED 166 connected to a control output of the hybrid 70 which is illuminated when the CEPT interface 78 of the hybrid 70 achieves frame synchronisation. The CCE card 6, as is apparent from Figure 10, is configured in a similar manner to the MAS cards 4.

The TLC card 8, as shown in Figures 11, includes a Rockwell 65F12 microcontroller 170 and a 4kbyte EPROM 172 and a 2kbyte RAM 174 connected to the microcontroller 170 by address and data buses 176 and 178, respectively. The microcontroller 170 is connected to the TEM data bus 146 by a control bus 180, a second data bus 182 and a second address bus 184. The address bus 184 's also connected to a board select decoder 186 which provides chip select outputs 188 to the TEM bus 146. The microcontroller 170 functions in accordance with a main operating routine stored in the EPROM 172 to process commands received on the RS232 port 15 32 connected to the TEM databus 146. In response to the commands the microcontroller 170 is able to access the MAS and CCE cards 4 and 6 and reconfigure the switch chips 92 and hybrids 70, as desired. The microcontroller 170 is also able a* *4 to select which of the 8kHz outputs 130 and 164 of the cards 4 and 6 is to be used as a basis for synchronising the ST-Bus streams in the TEM 2. A watchdog and power on reset circuit 190 is provided to reset the microcontroller 170 when the TEM 2 is initially switched on, and when the main operating routine stored in the EPROM 172 ceases execution for a predetermined period of time.

The TLC card 8 also includes a Mitel MT8940 Dual Phase-Locked Loop chip 25 192 which provides the ST-Bus clock signal 36 on an output 194, according to CEPT "t format timing or on an output 196 according to T1 format timing. The chip 192 also provides the ST-Bus frame pulses 34 on an output 198. The ST-Bus clock and frame signals 36 and 34 are provided to all of the cards 4 and 6 and are synchronised to a selected 8kHz signal inputted to the chip 192 on a line 200 which forms the output of clock gate circuitry 202. The gate circuitry 202 is able to receive all of the extracted 8kHz outputs 130 and 164 from the cards 4 and 6 on inputs 204 from the TEM bus 146. The mode of operation of the chip 192 is controlled by a mode adjust 911129,dbwspcO37,tekewm~aus,13 14circuit 206.

The phase-locked loop chip 192, as shown in Figure 12, includes two phase-locked loops 208 and 210 which both receive the 8kHz input on the line 200.

The first phase-locked loop 208 produces a 1.543 MHz clock output in accordance with the T1 format based on a 12.355 Mhz clock input 212. The second phase-locked loop 210 produces a 2.048 MHz output in accordance with the CEPT format based on a 16.388 MHz input 214. Both of the outputs are synchronised or locked to the 8kHz input provided on the line 200. One of the outputs is selected by a loop selection circuit 212 and is provided to one of the clock outputs 194 or 196 and a frame counter circuit 214, which produces the frame pulse for the frame output 198. The mode of operation of the chip is controlled by a control circuit 216 in response to control inputs 218.

o: 15 The EPROM 172 and the RAM 174, as illustrated in Figure 13, are selected by two 1 out of 4 decoders 220 responsive to the two most significant bits of the address bus 176. An 8bit latch 222 is provided to latch the least significant 8 bits of the address bus 176 outputted by the microcontroller 170 so as to separate the address and data buses 176 and 178 as the microcontroller 170 outputs the least significant data and address signals on the same lines. The RAM 174 is provided to meet the dynamic program requirements of the main operating routine stored in the EPROM 172.

0 The board select decoder 186 provides chip select signals on the outputs 188 25 to the switch chips 92 of the MAS and CCE cards 4 and 6 in response to signals from the controller 170. The controller 170 can then access the switch chips 92 using the second address and data buses 182 and 184 so as to adjust the connection memories 98 of the switch chips 92 as desired. The CEPT interfaces 78 of the hybrid chips of the cards 4 and 6 are controlled in response to instructions received from the respective switch chips 92 on each card 4 and 6. By not controlling the CEPT interfaces 78 directly by the microcontroller 170 provides a degree of protection against processor failure on the TLC card 8. If a failure occurs, the current control 911129,dbwsp.037,tkcomaus,14 15 settings of the CEPT interfaces 78 are maintained and the TEM 2 is able to continue to provide connections in accordance with the settings until power is removed.

The watchdog and power on reset circuit 190 includes two monostables 224 and 226. The first monostable 224 resets the controller 170 when power is supplied to the TEM 2 and the second monostable 226 monitors execution of the main operating routine and initiates a reset sequence if the routine ceases for a predetermined period of time. The monostable 226 also illuminates an LED 228 if the main operating routine is being correctly executed.

The TLC card 8 further includes an RS232 conversion circuit 230, which includes a transistor stage 232 and an operational amplifier stage 234. The transistor stage 232 is used to convert input signals received on the RS232 port 32 to the appropriate level for use by the controller 170. The amplifier stage 234 is used to 15 provide an output signal drive for the port 32, while the microcontroller 170 provides serialisation of the output data at the appropriate baud rate.

The gate circuit 202 of the TLC card 8, as shown in Figure 13, includes an OR Sgate 236 which is able to receive all of the 8kHz signals extracted by the MAS and CCE cards 4 and 6, only one of the signals being received as selected by the microcontroller 170. The gate circuit 202 then passes the output of the gate 236 to the phase locked-loop chip 192. Crystal circuits 238 and 240 provide the 12.355 MHz and 16.388 MHz input clock signals, respectively, for the chip 192. A retriggerable monostable circuit forms the mode adjust circuit 206 which in the 25 absence of an 8kHz signal being provided on the output of the OR gate 236 sends a control signal to the phase locked-loop chip 192 to place the chip 192 in a master mode. In master mode, the clock signal output on the line 194 or 196 is based on the 16.388 MHz clock input.

The operating routine 250 stored in the EPROM 172, as shown in Figure 14, begins at step 252 on resetting the microcontroller 170. All the default configurations for the MAS and CCE cards 4 and 6 are retrieved from the ROM 172 and copied to 91!129,dbwpeM7Itlcm.aus, 16 the RAM 174. At step 254 the configurations are set in the cards 4 and 6 and software connections made accordingly to the links 10 and 24. The routine 250 then enters the main operating routine 256 which is a continuous routine during which a series of flags are checked, together with frame synchronisation status of the MAS and CCE cards 4 and 6. At step 258 the status of a configuration flag is checked and if it has been set operation of the routine 256 proceeds to step 260 otherwise operation proceeds to step 262. The configuration of the cards 4 and 6 is adjusted at step 260 in accordance with new configuration information stored in the RAM 174. At step 262 the status of a synch flag is examined and if set operation proceeds to step 264 and if not set proceeds to step 266. The 8khz signal which is used to synchronise the internal timing of the TEM 2 is changed at step 264 so a new extracted 8 khz signal is provided to the OR gate 236. The status of a character flag is examined at step 266 and if it is set, operation proceeds to step 268 otherwise operation proceeds to step 270. The character flag is set by the microcontroller 170 whenever a valid ASCII 15 character is received by the RS232 interface circuit 230. The character is processed at step 268 and added to any other characters received to build up a word stream. At step 270 the status of a word flag is examined and if the flag has been set operation proceeds to step 272 otherwise operation proceeds to step 274. The word flag is set whenever a word stream has been built up that constitutes a valid command for the a00 microcontroller 170. The command is processed at step 272. The command may comprise instructions such as adjust the configuration information stored in the RAM 174 and then set the configuration flag or store information concerning a new 8kHz synchronisation source and set the synch flag.

o 25 The microcontroller at step 274 issues instructions to the cards 4 and 6 to examine status bits of the CEPT interfaces 78 to determine whether frame synchronisation is present and to illuminate or disable the synchronisation LEDs 118 or 166, accordingly. After step 274 the main operating routine 256 continues execution at step 258.

An alternative to the MAS card 4 is a Non-Intrusive Monitor (NIM) card 280, as shown in Figure 15. The NIM card 280 is similar to the MAS card 4 except it 911f1_9,dbwsp".O37cccoi.zus,16 17provides a means whereby the transmit and receive streams 12 and 14 of the link can be monitored by simply tapping into the link without having to insert circuitry of the card 280 in the link streams 12 and 14. The NIM card 280 uses high impedance tapping connectors which are presently provided at service access panels of exchanges.

Exchange transmit and line receive inputs 50 and 54 of the card 280 are respectively connected by cables to the tapping connectors of a link 10 to be monitored.

The circuitry of the NIM card 280 is the same as a MAS card 4 except the interface to the hybrids 70 of the first and second hybrid circuits 44 and 46 is different. The transformer circuits 108, 110, 120, and 122 are replaced by two identical amplifier circuits 282 for each hybrid 70. As the card 280 is a monitor card no exchange or line outputs are provided.

To overcome termination effects and cable matching problems which occur 15 with use of the exchange tapping connectors, the amplifier circuit 282 provides a 752 terminating impedance 284 for the inputs 50 and 54. The terminating impedance correctly matches the characteristic impedance of the cables normally used at the exchange service access panels. The tapping connectors represent a series impedance ranging from 1kQ to 2.2kQ and therefore the amplifier circuit 282 includes an input 0* amplifier 286 having a large gain-bandwidth product to overcome attenuation caused by the input series impedance. The amplifier 286 is an AD846 amplifier produced by Analog Devices. It enables the amplifier circuit 282 to recover 26 dB lost across the divider formed by the series impedance and the 752 input termination 284, The output of the input amplifier 286 is fed to two high speed comparators 288 and 290 25 of the amplifier circuit 282. The comparators 288 and 290 are configured to split the two phases of the Alternate Mark Inversion (AMI) line code pulses outputted by the input amplifier 286 so as to drive input pins 292 and 294, respectively, of the hybrid 70. For the IVfAS card 4, the pins 292 and 294 normally have pulses appearing on them from a transistor input stage via the secondaries of the transformer circuits 108 and 120 but as the transformer circuits are not included, the pins 292 and 294 can be driven directly by the comparators 288 and 290. The comparators 288 and 290 reproduce the level and polarity of pulses which would normally appear on the input 911129,dbwspec.37,tclwntaus,17 18pins of the hybrids 70 on the MAS card 4.

An analysis centre 300 which can receive the transmissions sent by a TEM 2 on the remote link 24, includes, as shown in Figure 16, a TEM-bar 302 connected to the link 24, a network protocol analyser 304 connected to the TEM-bar 302 and a PC control station 306. The TEM-bar 302 includes essentially the same circuitry as the TEM 2 and is the logical inversion of the TEM 2. The TEM-bar 302 is used to unpack or demultiplex frames received on the link 24 and submit the unpacked frames to the protocol analyser 304. A TEM-bar 302 is provided at the centre 300 for each TEM 2 placed in the network. The PC station 306 is used to issue control signals to the analyser 304 and the TEM-bar 302. The station 306 also issues control signals to the TEM 2 via the control link 30 and complimentary modems 308. The analyser 304 can, of course, be replaced with other equipment such as a model exchange to monitor accesses thereto by other exchanges, for example PABXs connected to the 15 TEM 2. In this configuration, the TEM 2 and the TEM-bar 302 are effectively used as concentrators and expanders, and slightly different operating software is employed.

0* 9' The TEM-bar 302 and the TEM 2 have the same circuitry, except the S* TEM-bar 302 includes Data Expansion and Analysis (DEA) cards 310, as shown in Figures 17 and 18, instead of MAS cards 4 or NIM cards 280. A DEA card 310 has the same circuitry as a MAS card 4 except the inputs 50 and 54 and outputs 52 and 56 of the hybrid circuits 44 and 46 are used and configured differently. Frames received from the TEM 2 which are accessed by MAS cards 4 in monitor mode and NIM cards 280 are demultiplexed by the switch circuit 48 of the DEA card 310 so the 25 time slots relating to the transmit stream 12 are outputted by the second hybrid circuit 46 on the output 56 and timeslots relating to the receive stream 14 are outputted by the first hybrid circuit 44 on the output 52. The output 56 is connected to an exchange monitor port 312 of the card 310 and the output 52 is connected to a line monitor port 314 of the card 310.

For frames received by the DEA card 310, which relate to frames accessed by MAS cards 4 in simulate mode, only one of the hybrid circuits 44 and 46 is required.

911129,dbwspc.037,telecom.aus,18 19 The switch circuit 48 of the card 310 sends the accessed timeslots to the second hybrid circuit 46 which are transmitted from the output 56 to a transmit simulate port 316 of the card 310. Frames to be sent back to the MAS card 4 in simulate mode are sent by a receive simulate port 318 of the card 310 to the input 54 of the second hybrid circuit 46 and passed to the switch circuit 48 for output to the TEM-bar bus 146. The input 50 of the first hybrid circuit 44 is not used so it is grounded whilst the output 56 of the second hybrid circuit 46 is connected to both of the exchange monitor and transmit simulate ports 312 and 316, as shown in Figures 17 and 18.

The ports 312 to 318 of the DEA card 310 are complimentary to input/output ports of the network analyser 304 and can be directly connected thereto.

Throughout this specification and the claims which follow, unless the context requires otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated integer or group of integers but not the exclusion of any other integer or group of integers.

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Claims (9)

1. A telecommunications data accessing device including: means for connecting the device to a digital link of a telecommunications network, said digital link transmitting telecommunications data in a plurality of data channels; means for accessing a predetermined data channel received on said link; and means for transmitting data on said channel to a remote analysis centre; said device being able to access and transmit said data without affecting a telecommunications terminal connected to said link.

2. A device as claimed in claim 1, including interface means which comprises said connecting means and accessing means, and is configurable to access said data channel on the transmit stream and receive stream of said link, whilst receiving and outputting said streams effectively without alteration.

3. A device as claimed in claim 2, wherein said connecting means includes input circuits which are impedance matched to tapping connectors used for connection to said link. 0* 20 4. A device as claimed in claim 2, including means for receiving data from said 0@ remote centre and means for placing the received data on said link for transmission. A device as claimed in claim 4, wherein said interface means comprises said placing means and is configurable to access said predetermined data channel on one of 25 the transmit and receive streams and place said received data on a selected data channel of the other stream so as to simulate a telecommunications terminal connected to said 0 link.

6. A device as claimed in claim 2, 3 or 5, wherein said interface means includes 30 respective hybrid circuits for said transmit and receive streams adapted to detect frames of a predetermined format on said streams, achieve frame alignment upon detection of said frames, and output frames of at least one stream to said accessing means. 94M24,vp-4cdb&w.Ns81.91.:YD

21- 7. A device as claimed in claim 6, wherein said accessing means includes a switch circuit for copying data of said predetermined data channel from frames received into an information channel of frames outputted to said transmitting means. 8. A device as claimed in claim 7, including a plurality of said interface means for accessing a plurality of respective links simultaneously, and wherein said transmitting means includes a multiplexing switch circuit for placing data of information channels received simultaneously from the swit.-.h circuits of said interface means into a transmit frame for transmission to said remote centre. 9. A device as claimed in claim 8, wherein said transmitting means includes a remote link interface for transmitting said transmit frame on a remote link to said remote centre. 15 10. A device as claimed in claim 5, wherein said interface means includes S respective hybrid circuits for said transmit and receive streams adapted to detect frames of a predetermined format on a least one of said streams, achieve frame alignment upon detection of said frames, and output said frames to said accessing means, and further being adapted to receive frames from said accessing means and place the received frames on one of said streams in said predetermined format. 11. A device as claimed in claim 10, wherein said accessing means includes a switch circuit for copying data of said predetermined data channel from frames received into an information channel of frames outputted to said transmitting means, 25 and for copying data from an information channel of frames received from said receiving means into a predetermined data channel of frames outputted to one of said hybrid circuits. S* 12. A device as claimed in claim 11, including a plurality of said interface means for accessing a plurality of respective lengths simultaneously, and including channel compressor/expander means which comprises said transmitting and receiving means and includes a multiplexing/demultiplexing switch circuit placing said information 911129,dbwsp,.O37,cccm.aus21 -22 channels received simultaneously from said interface means into a transmit frame for transmission to said remote centre and for simultaneously placing information channels of a frame received from said remote centre into respective frames for output to said interface means, respectively. 13. A device as claimed in claim 12, wherein said compressor/expander means includes a remote link interface for transmitting and receiving frames on a remote link to said remote centre, said remote link interface comprising a hybrid circuit which performs error checking on and frame alignment of frames received on said remote link. 14. A device as claimed in claim 9 or 13, further including a microcontroller circuit, responsive to command signals received from said remote centre, for selecting the channels pocessed by said switch circuits. 15. A device as claimed in claim 14, further including a synchronising circuit for selecting a clock signal extracted by one of sai'i hiterface means from frames received thereby, and for generating frame and clock signals for said device on the basis of the extracted signal, 16. A device as claimed in claim 13, further including a micro-controller circuit responsive to command signals received from said remote centre, for selecting the channels processed by said switch circuits, and for setting the hybrid circuits of the S interface means so as to operate in a monitor or simulate mode. 17. A device as claimed in claim 16, further including a synchronising circuit for selecting a clock signal extracted by one of said interface means from fiames received thereby, and for generating frame and clock signals for said device on the basis of the 0* extracted signal. 911129,dbwspe.037,telcm.aus.22 -23 18. A telecommunications link access system comprising: at least one telecommunications data accessing device as claimed in any one of the preceding claims; and said remote centre including: at least one complementary telecommunications data receiving device connected to said accessing device by a remote link, and which unpacks data received from said accessing device. 19. An access system as claimed in claim 18, wherein the unpacked data is analysed by a network protocol analyser connected to said receiving device. An access system as claimed in claim 18, wherein said receiving device is further adapted to pack data for transmission to said accessing device. 15 21. An access system as claimed in claim 20, wherein the data received and transmitted on said remote link is processed by a simulating circuit connected to said S' -i receiving device.

22. An access system as claimed in any one of claims 18 to 21, wherein said receiving device includes the same circuitry as said accessing device.

23. An access system as claimed in any of claims 18 to 22, wherein the accessing and receiving devices are configured in accordance with command signals issued by a computer station of the remote centre. 0

24. A telecommunications data accessing device substantially as hereinbefore described with reference to the accompanying drawings. 4. *25. A telecommunications link access system substantially as hereinbefore described with reference to the accompanying drawings. 911129,dbwspc37jtdom.ztus23 -24-

26. The steps, features, compositions and comnpoundsref r indicated in the specification and/or claims of this am ia ,individually or collectively, and any and al cnmbin any two or more of said steps or features. DATED this 29th clay of November, 1991. '7fT4s O By its Patent Attorneys DAVIES COLLISON CAVE R44 Sao. .o104 Sr see. e 911129,dbwspc37cIccam.as,24 ABSTRACT A telecommunications data accessing device comprising means (44,46) for S" connecting the device to a link (10) of a telecommunications network, means (48) for accessing a predetermined data channel (40) received on the link and means (6) for transmitting data on the channrel (40) to a remote analysis centre (300), the device being able to access and transmit the data without affecting a telecommunications terminal connected to said link U 0* *0 S PS 911129,dbwspe37,tdcc.auM.I,1