AU640727B2 - Device for inserting information bits into a specific frame structure - Google Patents

Device for inserting information bits into a specific frame structure Download PDF

Info

Publication number
AU640727B2
AU640727B2 AU68434/90A AU6843490A AU640727B2 AU 640727 B2 AU640727 B2 AU 640727B2 AU 68434/90 A AU68434/90 A AU 68434/90A AU 6843490 A AU6843490 A AU 6843490A AU 640727 B2 AU640727 B2 AU 640727B2
Authority
AU
Australia
Prior art keywords
bit
bits
justification
memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU68434/90A
Other languages
English (en)
Other versions
AU6843490A (en
Inventor
Philippe Regent
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel CIT SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel CIT SA filed Critical Alcatel CIT SA
Publication of AU6843490A publication Critical patent/AU6843490A/en
Application granted granted Critical
Publication of AU640727B2 publication Critical patent/AU640727B2/en
Anticipated expiration legal-status Critical
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/12Arrangements providing for calling or supervisory signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/07Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Holo Graphy (AREA)
  • Mirrors, Picture Frames, Photograph Stands, And Related Fastening Devices (AREA)
  • Communication Control (AREA)
  • Television Systems (AREA)
AU68434/90A 1989-12-27 1990-12-21 Device for inserting information bits into a specific frame structure Expired AU640727B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8917256 1989-12-27
FR8917256A FR2656479B1 (enrdf_load_stackoverflow) 1989-12-27 1989-12-27

Publications (2)

Publication Number Publication Date
AU6843490A AU6843490A (en) 1991-07-04
AU640727B2 true AU640727B2 (en) 1993-09-02

Family

ID=9389013

Family Applications (1)

Application Number Title Priority Date Filing Date
AU68434/90A Expired AU640727B2 (en) 1989-12-27 1990-12-21 Device for inserting information bits into a specific frame structure

Country Status (8)

Country Link
EP (1) EP0435130B1 (enrdf_load_stackoverflow)
JP (1) JPH0761056B2 (enrdf_load_stackoverflow)
AT (1) ATE120909T1 (enrdf_load_stackoverflow)
AU (1) AU640727B2 (enrdf_load_stackoverflow)
CA (1) CA2033156C (enrdf_load_stackoverflow)
DE (1) DE69018411T2 (enrdf_load_stackoverflow)
ES (1) ES2071736T3 (enrdf_load_stackoverflow)
FR (1) FR2656479B1 (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04137993A (ja) * 1990-09-28 1992-05-12 Fujitsu Ltd サブレート時間スイッチ
FR2680062A1 (fr) * 1991-07-31 1993-02-05 Cit Alcatel Dispositif d'extraction d'elements binaires d'information d'une structure de trame determinee.
ES2046106B1 (es) * 1992-02-18 1996-11-16 Estandard Electrica S A Metodo de realizacion de circuitos alineadores inmunes a los deslizamientos ocurridos en la memoria elastica de recepcion.
FI90484C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän elastisen puskurimuistin täyttöasteen valvomiseksi
FI90485C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä osoittimia sisältävien kehysrakenteiden purkamiseksi ja muodostamiseksi
FI90486C (fi) * 1992-06-03 1999-08-11 Nokia Telecommunications Oy Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä suoritettavan elastisen puskuroinnin toteuttamiseksi
AU664097B2 (en) * 1992-06-26 1995-11-02 Hewlett-Packard Australia Limited A justifier and de-justifier
US5327126A (en) * 1992-06-26 1994-07-05 Hewlett-Packard Company Apparatus for and method of parallel justifying and dejustifying data in accordance with a predetermined mapping

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4884268A (en) * 1987-11-09 1989-11-28 Nec Corporation Repeater arrangement capable of avoiding accumulation of stuff jitters
US5014271A (en) * 1988-03-25 1991-05-07 Fujitsu Limited Pulse insertion circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2641488C2 (de) * 1976-09-15 1978-11-16 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung zum Phasenausgleich bei PCM-Vermittlungsstellen
DE3600795A1 (de) * 1986-01-14 1987-07-16 Ant Nachrichtentech Digitales nachrichtenuebertragungssystem

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4884268A (en) * 1987-11-09 1989-11-28 Nec Corporation Repeater arrangement capable of avoiding accumulation of stuff jitters
US5014271A (en) * 1988-03-25 1991-05-07 Fujitsu Limited Pulse insertion circuit

Also Published As

Publication number Publication date
FR2656479B1 (enrdf_load_stackoverflow) 1994-04-08
EP0435130B1 (fr) 1995-04-05
FR2656479A1 (enrdf_load_stackoverflow) 1991-06-28
ATE120909T1 (de) 1995-04-15
DE69018411T2 (de) 1995-08-03
ES2071736T3 (es) 1995-07-01
EP0435130A1 (fr) 1991-07-03
AU6843490A (en) 1991-07-04
JPH04211535A (ja) 1992-08-03
CA2033156C (fr) 1994-08-16
DE69018411D1 (de) 1995-05-11
CA2033156A1 (fr) 1991-06-28
JPH0761056B2 (ja) 1995-06-28

Similar Documents

Publication Publication Date Title
CA2031054C (en) Inverse multiplexer and demultiplexer techniques
US5172376A (en) Sdh rejustification
EP0788695B1 (en) Method for disassembling and assembling frame structures containing pointers
US4667324A (en) Network multiplex structure
EP0491054B1 (en) Circuit for extracting asynchronous signals
US5287360A (en) Device for inserting information bits into a specific frame structure
AU640727B2 (en) Device for inserting information bits into a specific frame structure
EP0788694B1 (en) Method and equipment for elastic buffering in a synchronous digital telecommunication system
NZ242762A (en) Time switch for time division mutiplex network
US4829518A (en) Multiplexing apparatus having BSI-code processing and bit interleave functions
EP0650652A1 (en) Method for implementing switching in time or space domain
FI90484C (fi) Menetelmä ja laite synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän elastisen puskurimuistin täyttöasteen valvomiseksi
US4101739A (en) Demultiplexer for originally synchronous digital signals internested word-wise
US7688833B2 (en) Synchronous transmission network node
US5305322A (en) Phase alignment circuit for stuffed-synchronized TDM transmission system with cross-connect function
US20060233165A1 (en) Managing data in a subtended switch
JP2002508127A (ja) データストリームの適応および通過接続のための方法および回路装置
KR0168921B1 (ko) 동기식 전송시스템에서 시험액세스를 위한 24x3교차 스위치 회로
JPH05292556A (ja) スイッチシステムおよびスイッチング方法
WO1995010897A1 (en) A buffering method and a buffer
HK1002380B (en) Method for disassembling and assembling frame structures containing pointers
HK1002378B (en) Method and equipment for elastic buffering in a synchronous digital telecommunication system