AU3039099A - Method for producing a decorative item on an integrated circuit card - Google Patents

Method for producing a decorative item on an integrated circuit card

Info

Publication number
AU3039099A
AU3039099A AU30390/99A AU3039099A AU3039099A AU 3039099 A AU3039099 A AU 3039099A AU 30390/99 A AU30390/99 A AU 30390/99A AU 3039099 A AU3039099 A AU 3039099A AU 3039099 A AU3039099 A AU 3039099A
Authority
AU
Australia
Prior art keywords
producing
integrated circuit
circuit card
decorative item
decorative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU30390/99A
Inventor
Stephane Ayala
Didier Elbaz
Laurent Garcia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus SCA
Gemplus Card International SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus SCA, Gemplus Card International SA filed Critical Gemplus SCA
Publication of AU3039099A publication Critical patent/AU3039099A/en
Abandoned legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • G06K19/07747Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B44DECORATIVE ARTS
    • B44CPRODUCING DECORATIVE EFFECTS; MOSAICS; TARSIA WORK; PAPERHANGING
    • B44C5/00Processes for producing special ornamental bodies
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743External electrical contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
AU30390/99A 1998-04-17 1999-03-26 Method for producing a decorative item on an integrated circuit card Abandoned AU3039099A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9805267 1998-04-17
FR9805267A FR2777506B1 (en) 1998-04-17 1998-04-17 METHOD FOR PRODUCING A DECORATIVE ENTITY ON AN INTEGRATED CIRCUIT TYPE CARD
PCT/FR1999/000705 WO1999054845A1 (en) 1998-04-17 1999-03-26 Method for producing a decorative item on an integrated circuit card

Publications (1)

Publication Number Publication Date
AU3039099A true AU3039099A (en) 1999-11-08

Family

ID=9525719

Family Applications (1)

Application Number Title Priority Date Filing Date
AU30390/99A Abandoned AU3039099A (en) 1998-04-17 1999-03-26 Method for producing a decorative item on an integrated circuit card

Country Status (4)

Country Link
EP (1) EP1073997A1 (en)
AU (1) AU3039099A (en)
FR (1) FR2777506B1 (en)
WO (1) WO1999054845A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2720175A1 (en) * 2012-10-09 2014-04-16 Gemalto SA Electronic module, device with electronic module and manufacturing method.
FR3040516B1 (en) * 2015-08-27 2017-09-15 Linxens Holding METHOD FOR MANUFACTURING AN ELECTRIC CIRCUIT, ELECTRIC CIRCUIT OBTAINED BY THIS METHOD AND CHIP CARD COMPRISING SUCH AN ELECTRICAL CIRCUIT
EP3889839A1 (en) 2020-03-31 2021-10-06 Thales Dis France Sa Method for optimised graphic customisation of smart card modules and module obtained
FR3110734B1 (en) 2020-05-20 2022-07-29 Smart Packaging Solutions Electronic module for smart card with security patterns

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994002912A1 (en) * 1992-07-23 1994-02-03 Deutsche Thomson-Brandt Gmbh Contact, product therewith and device for accepting this product
FR2695234B1 (en) * 1992-08-26 1994-11-04 Gemplus Card Int Method of marking a smart card.
DE19630049A1 (en) * 1996-07-25 1998-01-29 Siemens Ag Chip card with a contact zone and method for producing such a contact zone

Also Published As

Publication number Publication date
FR2777506B1 (en) 2000-06-30
FR2777506A1 (en) 1999-10-22
WO1999054845A1 (en) 1999-10-28
EP1073997A1 (en) 2001-02-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase