AU2811301A - Apparatus for converting video format and method therefor - Google Patents
Apparatus for converting video format and method therefor Download PDFInfo
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- AU2811301A AU2811301A AU28113/01A AU2811301A AU2811301A AU 2811301 A AU2811301 A AU 2811301A AU 28113/01 A AU28113/01 A AU 28113/01A AU 2811301 A AU2811301 A AU 2811301A AU 2811301 A AU2811301 A AU 2811301A
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- video data
- format
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/44—Colour synchronisation
- H04N9/465—Synchronisation of the PAL-switch
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/64—Circuits for processing colour signals
- H04N9/73—Colour balance circuits, e.g. white balance circuits or colour temperature control
Description
P/00/011 Regulation 3.2
AUSTRALIA
Patents Act 1990
ORIGINAL
COMPLETE SPECIFICATION STANDARD PATENT Invention Title: "APPARATUS FOR CONVERTING VIDEO FORMAT AND METHOD THEREFOR" The following statement is a full description of this invention, including the best method of performing it known to me/us: *0 0 0 0 0 0 APPARATUS FOR CONVERTING VIDEO FORMAT AND METHOD THEREFOR BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting the format of video data and a method therefor, and more particularly, to an apparatus for converting the format of video data into a predetermined display format regardless of the format of input video data in a broadcasting receiver including a video decoder such as a moving picture experts group (MPEG) decoder and a method therefor.
2. Description of the Related Art An MPEG decoder decodes a video signal, received in a compressed form.
Broadcasting receivers that employ the MPEG decoder include a digital broadcasting receiver such as a high definition television (HDTV).
Displays used by digital broadcasting receivers include a flat panel display 15 such as liquid crystal display (LCD), a plasma display panel (PDP), a digital micro mirror device (DMD), and a ferro-electric liquid crystal display (FLCD). However, since the above-mentioned flat panel displays have a fixed number of pixels, they cannot adaptively correspond to video data having various resolutions. Therefore, it is necessary to employ a format converter for converting the resolution of the video data into the resolution used by the display without damaging original picture quality.
However, the currently suggested format converting apparatus is designed in consideration of only a digital television standard signal that is defined by the advanced television system committee (ATSC) specification of the United States.
Therefore, a normal format conversion is not performed in areas in which broadcasting (such as PAL) signals other than the signal defined by the ATSC specification are provided. Therefore, digital broadcasting receivers that employ format converting apparatuses that are suitable for the corresponding areas must be additionally manufactured and provided to the areas in which the broadcasting signals other than the signal defined by the ATSC specification are provided.
SUMMARY OF THE INVENTION To solve the above problems, it is an object of the present invention to provide an apparatus for converting the format of video data, which is capable of converting the format of video data into a predetermined display format regardless of the format of an input video signal, and a method therefor.
It is another object of the present invention to provide an apparatus for converting the format of video data, which is capable of converting the format of standard- definition (SD) and high definition (HD) video data of broadcasting (such as PAL) signals other than a signal defined by the advanced television system committee (ATSC) specification as well as the format of SD and HD video data defined by the ATSC specification into a predetermined display format, and a method therefor.
***Accordingly, to achieve the above objects, there is provided an apparatus for converting the format of video data of a broadcasting receiver comprising a video decoder, the apparatus comprising an interface module for interfacing with the video decoder so as to receive video data regardless of the format of the video data transmitted from the video decoder, a memory for storing standard definition (SD) video data having an interlace format and motion detection information corresponding to the SD video data, a first format converter for converting the 20 format of the video data transmitted from the interface module into a predetermined SD interlace format and transmitting the video data to the memory, an interlace/progressive converter (IPC) for converting the format of the video data transmitted from the memory into a progressive format using the video data and motion detection information, Which are stored in the memory, a second format converter for converting the format of the video data transmitted from the interface module or the IPC into a display format set in the broadcasting receiver, and a display processing module for providing timing signals required for the operations of the interface module, the memory, the first format converter, the IPC, and the second format converter according to the display format and the format of the video data received through the interface module.
The apparatus for converting the format of video data preferably further comprises a switch for selectively transmitting the video data transmitted from the interface module to the first format converter and the second format converter according to the format of the received video data and the display format and a control unit for controlling the operation of the switch according to the format of the received video data and the display format.
The video data that can be received from the video decoder comprises video data having SD and HD formats according to broadcasting signals excluding the broadcasting signal defined by the advanced television system committee (ATSC) specification as well as video data having SD and HD formats according to the ATSC specification and the display format is determined by the display resolution of the display device installed in the broadcasting receiver.
There is provided a method for converting the format of video data of a S broadcasting receiver comprising a video decoder, the method comprising the steps of determining whether the format of video data received from the video decoder is SD or HD, determining whether a display format set in the broadcasting receiver is SD or HD when the format of the video data. is SD, (c) converting the format of the received video data into a progressive format when the display format is HD, converting the format of the video data, which is converted into the progressive format, into the set display format, and (e) converting the format of the video data into the set display format and outputting the video data when the format of the video data is HD or when the display format Sis SD.
BRIEF DESCRIPTION OF THE DRAWING(S) The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which: FIG. 1 is a block diagram showing the function of an apparatus for converting the format of video data according to the present invention; FIG. 2 is a detailed block diagram showing the interlace/progressive converter (IPC) shown in FIG. 1; FIG. 3 is a detailed block diagram showing the display processing module shown in FIG. 1; and FIG. 4 is a flowchart showing the operation of a method for converting the format of video data according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S) FIG. 1 is a block diagram showing the function of an apparatus for converting the format of video data according to the present invention, which is applied to a broadcasting receiver including a moving picture experts group (MPEG) video decoder.
Referring to FIG. 1, the apparatus for converting the format of video data according to the present invention includes an MPEG video decoder interface module 101, a control unit 103, a switch 105, a first format converter 107, a memory control unit 109, a synchronous dynamic random access memory (SDRAM) 111, an interlace/progressive converter (IPC) 113, a second format S converter 115, and a display processing module 117.
o:o The MPEG video decoder interface module 101 interfaces with an MPEG video decoder (not shown) so as to receive video data that is decoded by and transmitted from the MPEG video decoder and to transmit the received video data to a next stage. The receivable video data include video data having standard definition (SD) and high definition (HD) formats which are not defined by the advanced television system committee (ATSC) specification as well as video data o 20 having SD and HD formats which are defined by the ATSC specification.
In detail, the MPEG video decoder interface module 101 transmits to the MPEG video decoder a horizontal synchronous signal Hsync and field information field, which are based on the horizontal synchronous signal Hsync, a vertical synchronous signal Vsync, and the field information field, which are suitable for the display format specification transmitted from the display processing module 117. Accordingly, the video data transmitted from the MPEG video decoder (not shown) and header information corresponding thereto are received.
Since the format of the receivable video data is not defined as mentioned above, video data having the SD format such as 720x576i and 720x288p according to a phase alternation by line (PAL) broadcasting method and 720x480i according to the ATSC specification, can be the receivable video data. Here, i and p mean interlace and progressive, respectively. Also, video data having the HD format such as 7 20x576p according to the PAL broadcasting method and 1920x1080i according to the ATSC specification can be the receivable video data.
The received video data.has a format in which YUV is 4:2:0 or 4:2:2.
Information on the format of the currently transmitted video data exists in the header information. The header information is received in the form of a bit stream through the same path as the received video data.
When the data including the above-mentioned video data and the header information are received from the MPEG video decoder, the MPEG video decoder interface module 101 separates the video data from the header information using a header separator 101_1. A header decoder 101 2 decodes the header information separated by the header separator 101_1 and registers the header information. Then, the registered header information is transmitted to the control unit 103.
The video data separated by the header separator 101 1 is active data having a YUV format. The MPEG video decoder interface module 101 buffers the video data on the basis of the synchronous signal and the field information that are transmitted from the display processing module 117 and transmits the buffered video data to the switch 105. The reason why the video data is buffered is to solve the problem of asynchronization between the MPEG video decoder and the MPEG video decoder interface module 101. Namely, the video data transmitted from the MPEG video decoder is buffered so as to be synchronized with the display format.
The control unit 103 for controlling the function of the apparatus for a converting the format of video data according to the present invention, includes a function for generating a synchronous signal, which is required for operation and a registering function. In particular, the format of the currently received video data is determined by the decoded header information, which is transmitted from the MPEG video decoder interface module 1.01, and the operation of the switch 105 is controlled according to the determination result and the display format of the corresponding broadcasting receiver.
Namely, when the format of the currently received video data is HD and the display format is HD, when the format of the currently received video data is SD and the display format is SD, and when the format of the currently received video data is HD and the display format is SD, the control unit 103 controls the operation of the switch 105 so that the video data output from the MPEG video decoder interface module 101 is transmitted to the second format converter 115.
When the format of the currently received video data is SD and the display format is HD, the control unit 103 controls the operation of the switch 105 so that the video data output from the MPEG video decoder interface module 101 is transmitted to the first format converter 107. The display format is determined by the display resolution of the display employed in the corresponding broadcasting receiver.
The control unit 103 (to which the registering function is added) provides information on the format of the currently received video data and information on i the display format to the display processing module 117 and controls the memory control unit 109 so that the memory control unit 109 can control the recording mode and the reading mode of the SDRAM 111 without conflict. Information on the number of pixels and information on a frame transmission rate are included in the information on the display format.
The first format converter 107 converts the format of the video data transmitted from the MPEG video decoder interface module 101 through the switch 105 into a predetermined SD interlace format. The predetermined SD is the SD defined by the ATSC specification.
°The memory control unit 109 performs the recording mode of the SDRAM 111 so that the video data, whose format is converted into the interlace format by the first format converter 107, can be recorded in the corresponding region of the SDRAM 111. At this time, the memory control unit 109 interfaces with the first format converter 107 so that the YUV format becomes 4:2:2.
The SDRAM 111 is a memory in which video data of at least three or five fields and motion detection information corresponding to the video data of at least three or five fields can be recorded. The memory control unit 109 and the SDRAM 111 can be designed to be included outside the apparatus for converting the format according to the present invention.
When reading of the video data and the motion detection information, which are stored in the SDRAM 111, is requested by the IPC 113, the memory control unit 109 interfaces with the IPC 113 and performs the reading mode of the SDRAM 111.
The IPC 113 converts the format of the corresponding video data into the progressive format by the video data and the motion detection information transmitted through the memory control unit 109. Namely, the IPC 113 includes an IPC field controller 201, a memory control unit interface 203, a video data transmission processor 205, a motion detection information transmission processor 207, an IPC processor 209, and a control signal generator 211 as shown in FIG. 2 and converts the format of the corresponding video data into the progressive format.
As mentioned above, the IPC field controller 201 interfaces with the S memory control unit 109 and controls the read timing of the video data stored in I-V: the SDRAM 111 so that the IPC 113 can operate. The IPC field controller 201 performs a frame transmission rate conversion function so that the number of 0:0'.015 frames per second of video data input to the IPC 201 is equal to the number of frames per second of video data whose format is converted into the progressive S" format and output. The frame transmission rate conversion function is realized by repeating or skipping a previous field and a next field, which exist in the SDRAM 111 on the basis of the current field.
The memory control unit interface 203 is controlled by the IPC field controller 201 and interfaces with the memory control unit 109 so as to receive the 0 video data and the motion detection information, which are read from the SDRAM 111.
The video data transmission processor 205 sequentially transmits the video data of at least three fields, which is transmitted from the memory control unit interface 203, to the IPC processor 209. At thistime, the transmitted video data has the YUV format.
The motion detection information transmission processor 207 transmits the motion detection information transmitted from the memory control unit interface 203 to the IPC processor 209 and, when motion detection information newly detected for IPC processing is received from the IPC processor 209, transmits the motion detection information to the memory control unit interface 203 and records the motion detection information in the SDRAM 111.
Page(s) were not lodged with this application The display processing module 117 provides the timing signal required for the operation of the apparatus for converting the format of video data according to the present invention, according to the display format information provided by the control unit 103 and the information on the format of the currently received video data. The display processing module 117 converts the YUV format of the video data, which is transmitted from the second format converter 115, into the YUV format in the ratio of 4:4:4 and outputs the video data or converts the video data into R, G, and B chrominance signals and outputs the chrominance signals. At this time, the display processing module 117 also converts the frame transmission rate of the output video data into the frame transmission rate according to the display format.
S
The display processing module 117 includes a parameter setting unit 301, a timing signal generator 303, and a color matrix converter 305 as shown in FIG. 3 and performs the above-mentioned operation.
15 The parameter setting unit 301 sets the parameters required for displaying the received video data on the basis of the information provided by the control unit S• 103. The timing signal generator 303 generates a timing signal required for driving the apparatus for converting the format of video data using the parameter transmitted from the parameter setting unit 301. The timing signal generator 303 provides the operation timings of the MPEG video decoder interface module 101, S the switch 105, the first format converter 107, the IPC 113, the second format 0o°0 converter 115, and the color matrix converter 305.
The color matrix converter 305 convertsthe video data transmitted from the second format converter 115 into R, G, and B chrominance signals, in which the ratio of a luminance signal to a color difference signal is 4:4:4 as mentioned above, or converts only the ratio of the luminance signal to the color difference signal into 4:4:4 and outputs the video data, by the timing signal provided by the timing signal generator 303. At this time, the color matrix converter 305 also converts the frame transmission rate into a frame transmission rate which is suitable for the display format, in synchronization with the timing signal provided by the timing signal generator 303.
The MPEG video decoder interface module 101, the first format converter 107, the IPC 113, and the second format converter 115 are formed so that data is processed in the YUV format, in which the ratio of the luminance signal to the color difference signal is no more than 4:2:2, before the ratio of the luminance signal to the color difference signal of the video data is converted into 4:4:4 at the display processing module 117. Accordingly, it is possible to reduce the amount of hardware of the apparatus for converting the format of video data.
FIG. 4 is a flowchart showing the operation of a method for converting the format of video data according to the present invention. As mentioned in FIG. 1, when decoded data is received from a video decoder such as an MPEG video decoder, it is determined whether the currently received video data is SD or HD in the step 401 by analyzing the header-information received together with the video data as described in FIG. 1.
When it is determined that the currently received video data is SD, the display format is determined in the step 402. When it is determined that the display format is HD, IPC processing is performed on the received video data in 15 the step 403. The IPC processing is performed using the video data of an adjacent field and the corresponding motion detection information after converting the format of the video data into the interlace format and storing the video data in a memory such as the SDRAM 111 as described in FIG. 1. When the format of o the video data is converted into the progressive format, the format of the video data is converted into the set display format in the step 404 and the video data is converted into the R, G, and B chrominance signals in the step 405. At this time, when the frame transmission rate of the received video data is different from the frame transmission rate of the video data to be displayed, the frame transmission rate of the received video data is converted into the frame transmission rate of the display format.
When it is determined in the step 401 that the format of the received video data is HD and when it is determined in the step 402 that the display format is SD, the format of the received video data is converted into the set display format in the step 404 and the above-mentioned processing is performed in the step 405.
As mentioned above, according to the present invention, since it is possible to convert the format of the SD and HD video data (the PAL 576i/p), which are not defined by the ATSC specification, as well as the standard video data defined by the United States ATSC specification to be suitable for the set display format (or the display resolution), a designer can construct the digital broadcasting receiver, which employs various displays such as a flat plate display device such as a plasma display panel (PDP) and liquid crystal display and a cathode ray tube (CRT) regardless of the format of the broadcasting signal of the corresponding area.
When the SD video data is to be displayed on an HD display, it is possible to maintain HD, which is the original characteristic of the digital broadcasting receiver, by operating a method obtained by mixing the two dimensional progressive format converting method with the three dimensional progressive format converting method.
Also, it is possible to reduce the amount of hardware by processing data to S have the YUV format, in which the ratio of the luminance signal to the color difference signal is no more than 4:2:2, before outputting the video data whose format is finally converted.
ooeoo .e .b ,o o* a 4
Claims (8)
- 2. The apparatus of claim 1, wherein the interface module further 2 comprises: 3 a separator for separating the video data and header information 4 corresponding to the video data included in data when the data is received from s the video decoder; and 6 a header decoder for decoding the header information separated by the 7 separator. 1 3. The apparatus of claim 2, wherein the apparatus for converting the 2 format of video data further comprises: 3 a switch for selectively transmitting the video data transmitted from the 4 interface module to the first format converter and the second format converter s according to the format of the received video data and the display format; and 6 a control unit for controlling the operation. of the switch according to the 7 format of the received video data and the display format. 1 4. The apparatus of claim 3, wherein the control unit further comprises 2 the function of providing information on the format of the received video data, 3 which is determined by analyzing the decoded header information transmitted from 4 the header decoder, and the display format information to the display processing module. 1 5. The apparatus of claim 3, wherein the display processing module 2 comprises: S•3 a parameter setting unit for setting a parameter required for displaying the 4 video data on the basis of the information transmitted from the control unit; s a timing signal generator for generating a timing signal required for driving 6 the apparatus for converting the format of video data by the parameter transmitted 7 from the parameter setting unit; and 8 a color matrix converter for controlling the ratio of a luminance signal to a 9 color difference signal of the video data transmitted from the second format ooo* 1o converter by a signal provided by the timing signal generator and controlling the video data to have a frame transmission rate which is suitable for the display format. 1 6. The apparatus of claim 5, wherein the color matrix converter further 2 performs the function of controlling the ratio of the luminance signal to the color 3 difference signal of the output video data to be 4:4:4, converting the video data 4 into R, G, and B chrominance signals, and outputting the chrominance signals.
- 7. The apparatus of claim 1, wherein the IPC comprises: 2 a controller for controlling read timing of the memory; 3 an interface controlled by the controller, the interface for interfacing with the 4 memory so as to receive the video data transmitted from the memory; s an interlace/progressive conversion processor for selectively outputting the 6 result obtained by performing two dimensional interlace/progressive conversion on 7 the video data or the result obtained by performing three dimensional 8 interlace/progressive conversion on the video data according to newly detected 9 motion detection information in consideration of the motion detection information transmitted from the interface and interpolating the video data; and 11 a motion detection information transmission processor for transmitting the 12 newly detected motion detection information to the interface so that the motion 13 detection information newly detected is stored in the memory. 1 8. The apparatus of claim 7, wherein the controller further comprises 2 the function of converting the frame transmission rate of the video data so that the 3 number of input frames of the IPC is equal to the number of output frames of the IPC.
- 9. The apparatus of claim 1, wherein the apparatus for converting the 2 format of video data further comprises a memory control unit for performing 3 interfacing data transmission between the first format converter and the memory 4 and between the second format converter and the memory.
- 10. The apparatus of claim 1, wherein the video data that can be 2 received from the video decoder comprises video data having SD and HD formats 3 according to broadcasting signals excluding the broadcasting signal defined by the 4 advanced television system committee (ATSC) specification as well as video data s having SD and HD formats according to the ATSC specification and the display 6 format is determined by the display resolution of the display device installed in the 7 broadcasting receiver. 1 11. The apparatus of claim 10, wherein the broadcasting signals 2 excluding the broadcasting signal defined by the ATSC specification follow a 3 phase alternation by line (PAL) broadcasting method. 1 12. The apparatus of claim 1, wherein the apparatus for converting the 2 format of video data comprises the interface module, the memory, the first format 3 converter, the IPC, and the second format converter so that the video data has the 4 format of video data, in which the ratio of a luminance signal to a color difference s signal is no more than 4:2:2, before the display processing module performing a 6 process for outputting the corresponding video data to have the display format.
- 13. The apparatus of claim 1, wherein the memory is comprised of a 2 synchronous dynamic random access memory (SDRAM), in which video data of at 3 least three or five fields and motion detection information corresponding the video data are stored. 1 14. A method for converting the format of video data of a broadcasting 2 receiver comprising a video decoder, the method comprising the steps of: 3 determining whether the format of video data received from the video 4 decoder is SD or HD; s determining whether a display format set in the broadcasting receiver is 6 SD or HD when the format of the video data is SD; 7 converting the format of the received video data into a progressive S•8 format when the display format is HD; 9 converting the format of the video data, which is converted into the progressive format, into the set display format; and converting the format of the video data into the set display format and 12 outputting the video data when the format of the video data is HD or when the 13 display format is SD. 1 15. The method of claim 14, wherein the video data that can be received 2 from the video decoder comprises video data having SD and HD formats 3 according to broadcasting signals excluding the broadcasting signal defined by the 4 advanced television system committee (ATSC) specification as well as video data s having SD and HD formats according to the ATSC specification and the display format is determined by the display resolution of the display device installed in the broadcasting receiver.
- 16. The method of claim 14, wherein the steps and further comprise the step of converting the frame transmission rate of the video data into the frame transmission rate of the video data to be displayed when the frame transmission rate of the received video data is different from the frame transmission rate of the video data to be displayed.
- 17. An apparatus for converting the format of video data as herein described with reference to figures 1, 2 and 3.
- 18. A method for converting the format of video data as herein described with reference to figure 4. Dated this Nineteenth Day of March 2001 SAMSUNG ELECTRONICS CO., LTD By Their Patent Attorneys FISHER ADAMS KELLY
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR00-48991 | 2000-08-23 | ||
| KR10-2000-0048991A KR100385975B1 (en) | 2000-08-23 | 2000-08-23 | Apparatus for converting video format and method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| AU2811301A true AU2811301A (en) | 2002-02-28 |
| AU770732B2 AU770732B2 (en) | 2004-03-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU28113/01A Ceased AU770732B2 (en) | 2000-08-23 | 2001-03-19 | Apparatus for converting video format and method therefor |
Country Status (2)
| Country | Link |
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| KR (1) | KR100385975B1 (en) |
| AU (1) | AU770732B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100429993B1 (en) * | 2001-09-12 | 2004-05-03 | 엘지전자 주식회사 | Compensation method and apparatus for system clock signal of video display processor |
| KR100474489B1 (en) * | 2002-08-14 | 2005-03-10 | 삼성전자주식회사 | HDTV with compansation horizontal synchronizing signal timming |
| KR100677545B1 (en) | 2004-12-29 | 2007-02-02 | 삼성전자주식회사 | Method for data processing using a plurality of data processing apparatus, and recoding medium storing a program for implementing the method |
| KR20070048025A (en) * | 2005-11-03 | 2007-05-08 | 삼성전자주식회사 | Apparatus and method for outputting multimedia data |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06268949A (en) * | 1993-03-12 | 1994-09-22 | Sony Corp | Flat display device and its drive circuit |
| US5610661A (en) * | 1995-05-19 | 1997-03-11 | Thomson Multimedia S.A. | Automatic image scanning format converter with seamless switching |
| KR0156186B1 (en) * | 1995-09-05 | 1998-11-16 | 구자홍 | Decoder apparatus and method of digital image data |
| KR970068580A (en) * | 1996-03-29 | 1997-10-13 | 구자홍 | Digital image format converter |
| KR100351816B1 (en) * | 2000-03-24 | 2002-09-11 | 엘지전자 주식회사 | Apparatus for conversing format |
-
2000
- 2000-08-23 KR KR10-2000-0048991A patent/KR100385975B1/en not_active IP Right Cessation
-
2001
- 2001-03-19 AU AU28113/01A patent/AU770732B2/en not_active Ceased
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| KR20020015862A (en) | 2002-03-02 |
| KR100385975B1 (en) | 2003-06-02 |
| AU770732B2 (en) | 2004-03-04 |
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